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MITO 8M SOM/MITO 8M Hardware/Pinout Table

554 bytes added, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains the pinout === Connectors description of ===In the following table are described all available connectors integrated on MITO 8M module, grouped in two tables (odd and even pins) that report the SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin mapping of the 204|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-pin SOAD-DIMM TR|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M connectorpinout specifications.See the images below for reference:
[[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]]
[[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
 
Below a detailed description of the pinout, grouped in the following tables:
* two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
* a dedicated tables for J4 one-piece connector
* a dedicated tables for J5 one-piece connector
 
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {| class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge* SV.<x>: pin connected to voltage supervisor(TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|NVCC_1V8
|I/O
|Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
|NVCC_1V8
|I/O
|Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|GPIO1_IO01
| rowspan="3" |J1.41
| rowspan="3" |SPDIF_EXT_CLK
| rowspan="3" |CPU.SPDIF_EXT_CLKSPDIF_EXT_CLK
| rowspan="3" |E6
| rowspan="3" |NVCC_3V3
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|GPIO1_IO13
|-
|ALT1
|ENET1_1588_EVENT0_INENET1_1588_EVENT0_IN
|-
|ALT5
|-
|ALT1
|ENET1_1588_EVENT0_OUTENET1_1588_EVENT0_OUT
|-
|ALT5
|SDMA2_EXT_EVENT0SDMA2_EXT_EVENT0
|-
| rowspan="3" |J1.55
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt,  do not connectPulled-up to NVCC_3V3
|ALT0
|GPIO1_IO05
|-
|ALT1
|ENET1_1588_EVENT1_INENET1_1588_EVENT1_IN
|-
|ALT5
|-
|ALT1
|ENET1_1588_EVENT1_OUTENET1_1588_EVENT1_OUT
|-
|ALT5
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable,  do not connect
|ALT0
|GPIO1_IO06
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| rowspan="2" |J1.99
| rowspan="2" |SD2_RST_B
| rowspan="2" |CPU.SD2_RESET_BSD2_RESET_B
| rowspan="2" |R22
| rowspan="2" |NVCC_3V3
|J1.101
|HDMI_DDC_SCL
|CPU.HDMI_DDC_SCLHDMI_DDC_SCL
|R3
|VDD_PHY_1V8
|J1.103
|HDMI_DDC_SDA
|CPU.HDMI_DDC_SDAHDMI_DDC_SDA
|P3
|VDD_PHY_1V8
|J1.105
|HDMI_AUX_N
|CPU.HDMI_AUX_NHDMI_AUX_N
|V2
| -
|D
|connected with capacitor in series
|
|
|J1.107
|HDMI_AUX_P
|CPU.HDMI_AUX_PHDMI_AUX_P
|V1
| -
|D
|connected with capacitor in series
|
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|J1.111
|HDMI_TX_M_LN_3
|CPU.HDMI_TX_M_LN_3HDMI_TX_M_LN_3
|M2
| -
|D
|connected with capacitor in series
|
|
|J1.113
|HDMI_TX_P_LN_3
|CPU.HDMI_TX_P_LN_3HDMI_TX_P_LN_3
|M1
| -
|D
|connected with capacitor in series
|
|
|J1.115
|HDMI_TX_M_LN_0
|CPU.HDMI_TX_M_LN_0HDMI_TX_M_LN_0
|T2
| -
|D
|connected with capacitor in series
|
|
|J1.117
|HDMI_TX_P_LN_0
|CPU.HDMI_TX_P_LN_0HDMI_TX_P_LN_0
|T1
| -
|D
|connected with capacitor in series
|
|
|J1.119
|HDMI_TX_M_LN_1
|CPU.HDMI_TX_M_LN_1HDMI_TX_M_LN_1
|U1
| -
|D
|connected with capacitor in series
|
|
|J1.121
|HDMI_TX_P_LN_1
|CPU.HDMI_TX_P_LN_1HDMI_TX_P_LN_1
|U2
| -
|D
|connected with capacitor in series
|
|
|J1.123
|HDMI_TX_M_LN_2
|CPU.HDMI_TX_M_LN_2HDMI_TX_M_LN_2
|N1
| -
|D
|connected with capacitor in series
|
|
|J1.125
|HDMI_TX_P_LN_2
|CPU.HDMI_TX_P_LN_2HDMI_TX_P_LN_2
|N2
| -
|D
|connected with capacitor in series
|
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|UART2_TX
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|UART2_RXD
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|}
===Pinout Table SODIMM J1 EVEN pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
| -
|S
|Absolute maximum ratings 5.25V
|
|
| -
|S
|Absolute maximum ratings 5.25V
|
|
|}
===Pinout Table ONE PIECE J4 pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA7
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA6
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA5
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA4
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA3
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA0
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA0
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7
|
|}
 ===Pinout Table ONE PIECE J5 pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|ALT5
|GPIO5_IO21
|}
 
===Pinout Table JD5 pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
|-
|JD5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|JD5.2
|EEPROM_WP
|Internal EEPROM Write Protect
| -
|NVCC_3V3
|I
|
|
|
|-
|JD5.3
|NC
|Not Connected
| -
| -
|Z
|
|
|
|-
|JD5.4
|JTAG_TCK
|CPU.JTAG_TCK
|T5
|NVCC_3V3
|I
|internal pull-up 10k to NVCC_3V3
|
|
|-
|JD5.5
|JTAG_TMS
|CPU.JTAG_TMS
|V5
|NVCC_3V3
|I
|
|
|
|-
|JD5.6
|JTAG_TDO
|CPU.JTAG_TDO
|U5
|NVCC_3V3
|O
|
|
|
|-
|JD5.7
|JTAG_TDI
|CPU.JTAG_TDI
|W5
|NVCC_3V3
|I
|
|
|
|-
|JD5.8
|JTAG_nTRST
|CPU.JTAG_TRST_B
|U6
|NVCC_3V3
|I
|
|
|
|-
|JD5.9
|CPU_PORn
|CPU.POR_B
PMIC.RESETMCU
|W20
3
|NVCC_SNVS
|I/O
|internal pull-up 100k to NVCC_SNVS
|
|
|-
|JD5.10
|NVCC_3V3
|NVCC_3V3
| -
|<nowiki>-</nowiki>
|S
|
|
|
|}
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