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MITO 8M SOM/MITO 8M Hardware/Pinout Table

5,403 bytes added, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains the pinout === Connectors description of ===In the following table are described all available connectors integrated on MITO 8M module, grouped in two tables (odd and even pins) that report the SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin mapping of the 204|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-pin SOAD-DIMM TR|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M connectorpinout specifications.See the images below for reference:
[[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]]
[[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
 
Below a detailed description of the pinout, grouped in the following tables:
* two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
* a dedicated tables for J4 one-piece connector
* a dedicated tables for J5 one-piece connector
 
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {| class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge* SV.<x>: pin connected to voltage supervisor(TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|GPIO1_IO01
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|GPIO1_IO13
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3
|ALT0
|GPIO1_IO05
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|GPIO1_IO06
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|}
===Pinout Table SODIMM J1 EVEN pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki>Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02
|-
| rowspan="2" |J1.54
(NAND on board)| rowspan="2" |SD1_STROBEGPIO1_IO10| rowspan="2" |CPU.SD1_STROBEGPIO1_IO10| rowspan="2" |T24M7
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |Internally used for ETH PHY interrupt, do not connect
|ALT0
|USDHC1_STROBE GPIO1_IO10
|-
|ALT5|GPIO2_IO11|-|J1.54(eMMC on board)|SD1_STROBE|CPU.SD1_STROBE|T24|NVCC_1V8|I/O|Internally used for eMMC, do not connect|ALT1|USB1_OTG_ID
|-
|J1.56
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|ALT5
|GPIO3_IO00
|-
| rowspan="2" |J1.128
(NAND on board)
| rowspan="2" |SD1_CLK
| rowspan="2" |CPU.SD1_CLK
| rowspan="2" |L25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC1_CLK
|-
|ALT5
|GPIO2_IO00
|-
| rowspan="3" |J1.128
(eMMCon board)| rowspan="3" |NAND_CE0_B // SD1_CLK
| rowspan="3" |CPU.NAND_CE0_B
| rowspan="3" |H19
|GPIO3_IO01
|-
| rowspan="2" |J1.128130(NANDon board)| rowspan="2" |NAND_CE0_B // SD1_CLKSD1_CMD| rowspan="2" |CPU.SD1_CLKSD1_CMD| rowspan="2" |L25L24
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC1_CLKUSDHC1_CMD
|-
|ALT5
|GPIO2_IO00GPIO2_IO01
|-
| rowspan="3" |J1.130(eMMC on board)| rowspan="3" |NAND_CE1_B // SD1_CMD| rowspan="3" |CPU.NAND_CE1_B // CPU.SD1_CMD| rowspan="3" |G21 // L24|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE1_B
|-
|J1.132|NAND_CE2_B // SD1_RST_B|CPU.NAND_CE2_B // CPU.SD1_RST_B|F21 // R24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_A_SS1_B
|-
|J1.134|NAND_CE3_B // SD1_STROBE|CPU.NAND_CE3_B // CPU.SD1_STROBE|H20 // T24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO02
|-
| rowspan="2" |J1.136132(NAND on board)|NAND_CLErowspan="2" |SD1_RST_B|DGNDrowspan="2" |CPU.SD1_RST_B|H21rowspan="2" |R24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_RESET_B
|-
|J1.138|NAND_DATA00 // SD1_DATA0|CPU.NAND_DATA00 // CPU.SD1_DATA0|G20 // M25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO2_IO10
|-
| rowspan="3" |J1.140132(eMMC on board)|NAND_DATA01 // SD1_DATA1rowspan="3" |NAND_CE2_B| rowspan="3" |CPU.NAND_DATA01 // CPU.SD1_DATA1NAND_CE2_B|J20 // M24rowspan="3" |F21|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE2_B
|-
|ALT1|QSPI_B_SS0_B|-|ALT5|GPIO3_IO03|-| rowspan="2" |J1.142134(NAND on board)|NAND_DATA02 // SD1_DATA2rowspan="2" |SD1_STROBE| rowspan="2" |CPU.NAND_DATA02 /SD1_STROBE| rowspan="2" |T24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/ O| rowspan="2" ||ALT0|USDHC1_STROBE|-|ALT5|GPIO2_IO11|-| rowspan="3" |J1.134(eMMC on board)| rowspan="3" |NAND_CE3_B| rowspan="3" |CPU.SD1_DATA2NAND_CE3_B|H22 // N25rowspan="3" |H20|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE3_B|-|ALT1|QSPI_B_SS1_B|-|ALT5|GPIO3_IO034
|-
|J1.144136(NAND on board)|NAND_DATA03 // SD1_DATA3NAND_CLE|CPU.NAND_DATA03 // CPU.SD1_DATA3NAND_CLE|J21 // P25H21|NVCC_1V8 // NVCC_3V3 ???
|I/O
|???Internally used for NAND, do not connect
|
|
|-
|J1.146|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J1.148|NAND_DATA04 // SD1_DATA4|CPU.NAND_DATA04 // CPU.SD1_DATA4|L20 // N24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|||-|J1.150|NAND_DATA05 // SD1_DATA5|CPU.NAND_DATA05 // CPU.SD1_DATA5|J22 // P24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|||-|J1.152|NAND_DATA06 // SD1_DATA6|CPU.NAND_DATA06 // CPU.SD1_DATA6|L19 // R25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|||-|J1.154|NAND_DATA07 // SD1_DATA7|CPU.NAND_DATA07 // CPU.SD1_DATA7|M19 // T25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|||-| rowspan="3" |J1.156136(eMMC on board)| rowspan="3" |NAND_RE_BNAND_CLE| rowspan="3" |CPU.NAND_RE_BNAND_CLE| rowspan="3" |K19H21| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_RE_BRAWNAND_CLE
|-
|ALT1
|QSPI_B_DQSQSPI_B_SCLK
|-
|ALT5
|GPIO3_IO15GPIO3_IO05
|-
| rowspan="2" |J1.158138(NAND on board)| rowspan="2" |NAND_READY_BSD1_DATA0| rowspan="2" |CPU.NAND_READY_BSD1_DATA0| rowspan="2" |K20M25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_READY_BUSDHC1_DATA0
|-
|ALT5
|GPIO3_IO16GPIO2_IO02
|-
| rowspan="3" |J1.138(eMMC on board)| rowspan="3" |NAND_DATA00| rowspan="3" |CPU.NAND_DATA00| rowspan="3" |G20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA00|-|ALT1|QSPI_A_DATA0|-|ALT5|GPIO3_IO06|-| rowspan="2" |J1.160140(NAND on board)| rowspan="2" |NAND_WE_BSD1_DATA1| rowspan="2" |CPU.NAND_WE_BSD1_DATA1| rowspan="2" |K22M24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WE_BUSDHC1_DATA1|-|ALT5|GPIO2_IO0|-| rowspan="3" |J1.140(eMMC on board)| rowspan="3" |NAND_DATA01| rowspan="3" |CPU.NAND_DATA01| rowspan="3" |J20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA01|-|ALT1|QSPI_A_DATA1
|-
|ALT5
|GPIO3_IO17GPIO3_IO07
|-
| rowspan="2" |J1.162142(NAND on board)| rowspan="2" |NAND_WP_BSD1_DATA2| rowspan="2" |CPU.NAND_WP_BSD1_DATA2| rowspan="2" |K21N25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WP_BUSDHC1_DATA2
|-
|ALT5
|GPIO3_IO18GPIO2_IO04
|-
| rowspan="3" |J1.164142(eMMC on board)| rowspan="3" |NAND_DATA02| rowspan="3" |CPU.NAND_DATA02| rowspan="3" |H22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA02|-|ALT1|QSPI_A_DATA2|-|ALT5|GPIO3_IO08|-| rowspan="2" |J1.144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |P25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.146
|DGND
|DGND
|
|-
| rowspan="2" |J1.166148(NAND on board)|CLK1_Nrowspan="2" |SD1_DATA4| rowspan="2" |CPU.CLK1_NSD1_DATA4|T23rowspan="2" |N24|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4
|-
|J1.168|CLK1_P|CPU.CLK1_P|R23||D||ALT5|GPIO2_IO06
|-
| rowspan="3" |J1.170148(eMMC on board)|USB2_RXNrowspan="3" |NAND_DATA04| rowspan="3" |CPU.USB2_RX_NNAND_DATA04|B8rowspan="3" |L20|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA04
|-
|J1.172|USB2_RXP|CPU.USB2_RX_P|A8||D||ALT1|QSPI_B_DATA0
|-
|J1.174|USB2_TXN|CPU.USB2_TX_N|B9||D||ALT5|GPIO3_IO10
|-
| rowspan="2" |J1.176150(NAND on board)|USB2_TXProwspan="2" |SD1_DATA5| rowspan="2" |CPU.USB2_TX_PSD1_DATA5|A9rowspan="2" |P24|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA5
|-
|J1.178|USB1_RXN|CPU.USB1_RX_N|B12||D||ALT5|GPIO2_IO07
|-
| rowspan="3" |J1.180150(eMMC on board)|USB1_RXProwspan="3" |NAND_DATA05| rowspan="3" |CPU.USB1_RX_PNAND_DATA05|A12rowspan="3" |J22|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA05
|-
|J1.182|USB1_TXN|CPU.USB1_TX_N|B13||D||ALT1|QSPI_B_DATA1
|-
|J1.184|USB1_TXP|CPU.USB1_TX_P|A13||D||ALT5|GPIO3_IO11
|-
| rowspan="2" |J1.186152(NAND on board)|USB1_VBUSrowspan="2" |SD1_DATA6| rowspan="2" |CPU.USB1_VBUSSD1_DATA6|D14rowspan="2" |R25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Srowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA6
|-
|J1.188|USB2_VBUS|CPU.USB2_VBUS|D9| -|S||ALT5|GPIO2_IO08
|-
| rowspan="3" |J1.190152(eMMC on board)| rowspan="3" |DGNDNAND_DATA06|DGNDrowspan="3" |CPU.NAND_DATA06| -rowspan="3" |L19|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_DATA06
|-
|J1.192|USB1_ID|CPU.USB1_ID|C14|VDD_PHY_3V3|I||ALT1|QSPI_B_DATA2
|-
|ALT5|GPIO3_IO12|-| rowspan="2" |J1.154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |T25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09|-| rowspan="3" |J1.154(eMMC on board)| rowspan="3" |NAND_DATA07| rowspan="3" |CPU.NAND_DATA07| rowspan="3" |M19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT5|GPIO3_IO13|-|J1.194156(NAND on board)|USB2_IDNAND_RE_B|CPU.USB2_IDNAND_RE_B|C9K19|VDD_PHY_3V3NVCC_3V3|I/O|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.196156(eMMC on board)|USB1_DNrowspan="3" |NAND_RE_B| rowspan="3" |CPU.USB1_DNNAND_RE_B| rowspan="3" |K19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|B14rowspan="3" || -ALT0|DRAWNAND_RE_B|-|ALT1|QSPI_B_DQS
|-
|J1.198|USB1_DP|CPU.USB1_DP|A14| -|D||ALT5|GPIO3_IO15
|-
|J1.200158(NAND on board)|USB2_DPNAND_READY_B|CPU.USB2_DPNAND_READY_B|A10K20| -NVCC_3V3|DI/O|Internally used for NAND, do not connect
|
|
|-
| rowspan="2" |J1.202158(eMMC on board)|USB2_DNrowspan="2" |NAND_READY_B| rowspan="2" |CPU.USB2_DNNAND_READY_B| rowspan="2" |K20| rowspan="2" |NVCC_3V3| rowspan="2" |I/O|B10rowspan="2" || -ALT0|DRAWNAND_READY_B|-|ALT5|GPIO3_IO16
|-
|J1.204160(NAND on board)|DGNDNAND_WE_B|DGNDCPU.NAND_WE_B| -K22|<nowiki>-</nowiki>NVCC_3V3|GI/O|Internally used for NAND, do not connect
|
|
|-
|}rowspan="2" |J1.160(eMMC on board)| rowspan="2" |NAND_WE_B| rowspan="2" |CPU.NAND_WE_B| rowspan=Pinout Table J4 pins declaration =="2" |K22| rowspan="2" |NVCC_3V3{| classrowspan="wikitable2" |I/O! latexfontsize| rowspan="scriptsize2" | Pin ! latexfontsize|ALT0|RAWNAND_WE_B|-|ALT5|GPIO3_IO17|-|J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|K21|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="scriptsize2" | Pin NameJ1.162! latexfontsize(eMMC on board)| rowspan="scriptsize2" | Internal Connections NAND_WP_B! latexfontsize| rowspan="scriptsize2" | Ball/pin # CPU.NAND_WP_B! latexfontsize| rowspan="scriptsize2" |<nowiki>VoltageK21|domain</nowiki>! latexfontsizerowspan="scriptsize2" | Type NVCC_3V3! latexfontsize| rowspan="scriptsize2" | NotesI/O! colspan| rowspan="2" |Alternative Functions|ALT0|RAWNAND_WP_B|-|ALT5|GPIO3_IO18
|-
|J4J1.1164
|DGND
|DGND
|
|-
| rowspan="7" |J4J1.2166| rowspan="7" |SAI1_RXD7CLK1_N| rowspan="7" |CPU.SAI1_RXD7CLK1_N| rowspan="7" |G1T23| rowspan="7" |NVCC_3V3| rowspan="7" |I/OD| rowspan="7" |internally used for BOOT config|ALT0|SAI1_RX_DATA7
|-
|ALT1J1.168|CLK1_P|CPU.CLK1_P|R23||D|||SAI6_MCLK
|-
|ALT2J1.170|USB2_RXN|CPU.USB2_RX_N|B8||D|||SAI1_TX_SYNC
|-
|ALT3J1.172|USB2_RXP|CPU.USB2_RX_P|A8||D|||SAI1_TX_DATA4
|-
|ALT4J1.174|USB2_TXN|CPU.USB2_TX_N|B9||D|||CORESIGHT_TRACE7
|-
|ALT5J1.176|USB2_TXP|CPU.USB2_TX_P|A9||D|||GPIO4_IO09
|-
|ALT6|SRC_BOOT_CFG7|-| rowspan="6" |J4J1.3178| rowspan="6" |SAI1_RXD6USB1_RXN| rowspan="6" |CPU.SAI1_RXD6USB1_RX_N| rowspan="6" |G2B12| rowspan="6" |NVCC_3V3| rowspan="6" |I/OD| rowspan="6" |internally used for BOOT config|ALT0|SAI1_RX_DATA6
|-
|ALT1J1.180|USB1_RXP|CPU.USB1_RX_P|A12||D|||SAI6_TX_SYNC
|-
|ALT2J1.182|USB1_TXN|CPU.USB1_TX_N|B13||D|||SAI6_RX_SYNC
|-
|ALT4J1.184|USB1_TXP|CPU.USB1_TX_P|A13||D|||CORESIGHT_TRACE6
|-
|ALT5J1.186|USB1_VBUS|CPU.USB1_VBUS|D14| -|S|Absolute maximum ratings 5.25V||GPIO4_IO08
|-
|ALT6J1.188|USB2_VBUS|CPU.USB2_VBUS|D9| -|S|Absolute maximum ratings 5.25V||SRC_BOOT_CFG6
|-
| rowspan="7" |J4J1.4190| rowspan="7" |SAI1_RXD5| rowspan="7" |CPU.SAI1_RXD5DGND| rowspan="7" |F1DGND| rowspan="7" |NVCC_3V3-| rowspan="7" |I<nowiki>-</Onowiki>| rowspan="7" G|internally used for BOOT config|ALT0|SAI1_RX_DATA5
|-
|ALT1J1.192|USB1_ID|CPU.USB1_ID|C14|VDD_PHY_3V3|I|||SAI6_TX_DATA0
|-
|ALT2J1.194|USB2_ID|CPU.USB2_ID|C9|VDD_PHY_3V3|I|||SAI6_RX_DATA0
|-
|ALT3J1.196|USB1_DN|CPU.USB1_DN|B14| -|D|||SAI1_RX_SYNC
|-
|ALT4J1.198|USB1_DP|CPU.USB1_DP|A14| -|D|||CORESIGHT_TRACE5
|-
|ALT5J1.200|USB2_DP|CPU.USB2_DP|A10| -|D|||GPIO4_IO07
|-
|ALT6J1.202|USB2_DN|CPU.USB2_DN|B10| -|D|||SRC_BOOT_CFG5
|-
| rowspan="6" |J4J1.5| rowspan="6" |SAI1_RXD4204| rowspan="6" |CPU.SAI1_RXD4DGND| rowspan="6" |J1DGND| rowspan="6" |NVCC_3V3-| rowspan="6" |I<nowiki>-</Onowiki>| rowspan="6" G|internally used for BOOT config|ALT0|SAI1_RX_DATA4
|-
|ALT1} ==ONE PIECE J4 pins declaration =={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" |SAI6_TX_BCLKAlternative Functions
|-
|ALT2J4.1|DGND|DGND| -|<nowiki>-</nowiki>|G|||SAI6_RX_BCLK
|-
|ALT4rowspan="7" |J4.2| rowspan="7" |SAI1_RXD7| rowspan="7" |CPU.SAI1_RXD7| rowspan="7" |G1| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|CORESIGHT_TRACE4SAI1_RX_DATA7
|-
|ALT5ALT1|GPIO4_IO06SAI6_MCLK
|-
|ALT6ALT2|SRC_BOOT_CFG4SAI1_TX_SYNC
|-
| rowspan="5" |J4.6| rowspan="5" |SAI1_RXD3| rowspan="5" |CPU.SAI1_RXD3| rowspan="5" |J2| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |internally used for BOOT config|ALT0|SAI1_RX_DATA3|-|ALT1ALT3|SAI5_RX_DATA3SAI1_TX_DATA4
|-
|ALT4
|CORESIGHT_TRACE3CORESIGHT_TRACE7
|-
|ALT5
|GPIO4_IO05GPIO4_IO09
|-
|ALT6
|SRC_BOOT_CFG3SRC_BOOT_CFG7
|-
| rowspan="56" |J4.73| rowspan="56" |SAI1_RXD2SAI1_RXD6| rowspan="56" |CPU.SAI1_RXD2SAI1_RXD6| rowspan="56" |H2G2| rowspan="56" |NVCC_3V3| rowspan="56" |I/O| rowspan="56" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA2SAI1_RX_DATA6
|-
|ALT1
|SAI5_RX_DATA2SAI6_TX_SYNC|-|ALT2|SAI6_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE2CORESIGHT_TRACE6
|-
|ALT5
|GPIO4_IO04GPIO4_IO08
|-
|ALT6
|SRC_BOOT_CFG2SRC_BOOT_CFG6
|-
| rowspan="57" |J4.84| rowspan="57" |SAI1_RXD1SAI1_RXD5| rowspan="57" |CPU.SAI1_RXD1SAI1_RXD5| rowspan="57" |L2F1| rowspan="57" |NVCC_3V3| rowspan="57" |I/O| rowspan="57" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA1SAI1_RX_DATA5
|-
|ALT1
|SAI5_RX_DATA1SAI6_TX_DATA0
|-
|ALT2|SAI6_RX_DATA0|-|ALT3|SAI1_RX_SYNC|-|ALT4|CORESIGHT_TRACE1CORESIGHT_TRACE5
|-
|ALT5
|GPIO4_IO03GPIO4_IO07
|-
|ALT6
|SRC_BOOT_CFG1SRC_BOOT_CFG5
|-
| rowspan="56" |J4.95| rowspan="56" |SAI1_RXD0SAI1_RXD4| rowspan="56" |CPU.SAI1_RXD0SAI1_RXD4| rowspan="56" |K2J1| rowspan="56" |NVCC_3V3| rowspan="56" |I/O| rowspan="56" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA0SAI1_RX_DATA4
|-
|ALT1
|SAI5_RX_DATA0SAI6_TX_BCLK|-|ALT2|SAI6_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE0CORESIGHT_TRACE4
|-
|ALT5
|GPIO4_IO02GPIO4_IO06
|-
|ALT6
|SRC_BOOT_CFG0SRC_BOOT_CFG4
|-
| rowspan="45" |J4.106| rowspan="45" |SAI1_RXCSAI1_RXD3| rowspan="45" |CPU.SAI1_RXCSAI1_RXD3| rowspan="45" |K1J2| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_BCLKSAI1_RX_DATA3
|-
|ALT1
|SAI5_RX_BCLKSAI5_RX_DATA3
|-
|ALT4
|CORESIGHT_TRACE_CTLCORESIGHT_TRACE3
|-
|ALT5
|GPIO4_IO01GPIO4_IO05|-|ALT6|SRC_BOOT_CFG3
|-
| rowspan="45" |J4.117| rowspan="45" |SAI1_RXFSSAI1_RXD2| rowspan="45" |CPU.SAI1_RXFSSAI1_RXD2| rowspan="45" |L1H2| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_SYNCSAI1_RX_DATA2
|-
|ALT1
|SAI5_RX_SYNCSAI5_RX_DATA2
|-
|ALT4
|CORESIGHT_TRACE_CLKCORESIGHT_TRACE2
|-
|ALT5
|GPIO4_IO00GPIO4_IO04
|-
|J4.12|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT6|SRC_BOOT_CFG2
|-
| rowspan="45" |J4.138| rowspan="45" |SAI1_MCLKSAI1_RXD1| rowspan="45" |CPU.SAI1_MCLKSAI1_RXD1| rowspan="45" |L2| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_MCLKSAI1_RX_DATA1
|-
|ALT1
|SAI5_MCLK SAI5_RX_DATA1
|-
|ALT2ALT4|SAI1_TX_BCLKCORESIGHT_TRACE1
|-
|ALT5
|GPIO4_IO20GPIO4_IO03|-|ALT6|SRC_BOOT_CFG1
|-
| rowspan="5" |J4.149| rowspan="5" |SAI1_RXD0| rowspan="5" |CPU.SAI1_RXD0| rowspan="5" |K2|DGNDrowspan="5" |NVCC_3V3|DGNDrowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA0|-|ALT1|SAI5_RX_DATA0|<nowiki>-</nowiki>|GALT4|CORESIGHT_TRACE0|-|ALT5|GPIO4_IO02|-|ALT6|SRC_BOOT_CFG0
|-
| rowspan="4" |J4.1510| rowspan="4" |SAI1_TXFSSAI1_RXC| rowspan="4" |CPU.SAI1_TXFSSAI1_RXC| rowspan="4" |H4K1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_SYNCSAI1_RX_BCLK
|-
|ALT1
|SAI5_TX_SYNCSAI5_RX_BCLK
|-
|ALT4
|CORESIGHT_EVENTOCORESIGHT_TRACE_CTL
|-
|ALT5
|GPIO4_IO10GPIO4_IO01
|-
| rowspan="4" |J4.1611| rowspan="4" |SAI1_TXCSAI1_RXFS| rowspan="4" |CPU.SAI1_TXCSAI1_RXFS| rowspan="4" |J5L1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_BCLKSAI1_RX_SYNC
|-
|ALT1
|SAI5_TX_BCLKSAI5_RX_SYNC
|-
|ALT4
|CORESIGHT_EVENTICORESIGHT_TRACE_CLK
|-
|ALT5
|GPIO4_IO11GPIO4_IO00
|-
| rowspan="5" |J4.1712| rowspan="5" |SAI1_TXD0| rowspan="5" |CPU.SAI1_TXD0DGND| rowspan="5" |F2DGND| rowspan="5" |NVCC_3V3-| rowspan="5" |I<nowiki>-</Onowiki>| rowspan="5" G|internally used for BOOT config|ALT0|SAI1_TX_DATA0
|-
|ALT1|SAI5_TX_DATA0|-|ALT4|CORESIGHT_TRACE8|-|ALT5|GPIO4_IO12|-|ALT6|SRC_BOOT_CFG8|-| rowspan="54" |J4.1813| rowspan="54" |SAI1_TXD1SAI1_MCLK| rowspan="54" |CPU.SAI1_TXD1SAI1_MCLK| rowspan="54" |E2| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA1SAI1_MCLK
|-
|ALT1
|SAI5_TX_DATA1SAI5_MCLK
|-
|ALT4ALT2|CORESIGHT_TRACE9SAI1_TX_BCLK
|-
|ALT5
|GPIO4_IO13GPIO4_IO20
|-
|ALT6J4.14|DGND|DGND| -|<nowiki>-</nowiki>|G|||SRC_BOOT_CFG9|-| rowspan="54" |J4.1915| rowspan="54" |SAI1_TXD2SAI1_TXFS| rowspan="54" |CPU.SAI1_TXD2SAI1_TXFS| rowspan="54" |B2H4| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA2SAI1_TX_SYNC
|-
|ALT1
|SAI5_TX_DATA2SAI5_TX_SYNC
|-
|ALT4
|CORESIGHT_TRACE10CORESIGHT_EVENTO
|-
|ALT5
|GPIO4_IO14GPIO4_IO10
|-
|ALT6rowspan="4" |J4.16| rowspan="4" |SAI1_TXC| rowspan="4" |CPU.SAI1_TXC| rowspan="4" |J5| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SRC_BOOT_CFG10SAI1_TX_BCLK
|-
|ALT1|SAI5_TX_BCLK|-|ALT4|CORESIGHT_EVENTI|-|ALT5|GPIO4_IO11|-| rowspan="5" |J4.2017| rowspan="5" |SAI1_TXD3SAI1_TXD0| rowspan="5" |CPU.SAI1_TXD3SAI1_TXD0| rowspan="5" |D1F2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3SAI1_TX_DATA0
|-
|ALT1
|SAI5_TX_DATA3SAI5_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE11CORESIGHT_TRACE8
|-
|ALT5
|GPIO4_IO15GPIO4_IO12
|-
|ALT6
|SRC_BOOT_CFG11SRC_BOOT_CFG8
|-
| rowspan="65" |J4.2118| rowspan="65" |SAI1_TXD4SAI1_TXD1| rowspan="65" |CPU.SAI1_TXD4SAI1_TXD1| rowspan="65" |D2E2| rowspan="65" |NVCC_3V3| rowspan="65" |I/O| rowspan="65" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4SAI1_TX_DATA1
|-
|ALT1
|SAI6_RX_BCLK|-|ALT2|SAI6_TX_BCLKSAI5_TX_DATA1
|-
|ALT4
|CORESIGHT_TRACE12CORESIGHT_TRACE9
|-
|ALT5
|GPIO4_IO16GPIO4_IO13
|-
|ALT6
|SRC_BOOT_CFG12SRC_BOOT_CFG9
|-
| rowspan="65" |J4.2219| rowspan="65" |SAI1_TXD5SAI1_TXD2| rowspan="65" |CPU.SAI1_TXD5SAI1_TXD2| rowspan="65" |C2B2| rowspan="65" |NVCC_3V3| rowspan="65" |I/O| rowspan="65" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5SAI1_TX_DATA2
|-
|ALT1
|SAI6_RX_DATA0|-|ALT2|SAI6_TX_DATA0SAI5_TX_DATA2
|-
|ALT4
|CORESIGHT_TRACE13CORESIGHT_TRACE10
|-
|ALT5
|GPIO4_IO17GPIO4_IO14
|-
|ALT6
|SRC_BOOT_CFG13SRC_BOOT_CFG10
|-
| rowspan="5" |J4.20| rowspan="5" |SAI1_TXD3| rowspan="5" |CPU.SAI1_TXD3| rowspan="5" |D1| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA3|-|ALT1|SAI5_TX_DATA3|-|ALT4|CORESIGHT_TRACE11|-|ALT5|GPIO4_IO15|-|ALT6|SRC_BOOT_CFG11|-| rowspan="6" |J4.2321| rowspan="6" |SAI1_TXD6SAI1_TXD4| rowspan="6" |CPU.SAI1_TXD6SAI1_TXD4| rowspan="6" |B3D2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6SAI1_TX_DATA4
|-
|ALT1
|SAI6_RX_SYNCSAI6_RX_BCLK
|-
|ALT2
|SAI6_TX_SYNCSAI6_TX_BCLK
|-
|ALT4
|CORESIGHT_TRACE14CORESIGHT_TRACE12
|-
|ALT5
|GPIO4_IO18GPIO4_IO16
|-
|ALT6
|SRC_BOOT_CFG14SRC_BOOT_CFG12
|-
| rowspan="56" |J4.2422| rowspan="56" |SAI1_TXD7SAI1_TXD5| rowspan="56" |CPU.SAI1_TXD7SAI1_TXD5| rowspan="56" |C1C2| rowspan="56" |NVCC_3V3| rowspan="56" |I/O| rowspan="56" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7SAI1_TX_DATA5
|-
|ALT1
|SAI6_MCLKSAI6_RX_DATA0|-|ALT2|SAI6_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE15CORESIGHT_TRACE13
|-
|ALT5
|GPIO4_IO19GPIO4_IO17
|-
|ALT6
|SRC_BOOT_CFG15SRC_BOOT_CFG13
|-
| rowspan="6" |J4.25|DGND|DGND| -23|<nowiki>-</nowiki>|G||||}===Pinout Table J5 pins declaration ==={| classrowspan="wikitable6" |SAI1_TXD6! latexfontsize| rowspan="scriptsize6" | Pin CPU.SAI1_TXD6! latexfontsize| rowspan="scriptsize6" | Pin NameB3! latexfontsize| rowspan="scriptsize6" | Internal Connections NVCC_3V3! latexfontsize| rowspan="scriptsize6" | BallI/pin # O! latexfontsize| rowspan="scriptsize6" |<nowiki>Voltage|domain</nowiki>Internally used for BOOT config! latexfontsize="scriptsize" | Type Could be pulled-up or down during bootstrap.! latexfontsize="scriptsize" | NotesALT0! colspan="2" |Alternative FunctionsSAI1_TX_DATA6
|-
|J5.1|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT1|SAI6_RX_SYNC
|-
|J5.2|PCIE2_RXN|CPU.PCIE2_RXN_N|D24| -|D||ALT2|SAI6_TX_SYNC
|-
|J5ALT4|CORESIGHT_TRACE14|-|ALT5|GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14|-| rowspan="5" |J4.324|PCIE2_RXProwspan="5" |SAI1_TXD7| rowspan="5" |CPU.PCIE2_RXN_PSAI1_TXD7| rowspan="5" |C1| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|D25SAI1_TX_DATA7| -|DALT1|SAI6_MCLK|-|ALT4|CORESIGHT_TRACE15|-|ALT5|GPIO4_IO19|-|ALT6|SRC_BOOT_CFG15
|-
|J5J4.425
|DGND
|DGND
|
|
|} ==ONE PIECE J5 pins declaration =={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" |Alternative Functions|-|J5.1|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J5.52|PCIE2_TXNPCIE2_RXN|CPU.PCIE2_TXN_NPCIE2_RXN_N|E24D24
| -
|D
|
|-
|J5.63|PCIE2_TXPPCIE2_RXP|CPU.PCIE2_TXN_PPCIE2_RXN_P|E25D25
| -
|D
|
|-
|J5.74
|DGND
|DGND
|
|-
|J5.5|PCIE2_TXN|CPU.PCIE2_TXN_N|E24| -|D||||-|J5.6|PCIE2_TXP|CPU.PCIE2_TXN_P|E25| -|D||||-|J5.7|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J5.8
|PCIE2_REF_CLKN
|CPU.PCIE2_REF_PAD_CLK_N
|ALT5
|GPIO5_IO21
|}
 
===Pinout Table JD5 pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
|-
|JD5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|JD5.2
|EEPROM_WP
|Internal EEPROM Write Protect
| -
|NVCC_3V3
|I
|
|
|
|-
|JD5.3
|NC
|Not Connected
| -
| -
|Z
|
|
|
|-
|JD5.4
|JTAG_TCK
|CPU.JTAG_TCK
|T5
|NVCC_3V3
|I
|internal pull-up 10k to NVCC_3V3
|
|
|-
|JD5.5
|JTAG_TMS
|CPU.JTAG_TMS
|V5
|NVCC_3V3
|I
|
|
|
|-
|JD5.6
|JTAG_TDO
|CPU.JTAG_TDO
|U5
|NVCC_3V3
|O
|
|
|
|-
|JD5.7
|JTAG_TDI
|CPU.JTAG_TDI
|W5
|NVCC_3V3
|I
|
|
|
|-
|JD5.8
|JTAG_nTRST
|CPU.JTAG_TRST_B
|U6
|NVCC_3V3
|I
|
|
|
|-
|JD5.9
|CPU_PORn
|CPU.POR_B
PMIC.RESETMCU
|W20
3
|NVCC_SNVS
|I/O
|internal pull-up 100k to NVCC_SNVS
|
|
|-
|JD5.10
|NVCC_3V3
|NVCC_3V3
| -
|<nowiki>-</nowiki>
|S
|
|
|
|}
U0007
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