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MITO 8M SOM/MITO 8M Hardware/Pinout Table

14,192 bytes added, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains the pinout === Connectors description of ===In the following table are described all available connectors integrated on MITO 8M module, grouped in two tables (odd SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|}The dedicated carrier board must mount the mating connector and even pins) that report connect the pin mapping of desired peripheral interfaces according to MITO 8M pinout specifications. See the 204images below for reference: [[File:MITO 8M-pin SOconn-DIMM TOP.png|500px|thumb|MITO 8M connectorTOP view|none]][[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
Below a detailed description of the pinout, grouped in the following tables:
* two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
* a dedicated tables for J4 one-piece connector
* a dedicated tables for J5 one-piece connector
 
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {| class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge* SV.<x>: pin connected to voltage supervisor(TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|GPIO1_IO01
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|GPIO1_IO13
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3
|ALT0
|GPIO1_IO05
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|GPIO1_IO06
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="63" |used as default Linux console
|ALT0
|UART2_TX
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|UART2_RXD
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|}
===Pinout Table SODIMM J1 EVEN pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02
|GPIO5_IO01
|-
| rowspan="2" |J1.54|SD1_STROBErowspan="2" |GPIO1_IO10| rowspan="2" |CPU.SD1_STROBEGPIO1_IO10|T24rowspan="2" |M7|NVCC_1V8 // rowspan="2" |NVCC_3V3 ???| rowspan="2" |I/O|internally rowspan="2" |Internally used for eMMCETH PHY interrupt, do not connect|ALT0|GPIO1_IO10|-|ALT1|USB1_OTG_ID
|-
|J1.56
|
|-
| rowspan="4" |J1.58| rowspan="4" |SAI5_MCLK| rowspan="4" |CPU.SAI5_MCLK| rowspan="4" |K4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0
|SAI5_MCLK
|CPU.SAI5_MCLK
|K4
|NVCC_3V3
|I/O
|
|
|
|-
|J1.60|GPIO1_IO15|CPU.GPIO1_IO15|J6|NVCC_3V3|I/O||ALT1|SAI1_TX_BCLK
|-
|J1.62|SAI5_RXFS|CPU.SAI5_RXFS|N4|NVCC_3V3|I/O||ALT2|SAI4_MCLK
|-
|J1.64|SAI5_RXC|CPU.SAI5_RXC|L5|NVCC_3V3|I/O||ALT5|GPIO3_IO25
|-
| rowspan="4" |J1.6660|SAI2_TXCrowspan="4" |GPIO1_IO15| rowspan="4" |CPU.SAI2_TXCGPIO1_IO15|J5rowspan="4" |J6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO15
|-
|J1.68|SAI2_TXD0|CPU.SAI2_TXD0|G5|NVCC_3V3|I/O||ALT1|USB2_OTG_OC
|-
|J1.70|SAI2_TXFS|CPU.SAI2_TXFS|H4|NVCC_3V3|I/O||ALT5|PWM4_OUT
|-
|J1.72|SAI2_RXD0|CPU.SAI2_RXD0|H6|NVCC_3V3|I/O||ALT6|CCM_CLKO2
|-
| rowspan="3" |J1.7462|SAI5_RXD0rowspan="3" |SAI5_RXFS| rowspan="3" |CPU.SAI5_RXD0SAI5_RXFS|M5rowspan="3" |N4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_SYNC
|-
|J1.76|SAI5_RXD1|CPU.SAI5_RXD1|L4|NVCC_3V3|I/O||ALT1|SAI1_TX_DATA0
|-
|J1.78|SAI5_RXD2|CPU.SAI5_RXD2|M4|NVCC_3V3|I/O||ALT5|GPIO3_IO19
|-
| rowspan="3" |J1.8064|SAI5_RXD3rowspan="3" |SAI5_RXC| rowspan="3" |CPU.SAI5_RXD3SAI5_RXC|K5rowspan="3" |L5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_BCLK
|-
|J1.82|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT1|SAI1_TX_DATA1
|-
|ALT5|GPIO3_IO20|-| rowspan="3" |J1.8466|CLK2_Nrowspan="3" |SAI2_TXC| rowspan="3" |CPU.CLK2_NSAI2_TXC|T22rowspan="3" |J5|VDDA_1V8rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_BCLK
|-
|J1.86|CLK2_P|CPU.CLK2_P|U22|VDDA_1V8|D||ALT1|SAI5_TX_DATA2
|-
|J1.88|PCIE1_REF_CLKN|CPU.PCIE1_REF_PAD_CLK_N|K24|VDD_PHY_3V3|D||ALT5|GPIO4_IO25
|-
| rowspan="3" |J1.9068|PCIE1_REF_CLKProwspan="3" |SAI2_TXD0| rowspan="3" |CPU.PCIE1_REF_PAD_CLK_PSAI2_TXD0|K25rowspan="3" |G5|VDD_PHY_3V3rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_DATA0
|-
|J1.92|PCIE1_RXN|CPU.PCIE1_RXN_N|H24|VDD_PHY_3V3|D||ALT1|SAI5_TX_DATA3
|-
|J1.94|PCIE1_RXP|CPU.PCIE1_RXN_P|H25|VDD_PHY_3V3|D||ALT5|GPIO4_IO26
|-
| rowspan="3" |J1.9670|PCIE1_TXNrowspan="3" |SAI2_TXFS| rowspan="3" |CPU.PCIE1_TXN_NSAI2_TXFS|J24rowspan="3" |H4|VDD_PHY_3V3rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_SYNC
|-
|J1.98|PCIE1_TXP|CPU.PCIE1_TXN_P|J25|VDD_PHY_3V3|D||ALT1|SAI5_TX_DATA1
|-
|J1.100|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO4_IO24
|-
| rowspan="3" |J1.10272|CSI1_CLK_Nrowspan="3" |SAI2_RXD0| rowspan="3" |CPU.MIPI_CSI1_CLK_NSAI2_RXD0| rowspan="3" |H6|A22rowspan="3" |NVCC_3V3| -rowspan="3" |I/O| rowspan="3" ||ALT0|DSAI2_RX_DATA0|-|ALT1|SAI5_TX_DATA0
|-
|J1.104|CSI1_CLK_P|CPU.MIPI_CSI1_CLK_P|B22| -|D||ALT5|GPIO4_IO23
|-
| rowspan="3" |J1.10674|CSI1_D0_Nrowspan="3" |SAI5_RXD0| rowspan="3" |CPU.MIPI_CSI1_D0_NSAI5_RXD0|A23rowspan="3" |M5| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_DATA0
|-
|J1.108|CSI1_D0_P|CPU.MIPI_CSI1_D0_P|B23| -|D||ALT1|SAI1_TX_DATA2
|-
|J1.110|CSI1_D1_N|CPU.MIPI_CSI1_D1_N|C22| -|D||ALT5|GPIO3_IO21
|-
| rowspan="5" |J1.11276|CSI1_D1_Prowspan="5" |SAI5_RXD1| rowspan="5" |CPU.MIPI_CSI1_D1_PSAI5_RXD1|D22rowspan="5" |L4| -rowspan="5" |NVCC_3V3|Drowspan="5" |I/O| rowspan="5" ||ALT0|SAI5_RX_DATA1
|-
|J1.114|CSI1_D2_N|CPU.MIPI_CSI1_D2_N|B24| -|D||ALT1|SAI1_TX_DATA3
|-
|J1.116ALT2|CSI1_D2_P|CPU.MIPI_CSI1_D2_P|C23SAI1_TX_SYNC| -|D||ALT3|SAI5_TX_SYNC
|-
|J1.118|CSI1_D3_N|CPU.MIPI_CSI1_D3_N|C21| -|D||ALT5|GPIO3_IO212
|-
| rowspan="5" |J1.12078|CSI1_D3_Prowspan="5" |SAI5_RXD2| rowspan="5" |CPU.MIPI_CSI1_D3_PSAI5_RXD2|D21rowspan="5" |M4| -rowspan="5" |NVCC_3V3|Drowspan="5" |I/O| rowspan="5" ||ALT0|SAI5_RX_DATA2
|-
|ALT1|SAI1_TX_DATA4|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_BCLK|-|ALT5|GPIO3_IO23|-| rowspan="5" |J1.12280| rowspan="5" |SAI5_RXD3| rowspan="5" |CPU.SAI5_RXD3| rowspan="5" |K5| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI5_RX_DATA3|-|ALT1|SAI1_TX_DATA5|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_DATA0|-|ALT5|GPIO3_IO24|-|J1.82|DGND|DGND
| -
|<nowiki>-</nowiki>
|
|-
|J1.12484|NAND_DQSCLK2_N|CPU.NAND_DQSCLK2_N|M20T22|NVCC_3V3VDDA_1V8|I/OD|internally Internally used for NANDPCIe CLK, do not connect
|
|
|-
|J1.12686|NAND_ALECLK2_P|CPU.NAND_ALECLK2_P|G19U22|NVCC_3V3VDDA_1V8|I/OD|internally Internally used for NANDPCIe CLK, do not connect
|
|
|-
|J1.12888|NAND_CE0_B // SD1_CLKPCIE1_REF_CLKN|CPU.NAND_CE0_B // CPU.SD1_CLKPCIE1_REF_PAD_CLK_N|H19 // L25K24|NVCC_1V8 // NVCC_3V3 ???VDD_PHY_3V3|I/OD|???
|
|
|-
|J1.13090|NAND_CE1_B // SD1_CMDPCIE1_REF_CLKP|CPU.NAND_CE1_B // CPU.SD1_CMDPCIE1_REF_PAD_CLK_P|G21 // L24K25|NVCC_1V8 // NVCC_3V3 ???VDD_PHY_3V3|I/OD|???
|
|
|-
|J1.13292|NAND_CE2_B // SD1_RST_BPCIE1_RXN|CPU.NAND_CE2_B // CPU.SD1_RST_B|F21 // R24PCIE1_RXN_N|NVCC_1V8 // NVCC_3V3 ???H24|I/OVDD_PHY_3V3|???D
|
|
|-
|J1.134
|NAND_CE3_B // SD1_STROBE
|CPU.NAND_CE3_B // CPU.SD1_STROBE
|H20 // T24
|NVCC_1V8 // NVCC_3V3 ???
|I/O
|???
|
|
|-
|J1.13694|NAND_CLEPCIE1_RXP|DGNDCPU.PCIE1_RXN_P|H21H25|NVCC_3V3VDD_PHY_3V3|I/OD
|
|
|
|-
|J1.13896|NAND_DATA00 // SD1_DATA0PCIE1_TXN|CPU.NAND_DATA00 // CPU.SD1_DATA0|G20 // M25PCIE1_TXN_N|NVCC_1V8 // NVCC_3V3 ???J24|I/OVDD_PHY_3V3|???D
|
|
|-
|J1.140
|NAND_DATA01 // SD1_DATA1
|CPU.NAND_DATA01 // CPU.SD1_DATA1
|J20 // M24
|NVCC_1V8 // NVCC_3V3 ???
|I/O
|???
|
|
|-
|J1.14298|NAND_DATA02 // SD1_DATA2PCIE1_TXP|CPU.NAND_DATA02 // CPU.SD1_DATA2|H22 // N25PCIE1_TXN_P|NVCC_1V8 // NVCC_3V3 ???J25|I/OVDD_PHY_3V3|???D
|
|
|-
|J1.144
|NAND_DATA03 // SD1_DATA3
|CPU.NAND_DATA03 // CPU.SD1_DATA3
|J21 // P25
|NVCC_1V8 // NVCC_3V3 ???
|I/O
|???
|
|
|-
|J1.146100
|DGND
|DGND
|
|-
|J1.148102|NAND_DATA04 // SD1_DATA4CSI1_CLK_N|CPU.NAND_DATA04 // CPU.SD1_DATA4MIPI_CSI1_CLK_N|L20 // N24A22|NVCC_1V8 // NVCC_3V3 ???-|I/OD|???
|
|
|-
|J1.150104|NAND_DATA05 // SD1_DATA5CSI1_CLK_P|CPU.NAND_DATA05 // CPU.SD1_DATA5MIPI_CSI1_CLK_P|J22 // P24B22|NVCC_1V8 // NVCC_3V3 ???-|I/OD|???
|
|
|-
|J1.152106|NAND_DATA06 // SD1_DATA6CSI1_D0_N|CPU.NAND_DATA06 // CPU.SD1_DATA6|L19 // R25MIPI_CSI1_D0_N|NVCC_1V8 // NVCC_3V3 ???A23|I/O-|???D
|
|
|-
|J1.154
|NAND_DATA07 // SD1_DATA7
|CPU.NAND_DATA07 // CPU.SD1_DATA7
|M19 // T25
|NVCC_1V8 // NVCC_3V3 ???
|I/O
|???
|
|
|-
|J1.156108|NAND_RE_BCSI1_D0_P|CPU.NAND_RE_BMIPI_CSI1_D0_P|K19B23|NVCC_3V3-|I/OD
|
|
|
|-
|J1.158110|NAND_READY_BCSI1_D1_N|CPU.NAND_READY_BMIPI_CSI1_D1_N|K20C22|NVCC_3V3-|I/OD
|
|
|
|-
|J1.160112|NAND_WE_BCSI1_D1_P|CPU.NAND_WE_BMIPI_CSI1_D1_P|K22D22|NVCC_3V3-|I/OD
|
|
|
|-
|J1.162114|NAND_WP_BCSI1_D2_N|CPU.NAND_WP_BMIPI_CSI1_D2_N|K21B24|NVCC_3V3-|I/OD
|
|
|
|-
|J1.164116|DGNDCSI1_D2_P|DGNDCPU.MIPI_CSI1_D2_P|C23
| -
|<nowiki>-</nowiki>|GD
|
|
|
|-
|J1.166118|CLK1_NCSI1_D3_N|CPU.CLK1_NMIPI_CSI1_D3_N|T23C21|-
|D
|
|
|-
|J1.168120|CLK1_PCSI1_D3_P|CPU.CLK1_PMIPI_CSI1_D3_P|R23D21|-
|D
|
|
|-
|J1.170122|USB2_RXNDGND|CPU.USB2_RX_NDGND|B8-|<nowiki>-</nowiki>|DG
|
|
|
|-
|J1.172124(NAND on board)|USB2_RXPNAND_DQS|CPU.USB2_RX_PNAND_DQS|M20|NVCC_3V3|I/O|A8Internally used for NAND, do not connect
|
|D
|
|-
| rowspan="3" |J1.124
(eMMC on board)
| rowspan="3" |NAND_DQS
| rowspan="3" |CPU.NAND_DQS
| rowspan="3" |M20
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DQS
|-
|ALT1
|QSPI_A_DQS
|-
|ALT5
|GPIO3_IO14
|-
|J1.126
(NAND on board)
|NAND_ALE
|CPU.NAND_ALE
|G19
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.174126(eMMC on board)|USB2_TXNrowspan="3" |NAND_ALE| rowspan="3" |CPU.USB2_TX_NNAND_ALE|B9rowspan="3" |G19|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_ALE
|-
|J1.176|USB2_TXP|CPU.USB2_TX_P|A9||D||ALT1|QSPI_A_SCLK
|-
|J1.178|USB1_RXN|CPU.USB1_RX_N|B12||D||ALT5|GPIO3_IO00
|-
| rowspan="2" |J1.180128(NAND on board)| rowspan="2" |USB1_RXPSD1_CLK| rowspan="2" |CPU.USB1_RX_PSD1_CLK| rowspan="2" |L25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_CLK|-|A12ALT5|GPIO2_IO00|D-| rowspan="3" |J1.128(eMMC on board)| rowspan="3" |NAND_CE0_B| rowspan="3" |CPU.NAND_CE0_B| rowspan="3" |H19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE0_B
|-
|J1.182|USB1_TXN|CPU.USB1_TX_N|B13||D||ALT1|QSPI_A_SS0_B
|-
|J1.184|USB1_TXP|CPU.USB1_TX_P|A13||D||ALT5|GPIO3_IO01
|-
| rowspan="2" |J1.186130(NAND on board)|USB1_VBUSrowspan="2" |SD1_CMD| rowspan="2" |CPU.USB1_VBUSSD1_CMD|D14rowspan="2" |L24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|SUSDHC1_CMD|-|ALT5|GPIO2_IO01
|-
| rowspan="3" |J1.188130(eMMC on board)|USB2_VBUSrowspan="3" |NAND_CE1_B| rowspan="3" |CPU.USB2_VBUSNAND_CE1_B|D9rowspan="3" |G21| -rowspan="3" |NVCC_3V3|Srowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE1_B
|-
|J1.190|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT1|QSPI_A_SS1_B
|-
|J1.192|USB1_ID|CPU.USB1_ID|C14|VDD_PHY_3V3|I||ALT5|GPIO3_IO02
|-
| rowspan="2" |J1.194132(NAND on board)|USB2_IDrowspan="2" |SD1_RST_B| rowspan="2" |CPU.USB2_IDSD1_RST_B|C9rowspan="2" |R24|VDD_PHY_3V3rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_RESET_B
|-
|J1.196|USB1_DN|CPU.USB1_DN|B14| -|D||ALT5|GPIO2_IO10
|-
| rowspan="3" |J1.198132(eMMC on board)|USB1_DProwspan="3" |NAND_CE2_B| rowspan="3" |CPU.USB1_DPNAND_CE2_B| rowspan="3" |F21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|A14rowspan="3" || -ALT0|DRAWNAND_CE2_B|-|ALT1|QSPI_B_SS0_B
|-
|J1.200|USB2_DP|CPU.USB2_DP|A10| -|D||ALT5|GPIO3_IO03
|-
| rowspan="2" |J1.202134(NAND on board)|USB2_DNrowspan="2" |SD1_STROBE| rowspan="2" |CPU.USB2_DNSD1_STROBE|B10rowspan="2" |T24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_STROBE
|-
|ALT5|GPIO2_IO11|-| rowspan="3" |J1.204134(eMMC on board)| rowspan="3" |NAND_CE3_B|DGNDrowspan="3" |CPU.NAND_CE3_B|DGNDrowspan="3" |H20| -rowspan="3" |NVCC_3V3|<nowiki>-<rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_CE3_B
|-
|}ALT1 ===Pinout Table J4 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! latexfontsize="scriptsize" | Alternative FunctionsQSPI_B_SS1_B
|-
|J4.1|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT5|GPIO3_IO034
|-
|J4J1.2136(NAND on board)|SAI1_RXD7NAND_CLE|CPU.SAI1_RXD7NAND_CLE|G1H21
|NVCC_3V3
|I/O
|internally Internally used for BOOT configNAND, do not connect|
|
|-
|J4rowspan="3" |J1.136(eMMC on board)| rowspan="3" |NAND_CLE|SAI1_RXD6rowspan="3" |CPU.SAI1_RXD6NAND_CLE|G2rowspan="3" |H21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internally used for BOOT configrowspan="3" ||ALT0|RAWNAND_CLE
|-
|J4.4|SAI1_RXD5|CPU.SAI1_RXD5|F1|NVCC_3V3|I/O|internally used for BOOT configALT1|QSPI_B_SCLK
|-
|J4.5|SAI1_RXD4|CPU.SAI1_RXD4|J1|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO3_IO05
|-
|J4rowspan="2" |J1.6138(NAND on board)| rowspan="2" |SAI1_RXD3SD1_DATA0| rowspan="2" |CPU.SAI1_RXD3SD1_DATA0|J2rowspan="2" |M25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|internally used for BOOT configrowspan="2" ||ALT0|USDHC1_DATA0
|-
|J4.7|SAI1_RXD2|CPU.SAI1_RXD2|H2|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO2_IO02
|-
|J4rowspan="3" |J1.8138(eMMC on board)|SAI1_RXD1rowspan="3" |NAND_DATA00| rowspan="3" |CPU.SAI1_RXD1NAND_DATA00|L2rowspan="3" |G20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internally used for BOOT configrowspan="3" ||ALT0|RAWNAND_DATA00
|-
|J4.9|SAI1_RXD0|CPU.SAI1_RXD0|K2|NVCC_3V3|I/O|internally used for BOOT configALT1|QSPI_A_DATA0
|-
|J4.10|SAI1_RXC|CPU.SAI1_RXC|K1|NVCC_3V3|I/O|ALT5|GPIO3_IO06
|-
|J4rowspan="2" |J1.11140(NAND on board)| rowspan="2" |SAI1_RXFSSD1_DATA1| rowspan="2" |CPU.SAI1_RXFSSD1_DATA1|L1rowspan="2" |M24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|rowspan="2" ||ALT0|USDHC1_DATA1
|-
|J4.12|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT5|GPIO2_IO0
|-
|J4rowspan="3" |J1.13140(eMMC on board)|SAI1_MCLKrowspan="3" |NAND_DATA01| rowspan="3" |CPU.SAI1_MCLKNAND_DATA01|rowspan="3" |J20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|rowspan="3" ||ALT0|RAWNAND_DATA01
|-
|J4ALT1|QSPI_A_DATA1|-|ALT5|GPIO3_IO07|-| rowspan="2" |J1.14142(NAND on board)| rowspan="2" |SD1_DATA2| rowspan="2" |CPU.SD1_DATA2| rowspan="2" |N25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA2|-|ALT5|GPIO2_IO04|-| rowspan="3" |J1.142(eMMC on board)| rowspan="3" |NAND_DATA02| rowspan="3" |CPU.NAND_DATA02| rowspan="3" |H22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA02|-|ALT1|QSPI_A_DATA2|-|ALT5|GPIO3_IO08|-| rowspan="2" |J1.144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |P25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.146
|DGND
|DGND
|G
|
|
|-
|J4.15
|SAI1_TXFS
|CPU.SAI1_TXFS
|H4
|NVCC_3V3
|I/O
|
|
|-
|J4rowspan="2" |J1.16148(NAND on board)| rowspan="2" |SAI1_TXCSD1_DATA4| rowspan="2" |CPU.SAI1_TXCSD1_DATA4|J5rowspan="2" |N24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|rowspan="2" ||ALT0|USDHC1_DATA4
|-
|J4.17|SAI1_TXD0|CPU.SAI1_TXD0|F2|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO2_IO06
|-
|J4rowspan="3" |J1.18148(eMMC on board)|SAI1_TXD1rowspan="3" |NAND_DATA04| rowspan="3" |CPU.SAI1_TXD1NAND_DATA04|E2rowspan="3" |L20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internally used for BOOT configrowspan="3" ||ALT0|RAWNAND_DATA04
|-
|J4.19|SAI1_TXD2|CPU.SAI1_TXD2|B2|NVCC_3V3|I/O|internally used for BOOT configALT1|QSPI_B_DATA0
|-
|J4.20|SAI1_TXD3|CPU.SAI1_TXD3|D1|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO3_IO10
|-
|J4rowspan="2" |J1.21150(NAND on board)| rowspan="2" |SAI1_TXD4SD1_DATA5| rowspan="2" |CPU.SAI1_TXD4SD1_DATA5|D2rowspan="2" |P24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|internally used for BOOT configrowspan="2" ||ALT0|USDHC1_DATA5
|-
|J4.22|SAI1_TXD5|CPU.SAI1_TXD5|C2|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO2_IO07
|-
|J4rowspan="3" |J1.23150(eMMC on board)|SAI1_TXD6rowspan="3" |NAND_DATA05| rowspan="3" |CPU.SAI1_TXD6NAND_DATA05|B3rowspan="3" |J22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internally used for BOOT configrowspan="3" ||ALT0|RAWNAND_DATA05
|-
|J4.24|SAI1_TXD7|CPU.SAI1_TXD7|C1|NVCC_3V3|I/O|internally used for BOOT configALT1|QSPI_B_DATA1
|-
|J4.25ALT5|DGND|DGND| -|<nowiki>-</nowiki>|G|||}===Pinout Table J5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! latexfontsize="scriptsize" | Alternative FunctionsGPIO3_IO11
|-
|J5rowspan="2" |J1.1152(NAND on board)| rowspan="2" |DGNDSD1_DATA6|DGNDrowspan="2" |CPU.SD1_DATA6| -rowspan="2" |R25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|<nowiki>-<rowspan="2" |I/nowiki>O| rowspan="2" ||ALT0|GUSDHC1_DATA6|-|ALT5|GPIO2_IO08
|-
|J5rowspan="3" |J1.2152(eMMC on board)|PCIE2_RXNrowspan="3" |NAND_DATA06| rowspan="3" |CPU.PCIE2_RXN_NNAND_DATA06| rowspan="3" |L19|D24rowspan="3" |NVCC_3V3| -rowspan="3" |I/O|Drowspan="3" ||ALT0|RAWNAND_DATA06
|-
|J5.3|PCIE2_RXP|CPU.PCIE2_RXN_P|D25| -|D|ALT1|QSPI_B_DATA2
|-
|J5ALT5|GPIO3_IO12|-| rowspan="2" |J1.4154(NAND on board)|DGNDrowspan="2" |SD1_DATA7|DGNDrowspan="2" |CPU.SD1_DATA7| rowspan="2" |T25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7| -|<nowiki>ALT5|GPIO2_IO09|-<| rowspan="3" |J1.154(eMMC on board)| rowspan="3" |NAND_DATA07| rowspan="3" |CPU.NAND_DATA07| rowspan="3" |M19| rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT5|GPIO3_IO13
|-
|J5J1.5156(NAND on board)|PCIE2_TXNNAND_RE_B|CPU.PCIE2_TXN_NNAND_RE_B|K19|E24NVCC_3V3| -I/O|DInternally used for NAND, do not connect
|
|
|-
|J5rowspan="3" |J1.6156(eMMC on board)|PCIE2_TXProwspan="3" |NAND_RE_B| rowspan="3" |CPU.PCIE2_TXN_PNAND_RE_B| rowspan="3" |K19| rowspan="3" |NVCC_3V3|E25rowspan="3" |I/O| -rowspan="3" ||ALT0|RAWNAND_RE_B|D-|ALT1|QSPI_B_DQS
|-
|J5.7|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT5|GPIO3_IO15
|-
|J5J1.8158(NAND on board)|PCIE2_REF_CLKNNAND_READY_B|CPU.PCIE2_REF_PAD_CLK_NNAND_READY_B|K20|F24NVCC_3V3| -I/O|DInternally used for NAND, do not connect
|
|
|-
|J5rowspan="2" |J1.9158(eMMC on board)|PCIE2_REF_CLKProwspan="2" |NAND_READY_B| rowspan="2" |CPU.PCIE2_REF_PAD_CLK_PNAND_READY_B| rowspan="2" |K20|F25rowspan="2" |NVCC_3V3| -rowspan="2" |I/O|Drowspan="2" ||ALT0|RAWNAND_READY_B
|-
|J5.10|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT5|GPIO3_IO16
|-
|J5J1.11160(NAND on board)|CSI_P2_CKNNAND_WE_B|CPU.MIPI_CSI2_CLK_NNAND_WE_B|K22|A19NVCC_3V3| -I/O|DInternally used for NAND, do not connect
|
|
|-
|J5rowspan="2" |J1.12160(eMMC on board)| rowspan="2" |CSI_P2_CKPNAND_WE_B| rowspan="2" |CPU.MIPI_CSI2_CLK_PNAND_WE_B|B19rowspan="2" |K22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_WE_B| -|DALT5|GPIO3_IO17|-|J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|K21|NVCC_3V3|I/O|Internally used for NAND, do not connect
|
|
|-
|J5rowspan="2" |J1.13162(eMMC on board)| rowspan="2" |NAND_WP_B| rowspan="2" |CPU.NAND_WP_B| rowspan="2" |K21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_WP_B|-|ALT5|GPIO3_IO18|-|J1.164
|DGND
|DGND
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5J1.14166|CSI_P2_DN0CLK1_N|CPU.MIPI_CSI2_D0_NCLK1_N|C20T23| -
|D
|
|
|
|-
|J5J1.15168|CSI_P2_DP0CLK1_P|CPU.MIPI_CSI2_D0_PCLK1_P|D10R23| -
|D
|
|
|
|-
|J5J1.16170|CSI_P2_DN1USB2_RXN|CPU.MIPI_CSI2_D1_NUSB2_RX_N|A20B8| -
|D
|
|
|
|-
|J5J1.17172|CSI_P2_DP1USB2_RXP|CPU.MIPI_CSI2_D1_PUSB2_RX_P|B20A8| -
|D
|
|
|
|-
|J5J1.18174|DGNDUSB2_TXN|DGND| -|<nowiki>-</nowiki>CPU.USB2_TX_N|GB9
|
|D
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|-
|J5J1.20176|CSI_P2_DP2USB2_TXP|CPU.MIPI_CSI2_D2_PUSB2_TX_P|B21A9| -
|D
|
|
|
|-
|J5J1.21178|CSI_P2_DN3USB1_RXN|CPU.MIPI_CSI2_D3_NUSB1_RX_N|C19B12| -
|D
|
|
|
|-
|J5J1.22180|CSI_P2_DP3USB1_RXP|CPU.MIPI_CSI2_D3_PUSB1_RX_P|D19A12| -
|D
|
|
|
|-
|J5J1.23182|DGNDUSB1_TXN|DGNDCPU.USB1_TX_N|B13| -|<nowiki>-</nowiki>D|G
|
|
|-
|J5J1.24184|I2C4_SCLUSB1_TXP|CPU.I2C4_SCLUSB1_TX_P|F8A13|NVCC_3V3|I/OD|
|
|
|-
|J5J1.25186|I2C4_SDAUSB1_VBUS|CPU.I2C4_SDAUSB1_VBUS|F9D14|NVCC_3V3-|I/OS|Absolute maximum ratings 5.25V|||-|J1.188|USB2_VBUS|CPU.USB2_VBUS|D9| -|S|Absolute maximum ratings 5.25V
|
|
|}
 
===Pinout Table JD5 pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! latexfontsize="scriptsize" | Alternative Functions
|-
|JD5J1.1190
|DGND
|DGND
|G
|
|
|-
|JD5.2
|EEPROM_WP
|Internal EEPROM Write Protect
| -
|NVCC_3V3
|I
|
|
|-
|JD5J1.3192|NCUSB1_ID|Not ConnectedCPU.USB1_ID|C14| -VDD_PHY_3V3| -I|Z
|
|
|-
|JD5J1.4194|JTAG_TCKUSB2_ID|CPU.JTAG_TCKUSB2_ID|T5C9|NVCC_3V3VDD_PHY_3V3
|I
|internal pull-up 10k to NVCC_3V3
|
|-
|JD5.5
|JTAG_TMS
|CPU.JTAG_TMS
|V5
|NVCC_3V3
|I
|
|
|-
|JD5J1.6196|JTAG_TDOUSB1_DN|CPU.JTAG_TDOUSB1_DN|U5B14|NVCC_3V3-|D|O
|
|
|-
|JD5J1.7198|JTAG_TDIUSB1_DP|CPU.JTAG_TDIUSB1_DP|W5A14|NVCC_3V3-|D|I
|
|
|-
|JD5J1.8200|JTAG_nTRSTUSB2_DP|CPU.JTAG_TRST_BUSB2_DP|U6A10|NVCC_3V3-|D|I
|
|
|-
|JD5J1.9202|CPU_PORnUSB2_DN|CPU.POR_BUSB2_DNPMIC.RESETMCU|B10|W203-|NVCC_SNVSD|I/O|internal pull-up 100k to NVCC_SNVS
|
|-
|JD5J1.10204|NVCC_3V3DGND|NVCC_3V3DGND
| -
|<nowiki>-</nowiki>
|SG|
|
|
|-
|}
 
==ONE PIECE J4 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J4.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="7" |J4.2
| rowspan="7" |SAI1_RXD7
| rowspan="7" |CPU.SAI1_RXD7
| rowspan="7" |G1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT2
|SAI1_TX_SYNC
|-
|ALT3
|SAI1_TX_DATA4
|-
|ALT4
|CORESIGHT_TRACE7
|-
|ALT5
|GPIO4_IO09
|-
|ALT6
|SRC_BOOT_CFG7
|-
| rowspan="6" |J4.3
| rowspan="6" |SAI1_RXD6
| rowspan="6" |CPU.SAI1_RXD6
| rowspan="6" |G2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA6
|-
|ALT1
|SAI6_TX_SYNC
|-
|ALT2
|SAI6_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE6
|-
|ALT5
|GPIO4_IO08
|-
|ALT6
|SRC_BOOT_CFG6
|-
| rowspan="7" |J4.4
| rowspan="7" |SAI1_RXD5
| rowspan="7" |CPU.SAI1_RXD5
| rowspan="7" |F1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA5
|-
|ALT1
|SAI6_TX_DATA0
|-
|ALT2
|SAI6_RX_DATA0
|-
|ALT3
|SAI1_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE5
|-
|ALT5
|GPIO4_IO07
|-
|ALT6
|SRC_BOOT_CFG5
|-
| rowspan="6" |J4.5
| rowspan="6" |SAI1_RXD4
| rowspan="6" |CPU.SAI1_RXD4
| rowspan="6" |J1
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA4
|-
|ALT1
|SAI6_TX_BCLK
|-
|ALT2
|SAI6_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE4
|-
|ALT5
|GPIO4_IO06
|-
|ALT6
|SRC_BOOT_CFG4
|-
| rowspan="5" |J4.6
| rowspan="5" |SAI1_RXD3
| rowspan="5" |CPU.SAI1_RXD3
| rowspan="5" |J2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA3
|-
|ALT1
|SAI5_RX_DATA3
|-
|ALT4
|CORESIGHT_TRACE3
|-
|ALT5
|GPIO4_IO05
|-
|ALT6
|SRC_BOOT_CFG3
|-
| rowspan="5" |J4.7
| rowspan="5" |SAI1_RXD2
| rowspan="5" |CPU.SAI1_RXD2
| rowspan="5" |H2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA2
|-
|ALT1
|SAI5_RX_DATA2
|-
|ALT4
|CORESIGHT_TRACE2
|-
|ALT5
|GPIO4_IO04
|-
|ALT6
|SRC_BOOT_CFG2
|-
| rowspan="5" |J4.8
| rowspan="5" |SAI1_RXD1
| rowspan="5" |CPU.SAI1_RXD1
| rowspan="5" |L2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA1
|-
|ALT1
|SAI5_RX_DATA1
|-
|ALT4
|CORESIGHT_TRACE1
|-
|ALT5
|GPIO4_IO03
|-
|ALT6
|SRC_BOOT_CFG1
|-
| rowspan="5" |J4.9
| rowspan="5" |SAI1_RXD0
| rowspan="5" |CPU.SAI1_RXD0
| rowspan="5" |K2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA0
|-
|ALT1
|SAI5_RX_DATA0
|-
|ALT4
|CORESIGHT_TRACE0
|-
|ALT5
|GPIO4_IO02
|-
|ALT6
|SRC_BOOT_CFG0
|-
| rowspan="4" |J4.10
| rowspan="4" |SAI1_RXC
| rowspan="4" |CPU.SAI1_RXC
| rowspan="4" |K1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_BCLK
|-
|ALT1
|SAI5_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE_CTL
|-
|ALT5
|GPIO4_IO01
|-
| rowspan="4" |J4.11
| rowspan="4" |SAI1_RXFS
| rowspan="4" |CPU.SAI1_RXFS
| rowspan="4" |L1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_SYNC
|-
|ALT1
|SAI5_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE_CLK
|-
|ALT5
|GPIO4_IO00
|-
|J4.12
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.13
| rowspan="4" |SAI1_MCLK
| rowspan="4" |CPU.SAI1_MCLK
| rowspan="4" |
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_MCLK
|-
|ALT1
|SAI5_MCLK
|-
|ALT2
|SAI1_TX_BCLK
|-
|ALT5
|GPIO4_IO20
|-
|J4.14
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.15
| rowspan="4" |SAI1_TXFS
| rowspan="4" |CPU.SAI1_TXFS
| rowspan="4" |H4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_SYNC
|-
|ALT1
|SAI5_TX_SYNC
|-
|ALT4
|CORESIGHT_EVENTO
|-
|ALT5
|GPIO4_IO10
|-
| rowspan="4" |J4.16
| rowspan="4" |SAI1_TXC
| rowspan="4" |CPU.SAI1_TXC
| rowspan="4" |J5
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_BCLK
|-
|ALT1
|SAI5_TX_BCLK
|-
|ALT4
|CORESIGHT_EVENTI
|-
|ALT5
|GPIO4_IO11
|-
| rowspan="5" |J4.17
| rowspan="5" |SAI1_TXD0
| rowspan="5" |CPU.SAI1_TXD0
| rowspan="5" |F2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA0
|-
|ALT1
|SAI5_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE8
|-
|ALT5
|GPIO4_IO12
|-
|ALT6
|SRC_BOOT_CFG8
|-
| rowspan="5" |J4.18
| rowspan="5" |SAI1_TXD1
| rowspan="5" |CPU.SAI1_TXD1
| rowspan="5" |E2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1
|-
|ALT1
|SAI5_TX_DATA1
|-
|ALT4
|CORESIGHT_TRACE9
|-
|ALT5
|GPIO4_IO13
|-
|ALT6
|SRC_BOOT_CFG9
|-
| rowspan="5" |J4.19
| rowspan="5" |SAI1_TXD2
| rowspan="5" |CPU.SAI1_TXD2
| rowspan="5" |B2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA2
|-
|ALT1
|SAI5_TX_DATA2
|-
|ALT4
|CORESIGHT_TRACE10
|-
|ALT5
|GPIO4_IO14
|-
|ALT6
|SRC_BOOT_CFG10
|-
| rowspan="5" |J4.20
| rowspan="5" |SAI1_TXD3
| rowspan="5" |CPU.SAI1_TXD3
| rowspan="5" |D1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3
|-
|ALT1
|SAI5_TX_DATA3
|-
|ALT4
|CORESIGHT_TRACE11
|-
|ALT5
|GPIO4_IO15
|-
|ALT6
|SRC_BOOT_CFG11
|-
| rowspan="6" |J4.21
| rowspan="6" |SAI1_TXD4
| rowspan="6" |CPU.SAI1_TXD4
| rowspan="6" |D2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4
|-
|ALT1
|SAI6_RX_BCLK
|-
|ALT2
|SAI6_TX_BCLK
|-
|ALT4
|CORESIGHT_TRACE12
|-
|ALT5
|GPIO4_IO16
|-
|ALT6
|SRC_BOOT_CFG12
|-
| rowspan="6" |J4.22
| rowspan="6" |SAI1_TXD5
| rowspan="6" |CPU.SAI1_TXD5
| rowspan="6" |C2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5
|-
|ALT1
|SAI6_RX_DATA0
|-
|ALT2
|SAI6_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE13
|-
|ALT5
|GPIO4_IO17
|-
|ALT6
|SRC_BOOT_CFG13
|-
| rowspan="6" |J4.23
| rowspan="6" |SAI1_TXD6
| rowspan="6" |CPU.SAI1_TXD6
| rowspan="6" |B3
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6
|-
|ALT1
|SAI6_RX_SYNC
|-
|ALT2
|SAI6_TX_SYNC
|-
|ALT4
|CORESIGHT_TRACE14
|-
|ALT5
|GPIO4_IO18
|-
|ALT6
|SRC_BOOT_CFG14
|-
| rowspan="5" |J4.24
| rowspan="5" |SAI1_TXD7
| rowspan="5" |CPU.SAI1_TXD7
| rowspan="5" |C1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT4
|CORESIGHT_TRACE15
|-
|ALT5
|GPIO4_IO19
|-
|ALT6
|SRC_BOOT_CFG15
|-
|J4.25
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|}
 
==ONE PIECE J5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.2
|PCIE2_RXN
|CPU.PCIE2_RXN_N
|D24
| -
|D
|
|
|
|-
|J5.3
|PCIE2_RXP
|CPU.PCIE2_RXN_P
|D25
| -
|D
|
|
|
|-
|J5.4
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.5
|PCIE2_TXN
|CPU.PCIE2_TXN_N
|E24
| -
|D
|
|
|
|-
|J5.6
|PCIE2_TXP
|CPU.PCIE2_TXN_P
|E25
| -
|D
|
|
|
|-
|J5.7
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.8
|PCIE2_REF_CLKN
|CPU.PCIE2_REF_PAD_CLK_N
|F24
| -
|D
|
|
|
|-
|J5.9
|PCIE2_REF_CLKP
|CPU.PCIE2_REF_PAD_CLK_P
|F25
| -
|D
|
|
|
|-
|J5.10
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|
|-
|J5.12
|CSI_P2_CKP
|CPU.MIPI_CSI2_CLK_P
|B19
| -
|D
|
|
|
|-
|J5.13
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.14
|CSI_P2_DN0
|CPU.MIPI_CSI2_D0_N
|C20
| -
|D
|
|
|
|-
|J5.15
|CSI_P2_DP0
|CPU.MIPI_CSI2_D0_P
|D10
| -
|D
|
|
|
|-
|J5.16
|CSI_P2_DN1
|CPU.MIPI_CSI2_D1_N
|A20
| -
|D
|
|
|
|-
|J5.17
|CSI_P2_DP1
|CPU.MIPI_CSI2_D1_P
|B20
| -
|D
|
|
|
|-
|J5.18
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|
|-
|J5.20
|CSI_P2_DP2
|CPU.MIPI_CSI2_D2_P
|B21
| -
|D
|
|
|
|-
|J5.21
|CSI_P2_DN3
|CPU.MIPI_CSI2_D3_N
|C19
| -
|D
|
|
|
|-
|J5.22
|CSI_P2_DP3
|CPU.MIPI_CSI2_D3_P
|D19
| -
|D
|
|
|
|-
|J5.23
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J5.24
| rowspan="4" |I2C4_SCL
| rowspan="4" |CPU.I2C4_SCL
| rowspan="4" |F8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SCL
|-
|ALT1
|PWM2_OUT
|-
|ALT2
|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO5_IO20
|-
| rowspan="4" |J5.25
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |F9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SDA
|-
|ALT1
|PWM1_OUT
|-
|ALT2
|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO5_IO21
|}
U0007
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