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MITO 8M SOM/MITO 8M Hardware/Pinout Table
237 bytes added
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11:00, 25 September 2020
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Pinout Table ODD pins declaration
|NVCC_1V8
|I/O
|
must
Must
be level translated if used @ 3V3
|
|
|NVCC_1V8
|I/O
|
must
Must
be level translated if used @ 3V3
|
|
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
Internally used for ETH PHY reset, do not connect
|ALT0
|GPIO1_IO01
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
Internally used, do not connect
|ALT0
|GPIO1_IO13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
Internally used for MIPI-to-LVDS interrupt, do not connect
|ALT0
|GPIO1_IO05
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|GPIO1_IO06
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02
U0005
a000298_approval, dave_user
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