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MITO 8M SOM/MITO 8M Hardware/Pinout Table

4,679 bytes added, 10:39, 25 September 2020
→‎Pinout Table J4 pins declaration
|ALT5
|GPIO3_IO00
|-
| rowspan="2" |J1.128
(NAND on board)
| rowspan="2" |SD1_CLK
| rowspan="2" |CPU.SD1_CLK
| rowspan="2" |L25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC1_CLK
|-
|ALT5
|GPIO2_IO00
|-
| rowspan="3" |J1.128
(eMMCon board)| rowspan="3" |NAND_CE0_B // SD1_CLK
| rowspan="3" |CPU.NAND_CE0_B
| rowspan="3" |H19
|GPIO3_IO01
|-
| rowspan="2" |J1.128130(NANDon board)| rowspan="2" |NAND_CE0_B SD1_CMD| rowspan="2" |CPU.SD1_CMD| rowspan="2" |L24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_CMD|-|ALT5|GPIO2_IO01|-| rowspan="3" |J1.130(eMMC on board)| rowspan="3" |NAND_CE1_B| rowspan="3" |CPU.NAND_CE1_B| rowspan="3" |G21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE1_B|-|ALT1|QSPI_A_SS1_B|-|ALT5|GPIO3_IO02|-| rowspan="2" |J1.132(NAND on board)| rowspan="2" |SD1_RST_B| rowspan="2" |CPU.SD1_RST_B| rowspan="2" |R24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_RESET_B|-|ALT5|GPIO2_IO10|-| rowspan="3" |J1.132(eMMC on board)| rowspan="3" |NAND_CE2_B| rowspan="3" |CPU.NAND_CE2_B| rowspan="3" |F21| rowspan="3" |NVCC_3V3| rowspan="3" |I/ SD1_CLKO| rowspan="3" ||ALT0|RAWNAND_CE2_B|-|ALT1|QSPI_B_SS0_B|-|ALT5|GPIO3_IO03|-| rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_CLKSD1_STROBE| rowspan="2" |L25T24
| rowspan="2" |NVCC_3V3
 
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC1_CLKUSDHC1_STROBE
|-
|ALT5
|GPIO2_IO00GPIO2_IO11
|-
| rowspan="3" |J1.130134(eMMC on board)|NAND_CE1_B // SD1_CMDrowspan="3" |NAND_CE3_B| rowspan="3" |CPU.NAND_CE1_B // CPU.SD1_CMDNAND_CE3_B|G21 // L24rowspan="3" |H20|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE3_B
|-
|J1.132|NAND_CE2_B // SD1_RST_B|CPU.NAND_CE2_B // CPU.SD1_RST_B|F21 // R24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_B_SS1_B
|-
|J1.134|NAND_CE3_B // SD1_STROBE|CPU.NAND_CE3_B // CPU.SD1_STROBE|H20 // T24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO034
|-
|J1.136
(NAND on board)
|NAND_CLE
|DGNDCPU.NAND_CLE
|H21
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|
|-
| rowspan="3" |J1.136(eMMC on board)| rowspan="3" |NAND_CLE| rowspan="3" |CPU.NAND_CLE| rowspan="3" |H21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CLE|-|ALT1|QSPI_B_SCLK|-|ALT5|GPIO3_IO05|-| rowspan="2" |J1.138(NAND on board)| rowspan="2" |SD1_DATA0| rowspan="2" |CPU.SD1_DATA0| rowspan="2" |M25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA0|-|ALT5|GPIO2_IO02|-| rowspan="3" |J1.138(eMMC on board)| rowspan="3" |NAND_DATA00 // SD1_DATA0| rowspan="3" |CPU.NAND_DATA00 | rowspan="3" |G20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA00|-|ALT1|QSPI_A_DATA0|-|ALT5|GPIO3_IO06|-| rowspan="2" |J1.140(NAND on board)| rowspan="2" |SD1_DATA1| rowspan="2" |CPU.SD1_DATA1| rowspan="2" |M24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/ O| rowspan="2" ||ALT0|USDHC1_DATA1|-|ALT5|GPIO2_IO0|-| rowspan="3" |J1.140(eMMC on board)| rowspan="3" |NAND_DATA01| rowspan="3" |CPU.SD1_DATA0NAND_DATA01| rowspan="3" |J20| rowspan="3" |NVCC_3V3|G20 rowspan="3" |I// M25O| rowspan="3" ||ALT0|RAWNAND_DATA01|-|ALT1|QSPI_A_DATA1|-|ALT5|GPIO3_IO07|-| rowspan="2" |J1.142(NAND on board)| rowspan="2" |SD1_DATA2| rowspan="2" |CPU.SD1_DATA2| rowspan="2" |N25|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA2|-|ALT5|GPIO2_IO04|-| rowspan="3" |J1.142(eMMC on board)| rowspan="3" |NAND_DATA02| rowspan="3" |CPU.NAND_DATA02| rowspan="3" |H22| rowspan="3" |NVCC_3V3| rowspan="3" |I/ O| rowspan="3" ||ALT0|RAWNAND_DATA02|-|ALT1|QSPI_A_DATA2|-|ALT5|GPIO3_IO08|-| rowspan="2" |J1.144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |P25| rowspan="2" |NVCC_3V3 ???(NVCC_1V8 on request)| rowspan="2" |I/O|???rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05
|-
| rowspan="3" |J1.140144(eMMC on board)|NAND_DATA01 // SD1_DATA1rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA01 // CPU.SD1_DATA1NAND_DATA03|J20 // M24rowspan="3" |J21|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_DATA03
|-
|J1.142|NAND_DATA02 // SD1_DATA2|CPU.NAND_DATA02 // CPU.SD1_DATA2|H22 // N25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_A_DATA3
|-
|J1.144|NAND_DATA03 // SD1_DATA3|CPU.NAND_DATA03 // CPU.SD1_DATA3|J21 // P25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO09
|-
|J1.146
|
|-
| rowspan="2" |J1.148(NAND on board)| rowspan="2" |SD1_DATA4| rowspan="2" |CPU.SD1_DATA4| rowspan="2" |N24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4|-|ALT5|GPIO2_IO06|-| rowspan="3" |J1.148(eMMC on board)| rowspan="3" |NAND_DATA04 | rowspan="3" |CPU.NAND_DATA04| rowspan="3" |L20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA04|-|ALT1|QSPI_B_DATA0|-|ALT5|GPIO3_IO10|-| rowspan="2" |J1.150(NAND on board)| rowspan="2" |SD1_DATA5| rowspan="2" |CPU.SD1_DATA5| rowspan="2" |P24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/ SD1_DATA4O| rowspan="2" ||ALT0|USDHC1_DATA5|-|ALT5|GPIO2_IO07|-| rowspan="3" |J1.150(eMMC on board)| rowspan="3" |NAND_DATA05| rowspan="3" |CPU.NAND_DATA04 NAND_DATA05| rowspan="3" |J22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA05|-|ALT1|QSPI_B_DATA1|-|ALT5|GPIO3_IO11|-| rowspan="2" |J1.152(NAND on board)| rowspan="2" |SD1_DATA6| rowspan="2" |CPU.SD1_DATA6| rowspan="2" |R25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/ O| rowspan="2" ||ALT0|USDHC1_DATA6|-|ALT5|GPIO2_IO08|-| rowspan="3" |J1.152(eMMC on board)| rowspan="3" |NAND_DATA06| rowspan="3" |CPU.SD1_DATA4NAND_DATA06| rowspan="3" |L19| rowspan="3" |NVCC_3V3|L20 rowspan="3" |I// N24O| rowspan="3" ||ALT0|RAWNAND_DATA06|-|ALT1|QSPI_B_DATA2|-|ALT5|GPIO3_IO12|-| rowspan="2" |J1.154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |T25|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I// O| rowspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09|-| rowspan="3" |J1.154(eMMC on board)| rowspan="3" |NAND_DATA07| rowspan="3" |CPU.NAND_DATA07| rowspan="3" |M19| rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_DATA07
|-
|J1.150|NAND_DATA05 // SD1_DATA5|CPU.NAND_DATA05 // CPU.SD1_DATA5|J22 // P24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_B_DATA3
|-
|J1.152|NAND_DATA06 // SD1_DATA6|CPU.NAND_DATA06 // CPU.SD1_DATA6|L19 // R25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO13
|-
|J1.154156(NAND on board)|NAND_DATA07 // SD1_DATA7NAND_RE_B|CPU.NAND_DATA07 // CPU.SD1_DATA7NAND_RE_B|M19 // T25K19|NVCC_1V8 // NVCC_3V3 ???
|I/O
|???Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.156
(eMMC on board)
| rowspan="3" |NAND_RE_B
| rowspan="3" |CPU.NAND_RE_B
|ALT5
|GPIO3_IO15
|-
|J1.158
(NAND on board)
|NAND_READY_B
|CPU.NAND_READY_B
|K20
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="2" |J1.158
(eMMC on board)
| rowspan="2" |NAND_READY_B
| rowspan="2" |CPU.NAND_READY_B
|ALT5
|GPIO3_IO16
|-
|J1.160
(NAND on board)
|NAND_WE_B
|CPU.NAND_WE_B
|K22
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="2" |J1.160
(eMMC on board)
| rowspan="2" |NAND_WE_B
| rowspan="2" |CPU.NAND_WE_B
|ALT5
|GPIO3_IO17
|-
|J1.162
(NAND on board)
|NAND_WP_B
|CPU.NAND_WP_B
|K21
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="2" |J1.162
(eMMC on board)
| rowspan="2" |NAND_WP_B
| rowspan="2" |CPU.NAND_WP_B
U0005
a000298_approval, dave_user
299
edits
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