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→Pinout Table
<section begin=Body/>
==Pinout Table==
===Introduction===
This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the ''TBD: connector type'' 204-pin SO-DIMM MITO 8M connector.
Each row in the pinout tables contains the following information:
{| class="wikitable"
! latexfontsize="scriptsize"| Pin ! latexfontsize="scriptsize"| Pin Name! latexfontsize="scriptsize"| Internal Connections ! latexfontsize="scriptsize"| Ball/pin # ! latexfontsize="scriptsize"| <nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize"| Type ! latexfontsize="scriptsize"| Notes! latexfontsize="scriptsize"| Alternative Functions
|-
|J1.1
|DGND|DGND|-|<nowiki>-</nowiki>|G
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|-
|J1.3
|3.3VIN|INPUT VOLTAGE|-|3.3VIN|S
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|-
|J1.5
|3.3VIN|INPUT VOLTAGE|-|3.3VIN|S
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|-
|J1.7
|3.3VIN|INPUT VOLTAGE|-|3.3VIN|S
|
|
|-
|J1.9
|3.3VIN|INPUT VOLTAGE|-|3.3VIN|S
|
|
|-
|J1.11
|DGND|DGND|-|-|G
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|
|-
|J1.13
|ETH0_LED1|LAN.LED1/PME_N1|17|NVCC_1V8|O|must be level translated if used @ 3V3
|
|-
|J1.15
|ETH0_LED2|LAN.LED2|15|NVCC_1V8|O|must be level translated if used @ 3V3
|
|-
|J1.17
|DGND|DGND|-|-|G
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|-
|J1.19
|ETH0_TXRX0_P|LAN.TXRXP_A|2|-|D
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|
|-
|J1.21
|ETH0_TXRX0_M|LAN.TXRXM_A|3|-|D
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|-
|J1.23
|ETH0_TXRX1_P|LAN.TXRXP_B|5|-|D
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|-
|J1.25
|ETH0_TXRX1_M|LAN.TXRXM_B|6|-|D
|
|
|-
|J1.27
|ETH0_TXRX2_P|LAN.TXRXP_C|7|-|D
|
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|-
|J1.29
|ETH0_TXRX2_M|LAN.TXRXM_C|8|-|D
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|-
|J1.31
|ETH0_TXRX3_P|LAN.TXRXP_D|10|-|D
|
|
|-
|J1.33
|ETH0_TXRX3_M|LAN.TXRXM_D|11|-|D
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|-
|J1.35
|DGND|DGND|-|-|G
|
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|-
|J1.37
|GPIO1_IO00
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|