a000298_approval, dave_user
299
edits
Changes
→RAM memory bank
| align="center" style="background:#f0f0f0;" |'''USB'''
|-
| i.MX8M Dual || 2 x 2x Arm® Cortex®-A53 1 x 1x Arm® Cortex®-M4
| rowspan="2" |1.3 GHz
1.5 GHz
up tp 4kp60
| rowspan="2" |1 x 1x HDMI 2.0a1 x 1x MIPI-DSI
(with MIPI to LVDS bridge)
| rowspan="2" |2 x 2x MIPI CSI
(4-lanes each)
| rowspan="2" | 2 x 2x PCIe 2.0
(1-lane each)
| rowspan="2" |2 x 2x USB 3.0
Dual role
|-
| i.MX8M Quad || 4 x 4x Arm® Cortex®-A53 1 x 1x Arm® Cortex®-M4
|-
|+ align="bottom" style="caption-side: bottom" | Table: i.MX8M models comparison
=== RAM memory bank ===
{| class="wikitable" |
|-
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
|-
| '''Size max'''||4 GB
|-
| '''Width'''||64 32 bit
|-
| '''Speed'''||533 1600 MHz
|-
|}
=== NOR eMMC flash bank ===
{| class="wikitable" |
|-
| '''CPU connection'''||eCSPI channel 5SDIO1
|-
| '''Size min'''||8 MB 4 GB
|-
| '''Size max'''||64 MB |-| '''Chip select'''||ECSPI5_SS0GB
|-
| '''Bootable'''||Yes
=== NAND flash bank ===
{| class="wikitable" |
| '''CPU connection'''||Raw NAND flash controller
|-
| '''Page size'''|| 512 byte, 2 kbyte or 4 kbyteTBD
|-
| '''Size min'''||128 MB TBD
|-
| '''Size max'''||2 GB TBD
|-
| '''Width'''||8 bit
|-
| '''Chip select'''||NANDF_CS0|-| '''Bootable'''||Yes |-|} === eMMC flash bank === {| class="wikitable" | |-| '''CPU connection'''|| SDIO|-| '''Page size'''|| xxxxxx |-| '''Size min'''||xxx MB |-| '''Size max'''||xxx GB |-| '''Width'''|| xx bit |-| '''SDHC'''||TBD
|-
| '''Bootable'''||Yes
MITO 8M embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
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[[Category:MITO 8M]]