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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Sep 2020/12/29
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
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<section end="History" />
__FORCETOC__
<section begin="Body" />
== Power Supply Unit (PSU) and recommended power-up sequence ==
Implementing correct power-up sequence for ''iMX8M Mini/Nano'' processors is not a trivial task because several power rails are involved.
MITO 8M Mini SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
[[File:MITO 8MMito8MMini-power-sequence.png | 800px500x500px]]
The PSU is composed of two main blocks:
# SNVS domain signals are pulled-up (unless carrier board circuitry keeps this signal low for any reason)
# CPU_PORn (active-low) is driven low by PMIC
# RTC_RESET_B are internally released after 200ms# VDD_SOC regulator starts and enables the VDD_ARM and PMIC regulators10ms# PMIC initiates power-up sequence needed by iMX8M Mini/Nano processor# BOARD_PGOOD goes up when NVCC_3V3 (all CPU I/O power rail) is ready
# CPU_PORn is deasserted after the last regulator to bring the processor out of reset
[[Category:MITO 8M Mini]]
[[Category:MITO 8M Nano]]