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MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table

23,204 bytes added, 18:06, 27 December 2023
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=== Connectors description ===
In the following table are described all available connectors integrated on MITO 8M Mini/Nano SOM:
{| class="wikitable"
|-
|-
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini/Nano pinout specifications. See the images below for reference:
[[File:MITO8M_Mini-conn-top.png|500px|thumb|MITO 8M Mini/Nano TOP view|none]]
|-
|'''Pin Name'''
| Pin (signal) name on the MITO 8M Mini/Nano connectors
|-
|'''Internal<br>connections'''
==SODIMM J1 ODD pins declaration ==
==SODIMM J1 EVEN pins declaration == {| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
|-
|J1.21
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.43|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.65|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.87|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.109|3.3VIN
|INPUT VOLTAGE
| -
|
|-
|J1.1211
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.1413|PMIC_LICELL ETH0_LED1|PMICLAN.LICELLLED1/PME_N1|4617| NVCC_1V8|I/O|Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap|S
|
|-
|J1.15
|ETH0_LED2
|LAN.LED2
|15
|NVCC_1V8
|I/O
|Must be level translated if used @ 3V3
Internally pulled-up to 1.8V during bootstrap
|
|
|-
|J1.1617|CPU_ONOFFDGND|CPU.ONOFFDGND|A25-|NVCC_SNVS_1V8-|IG|internal pull-up 100k to NVCC_SNVS_1V8
|
|
|-
|J1.1819|BOARD_PGOODETH0_TXRX0_P|LAN.TXRXP_A|2
| -
|D
|
|
|
|-
|J1.21
|ETH0_TXRX0_M
|LAN.TXRXM_A
|3
| -
|NVCC_3V3|OD
|
|
|
|-
|J1.2023|BOOT_MODE_SELETH0_TXRX1_P|BOOT MODE SELECTIONLAN.TXRXP_B|5
| -
|NVCC_3V3D|I|internal pull-up to NVCC_3V3
|
|
|-
|J1.2225|CPU_PORnETH0_TXRX1_M|CPULAN.POR_BPMIC.RESET_MCUTXRXM_B|B24216|NVCC_SNVS_1V8-|I/OD|internal pull-up 100k to NVCC_SNVS_1V8
|
|
|-
|J1.2427|PMIC_PWRONETH0_TXRX2_P|PMICLAN.PWRONTXRXP_C| 227
| -
|ID|internal pull-up 100k to VIN
|
|
|-
| rowspan="5" |J1.2629| rowspan="5" |SAI3_RXCETH0_TXRX2_M| rowspan="5" |CPULAN.SAI3_RXCTXRXM_C| rowspan="5" |AG78| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OD| rowspan="5" ||ALT0|SAI3_RX_BCLK
|-
|ALT1J1.31|ETH0_TXRX3_P|LAN.TXRXP_D|10| -|D|||GPT1_CLK
|-
|ALT2J1.33|SAI5_RX_BCLKETH0_TXRX3_M(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2)|LAN.TXRXM_D|11| -|D|||
|-
|ALT4J1.35|UART2_CTS_BDGND|DGND|-|ALT5-|G|||GPIO4_IO29
|-
| rowspan="4" |J1.2837| rowspan="4" |GPIO1_IO02GPIO1_IO00| rowspan="4" |CPU.GPIO1_IO02GPIO1_IO00| rowspan="4" |AG13AG14
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for PMIC WDI, do not connect
|ALT0
|GPIO1_IO02GPIO1_IO00
|-
|ALT1
|WDOG1_WDOG_BCCM_ENET_PHY_REF_CLK_ROOT
|-
|ALT5
|WDOG1_WDOG_ANYCCM_REF_CLK_32K
|-
|ALT7ALT6|SJC_DE_BCCM_EXT_CLK1
|-
|J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="54" |J1.3239| rowspan="54" |SAI3_RXDGPIO1_IO01| rowspan="54" |CPU.SAI3_RXDGPIO1_IO01| rowspan="54" |AF7AF14| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |Internally used for ETH PHY reset, do not connect
|ALT0
|SAI3_RX_DATA0GPIO1_IO01
|-
|ALT1
|GPT1_COMPARE1PWM1_OUT
|-
|ALT2ALT5|SAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT2)CCM_REF_CLK_24M
|-
|ALT4ALT6|UART2_RTS_BCCM_EXT_CLK2(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT4)|-| rowspan="3" |J1.41| rowspan="3" |SPDIF_EXT_CLK| rowspan="3" |CPU.SPDIF_EXT_CLK| rowspan="3" |AF8| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SPDIF1_EXT_CLK|-|ALT1|PWM1_OUT
|-
|ALT5
|GPIO4_IO30GPIO5_IO05
|-
| rowspan="3" |J1.3443| rowspan="3" |SAI2_MCLKGPIO1_IO13| rowspan="3" |CPU.SAI2_MCLKGPIO1_IO13| rowspan="3" |AD19AD9
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_MCLKGPIO1_IO13
|-
|ALT1
|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)USB1_OTG_OC
|-
|ALT5
|GPIO4_IO27PWM2_OUT
|-
| rowspan="52" |J1.3645| rowspan="52" |SAI3_RXFSGPIO1_IO11| rowspan="52" |CPU.SAI3_RXFSGPIO1_IO11| rowspan="52" |AG8AC10| rowspan="52" |NVCC_3V3| rowspan="52" |I/O| rowspan="52" |Internally used for ETH CLK enable, do not connect
|ALT0
|SAI3_RX_SYNCGPIO1_IO11
|-
|ALT1
|GPT1_CAPTURE1USB1_OTG_ID
|-
|ALT2rowspan="3" |J1.47| rowspan="3" |ECSPI2_SCLK| rowspan="3" |CPU.ECSPI2_SCLK| rowspan="3" |E6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|SAI5_RX_SYNCrowspan="3" |(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT2)|ALT0|ECSPI2_SCLK
|-
|ALT3ALT1|SAI3_RX_DATA1UART4_RX
|-
|ALT5
|GPIO4_IO28GPIO5_IO10
|-
| rowspan="43" |J1.3849| rowspan="43" |I2C3_SCLECSPI2_MOSI| rowspan="43" |CPU.I2C3_SCLECSPI2_MOSI| rowspan="43" |E10B8| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C3_SCLECSPI2_MOSI
|-
|ALT1
|PWM4_OUT|-|ALT2|GPT2_CLKUART4_TX
|-
|ALT5
|GPIO5_IO18GPIO5_IO11
|-
| rowspan="63" |J1.4051| rowspan="63" |SAI3_TXFSGPIO1_IO08| rowspan="63" |CPU.SAI3_TXFSGPIO1_IO08| rowspan="63" |AC6AG10| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" ||ALT0|SAI3_TX_SYNCGPIO1_IO08
|-
|ALT1
|GPT1_CAPTURE2ENET1_1588_EVENT0_IN|-|ALT5|USDHC2_RESET_B
|-
|ALT2rowspan="4" |J1.53| rowspan="4" |GPIO1_IO09| rowspan="4" |CPU.GPIO1_IO09| rowspan="4" |AF10| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|SAI5_RX_DATA1rowspan="4" |(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT2)|ALT0|GPIO1_IO09
|-
|ALT3ALT1|SAI3_TX_DATA1ENET1_1588_EVENT0_OUT
|-
|ALT4
|UART2_RXUSDHC3_RESET_B
|-
|ALT5
|GPIO4_IO31SDMA2_EXT_EVENT0
|-
| rowspan="3" |J1.4255| rowspan="3" |SPDIF_RXECSPI2_MISO| rowspan="3" |CPU.SPDIF_RXECSPI2_MISO| rowspan="3" |AG9A8
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_INECSPI2_MISO
|-
|ALT1
|PWM2_OUTUART4_CTS_B
|-
|ALT5
|GPIO5_IO04GPIO5_IO12
|-
|J1.57|DGND |DGND| -| -|G||||-| rowspan="3" |J1.4459| rowspan="3" |SPDIF_TXECSPI2_SS0| rowspan="3" |CPU.SPDIF_TXECSPI2_SS0| rowspan="3" |AF9A6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_OUTECSPI2_SS0|-|ALT1|UART4_RTS_B(Configure register IOMUXC_UART4_RTS_B_SELECT_INPUT for mode ALT1)|-|ALT5|GPIO5_IO13|-| rowspan="3" |J1.61| rowspan="3" |GPIO1_IO05| rowspan="3" |CPU.GPIO1_IO05| rowspan="3" |AF12| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3|ALT0|GPIO1_IO05
|-
|ALT1
|PWM3_OUTM4_NMI
|-
|ALT5
|GPIO5_IO03CCM_PMIC_READY
|-
| rowspan="4" |J1.4663| rowspan="4" |SAI3_MCLKSAI5_RXD0| rowspan="4" |CPU.SAI3_MCLKSAI5_RXD0| rowspan="4" |AD6AD18
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI3_MCLKSAI5_RX_DATA0( Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT0)
|-
|ALT1
|PWM4_OUTSAI1_TX_DATA2
|-
|ALT2ALT4|SAI5_MCLKPDM_BIT_STREAM0(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT2ALT4)
|-
|ALT5
|GPIO5_IO02GPIO3_IO21
|-
| rowspan="46" |J1.4865| rowspan="46" |I2C3_SDASAI5_RXD1| rowspan="46" |CPU.I2C3_SDASAI5_RXD1| rowspan="46" |F10AC14| rowspan="46" |NVCC_3V3| rowspan="46" |I/O| rowspan="46" |
|ALT0
|I2C3_SDASAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT0)
|-
|ALT1
|PWM3_OUTSAI1_TX_DATA3
|-
|ALT2
|GPT3_CLKSAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI5_TX_SYNC(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT3)|-|ALT4|PDM_BIT_STREAM1(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT4)
|-
|ALT5
|GPIO5_IO19GPIO3_IO22
|-
| rowspan="54" |J1.5067| rowspan="54" |SAI3_TXCGPIO1_IO06| rowspan="54" |CPU.SAI3_TXCGPIO1_IO06| rowspan="54" |AG6AG11| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|SAI3_TX_BCLKGPIO1_IO06
|-
|ALT1
|GPT1_COMPARE2ENET1_MDC
|-
|ALT2ALT5|SAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT2)USDHC1_CD_B
|-
|ALT4ALT6|UART2_TXCCM_EXT_CLK3
|-
|ALT5|GPIO5_IO00|-| rowspan="4" |J1.5269| rowspan="4" |SAI3_TXDSAI2_RXC| rowspan="4" |CPU.SAI3_TXDSAI2_RXC| rowspan="4" |AF6AB22
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI3_TX_DATA0SAI2_RX_BCLK
|-
|ALT1
|GPT1_COMPARE3SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|ALT2ALT4|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT2)UART1_RX
|-
|ALT5
|GPIO5_IO01GPIO4_IO22
|-
| rowspan="56" |J1.5471| rowspan="56" |SAI1_MCLKSAI2_RXFS| rowspan="56" |CPU.SAI1_MCLKSAI2_RXFS| rowspan="56" |AB18AC19| rowspan="56" |NVCC_3V3| rowspan="56" |I/O| rowspan="56" |
|ALT0
|SAI1_MCLKSAI2_RX_SYNC
|-
|ALT1
|SAI5_MCLKSAI5_TX_SYNC(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
|-
|ALT2
|SAI1_TX_BCLK(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT2)SAI5_TX_DATA1
|-
|ALT3
|PDM_CLKSAI2_RX_DATA1|-|ALT4|UART1_TX
|-
|ALT5
|GPIO4_IO20GPIO4_IO21
|-
|J1.5673|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
| rowspan="32" |J1.5875| rowspan="32" |SAI5_MCLKSD2_DATA0| rowspan="32" |CPU.SAI5_MCLKSD2_DATA0| rowspan="32" |AD15AB23| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT0)|-|ALT1|SAI1_TX_BCLK(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT1)USDHC2_DATA0
|-
|ALT5
|GPIO3_IO25GPIO2_IO15
|-
| rowspan="2" |J1.6077| rowspan="2" |GPIO1_IO10SD2_DATA1| rowspan="2" |CPU.GPIO1_IO10SD2_DATA1| rowspan="2" |AD10AB24
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |Internally used for ETH PHY interrupt, do not connect
|ALT0
|GPIO1_IO10USDHC2_DATA1
|-
|ALT1ALT5|USB1_OTG_IDGPIO2_IO16
|-
| rowspan="32" |J1.6279| rowspan="32" |SAI5_RXFSSD2_DATA2| rowspan="32" |CPU.SAI5_RXFSSD2_DATA2| rowspan="32" |AB15V24| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT0)|-|ALT1|SAI1_TX_DATA0USDHC2_DATA2
|-
|ALT5
|GPIO3_IO19GPIO2_IO17
|-
| rowspan="42" |J1.6481| rowspan="42" |SAI5_RXCSD2_DATA3| rowspan="42" |CPU.SAI5_RXCSD2_DATA03| rowspan="42" |AC15V23| rowspan="42" |NVCC_3V3| rowspan="42" |I/O| rowspan="42" |
|ALT0
|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT0)USDHC2_DATA3
|-
|ALT1ALT5|SAI1_TX_DATA1GPIO2_IO18
|-
|ALT4rowspan="2" |J1.83| rowspan="2" |SD2_CMD| rowspan="2" |CPU.SD2_CMD| rowspan="2" |W24| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|PDM_CLKUSDHC2_CMD
|-
|ALT5
|GPIO3_IO20GPIO2_IO14
|-
| rowspan="32" |J1.6685| rowspan="32" |SAI2_TXCSD2_CLK| rowspan="32" |CPU.SAI2_TXCSD2_CLK| rowspan="32" |AD22W23| rowspan="32" |NVCC_3V3| rowspan="32" |I/O| rowspan="32" |
|ALT0
|SAI2_TX_BCLK|-|ALT1|SAI5_TX_DATA2USDHC2_CLK
|-
|ALT5
|GPIO4_IO25GPIO2_IO13
|-
|J1.87|DGND |DGND| -| -|G||||-| rowspan="34" |J1.6889| rowspan="34" |SAI2_TXD0UART3_TXD| rowspan="34" |CPU.SAI2_TXD0UART3_TXD| rowspan="34" |AC22D18| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |Internally pulled-up to NVCC_3V3
|ALT0
|SAI2_TX_DATA0UART3_TX
|-
|ALT1
|SAI5_TX_DATA3UART1_RTS_B(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT1)|-|ALT2|USDHC3_VSELECT
|-
|ALT5
|GPIO4_IO26GPIO5_IO27
|-
| rowspan="54" |J1.7091| rowspan="54" |SAI2_TXFSUART3_RXD| rowspan="54" |CPU.SAI2_TXFSUART3_RXD| rowspan="54" |AD23E18| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |
|ALT0
|SAI2_TX_SYNCUART3_RX
|-
|ALT1
|SAI5_TX_DATA1UART1_CTS_B
|-
|ALT3ALT2|SAI2_TX_DATA1|-|ALT4|UART1_CTS_BUSDHC3_RESET_B
|-
|ALT5
|GPIO4_IO24GPIO5_IO26
|-
| rowspan="4" |J1.72| rowspan="4" |SAI2_RXD0| rowspan="4" |CPU.SAI2_RXD0| rowspan="4" |AC24| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI2_RX_DATA0|-|ALT1|SAI5_TX_DATA0|-|ALT4|UART1_RTS_B(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT4)|-|ALT5|GPIO4_IO23|-| rowspan="3" |J1.7493| rowspan="3" |I2C4_SDAUART1_TXD| rowspan="3" |CPU.I2C4_SDAUART1_TXD| rowspan="3" |E13F13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|I2C4_SDA UART1_TX
|-
|ALT1
|PWM1_OUTECSPI3_MOSI
|-
|ALT5
|GPIO5_IO21GPIO5_IO23
|-
| rowspan="3" |J1.7695| rowspan="3" |I2C4_SCLUART1_RXD| rowspan="3" |CPU.I2C4_SCLUART1_RXD| rowspan="3" |D13E14
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|I2C4_SCLUART1_RX
|-
|ALT1
|PWM2_OUTECSPI3_SCLK
|-
|ALT5
|GPIO5_IO20GPIO5_IO22
|-
| rowspan="62" |J1.7897| rowspan="62" |SAI5_RXD2SD2_WP| rowspan="62" |CPU.SAI5_RXD2SD2_WP| rowspan="62" |AD13AA27| rowspan="62" |NVCC_3V3| rowspan="62" |I/O| rowspan="62" |
|ALT0
|SAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT0)USDHC2_WP
|-
|ALT1ALT5|SAI1_TX_DATA4GPIO2_IO20
|-
|ALT2rowspan="2" |J1.99| rowspan="2" |SD2_RST_B| rowspan="2" |CPU.SD2_RESET_B| rowspan="2" |AB26| rowspan="2" |NVCC_3V3| rowspan="2" |I/O|SAI1_TX_SYNCrowspan="2" |(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|ALT0|USDHC2_RESET_B
|-
|ALT3ALT5|SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT3)GPIO2_IO19
|-
|ALT4rowspan="4" |J1.101| rowspan="4" |I2C2_SCL| rowspan="4" |CPU.I2C2_SCL| rowspan="4" |D10| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|I2C2_SCL|-|ALT1|ENET1_1588_EVENT1_IN|-|ALT2|PDM_BIT_STREAM2USDHC3_CD_B(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT4ALT2)
|-
|ALT5
|GPIO3_IO23GPIO5_IO16
|-
| rowspan="64" |J1.80103| rowspan="64" |SAI5_RXD3I2C2_SDA| rowspan="64" |CPU.SAI5_RXD3I2C2_SDA| rowspan="64" |AC13D9| rowspan="64" |NVCC_3V3| rowspan="64" |I/O| rowspan="64" |
|ALT0
|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT0)I2C2_SDA
|-
|ALT1
|SAI1_TX_DATA5ENET1_1588_EVENT1_OUT
|-
|ALT2
|SAI1_TX_SYNCUSDHC3_WP(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)|-|ALT3|SAI5_TX_DATA0|-|ALT4|PDM_BIT_STREAM3(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT4)
|-
|ALT5
|GPIO3_IO24GPIO5_IO17
|-
| rowspan="6" |J1.82105| rowspan="6" |SAI1_RXD3| rowspan="6" |CPU.SAI1_RXD3| rowspan="6" |AF17|DGNDrowspan="6" | NVCC_3V3|DGNDrowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|<nowiki>-<MITO 8M Mini SOM P/nowiki>N composition]]|ALT0|GSAI1_RX_DATA3|-|ALT1|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT1)
|-
|J1.84ALT3|PDM_BIT_STREAM3|||||||(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT3)
|-
|ALT4|CORESIGHT_TRACE3|-|ALT5|GPIO4_IO05|-|ALT6|SRC_BOOT_CFG3|-| rowspan="5" |J1.107| rowspan="5" |SAI1_TXD3| rowspan="5" |CPU.SAI1_TXD3| rowspan="5" |AF21| rowspan="5" | NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA3|-|ALT1|SAI5_TX_DATA3|-|ALT4|CORESIGHT_TRACE11|-|ALT5|GPIO4_IO15|-|ALT6|SRC_BOOT_CFG11|-|J1.109|DGND |DGND| -| -|G||||-| rowspan="4" |J1.111| rowspan="4" |SAI1_TXFS| rowspan="4" |CPU.SAI1_TXFS| rowspan="4" |AB19| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_TX_SYNC (Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_TX_SYNC(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT4|CORESIGHT_EVENTO|-|ALT5|GPIO4_IO10|-| rowspan="4" |J1.113| rowspan="4" |SAI1_TXC| rowspan="4" |CPU.SAI1_TXC| rowspan="4" |AC18| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_TX_BCLK (Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT4|CORESIGHT_EVENTI|-|ALT5|GPIO4_IO11|-| rowspan="5" |J1.115| rowspan="5" |SAI1_TXD0| rowspan="5" |CPU.SAI1_TXD0| rowspan="5" |AG20| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA0|-|ALT1|SAI5_TX_DATA0|-|ALT4|CORESIGHT_TRACE8|-|ALT5|GPIO4_IO12|-|ALT6|SRC_BOOT_CFG8|-| rowspan="5" |J1.117| rowspan="5" |SAI1_TXD1| rowspan="5" |CPU.SAI1_TXD1| rowspan="5" |AF20| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA1|-|ALT1|SAI5_TX_DATA1|-|ALT4|CORESIGHT_TRACE9|-|ALT5|GPIO4_IO13|-|ALT6|SRC_BOOT_CFG9|-| rowspan="5" |J1.119| rowspan="5" |SAI1_TXD2| rowspan="5" |CPU.SAI1_TXD2| rowspan="5" |AG21| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA2|-|ALT1|SAI5_TX_DATA2|-|ALT4|CORESIGHT_TRACE10|-|ALT5|GPIO4_IO14|-|ALT6|SRC_BOOT_CFG10|-| rowspan="4" |J1.121| rowspan="4" |SAI1_RXFS| rowspan="4" |CPU.SAI1_RXFS| rowspan="4" |AG16| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_SYNC (Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT4|CORESIGHT_TRACE_CLK|-|ALT5|GPIO4_IO00|-| rowspan="4" |J1.123| rowspan="4" |SAI1_RXC| rowspan="4" |CPU.SAI1_RXC| rowspan="4" |AF16| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_BCLK|-|ALT1|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT4|CORESIGHT_TRACE_CTL|-|ALT5|GPIO4_IO01|-| rowspan="7" |J1.125| rowspan="7" |SAI1_RXD0| rowspan="7" |CPU.SAI1_RXD0| rowspan="7" |AG15| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA0|-|ALT1|SAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT1)|-|ALT2|SAI1_TX_DATA1|-|ALT3|PDM_BIT_STREAM0(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT3)|-|ALT4|CORESIGHT_TRACE0|-|ALT5|GPIO4_IO02|-|ALT6|SRC_BOOT_CFG0|-| rowspan="6" |J1.127| rowspan="6" |SAI1_RXD1| rowspan="6" |CPU.SAI1_RXD1| rowspan="6" |AF15| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA1|-|ALT1|SAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT1)|-|ALT3|PDM_BIT_STREAM1(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT3)|-|ALT4|CORESIGHT_TRACE1|-|ALT5|GPIO4_IO03|-|ALT6|SRC_BOOT_CFG1|-| rowspan="6" |J1.129| rowspan="6" |SAI1_RXD2| rowspan="6" |CPU.SAI1_RXD2| rowspan="6" |AG17| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA2|-|ALT1|SAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT1)|-|ALT3|PDM_BIT_STREAM2(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT3)|-|ALT4|CORESIGHT_TRACE2|-|ALT5|GPIO4_IO04|-|ALT6|SRC_BOOT_CFG2|-|J1.131|DGND |DGND| -| -|G||||-|J1.133|LVDS0_CLK_N|BRIDGE.A_CLKN|F9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.133|DSI_CLK_N|CPU.MIPI_DSI_CLK_N|A11| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.135|LVDS0_CLK_P|BRIDGE.A_CLKP|F8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.135|DSI_CLK_P|CPU.MIPI_|B11| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.137|LVDS0_TX0_N|BRIDGE.A_Y0N|C9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.137|DSI_D0_N|CPU.MIPI_DSI_D0_N|A9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.139|LVDS0_TX0_P|BRIDGE.A_Y0P|C8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.139|DSI_D0_P|CPU.MIPI_DSI_D0_P|B9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.141|LVDS0_TX1_N|BRIDGE.A_Y1N|D9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.141|DSI_D1_N|CPU.MIPI_DSI_D1_N|A10| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.143|LVDS0_TX1_P|BRIDGE.A_Y1P|D8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.143|DSI_D1_P|CPU.MIPI_DSI_D1_P|B10| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.145|LVDS0_TX2_N|BRIDGE.A_Y2N|E9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.145|DSI_D2_N|CPU.MIPI_DSI_D2_N|A12| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.147|LVDS0_TX2_P|BRIDGE.A_Y2P|E8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.147|DSI_D2_P|CPU.MIPI_DSI_D2_P|B12| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.149|LVDS0_TX3_N|BRIDGE.A_Y3N|G9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.149|DSI_D3_N|CPU.MIPI_DSI_D3_N|A13| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.151|LVDS0_TX3_P|BRIDGE.A_Y3P|G8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.151|DSI_D3_P|CPU.MIPI_DSI_D3_P|B13| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.153|DGND |DGND| -| -|G||||-|J1.155|LVDS1_CLK_N|BRIDGE.B_CLKN|A6| -|D||||-|J1.157|LVDS1_CLK_P|BRIDGE.B_CLKP|B6| -|D||||-|J1.159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D||||-|J1.161|LVDS1_TX0_P|BRIDGE.B_Y0P|B3| -|D||||-|J1.163|LVDS1_TX1_N|BRIDGE.B_Y1N|A4| -|D||||-|J1.165|LVDS1_TX1_P|BRIDGE.B_Y1P|B4| -|D||||-|J1.167|LVDS1_TX2_N|BRIDGE.B_Y2N|A5| -|D||||-|J1.169|LVDS1_TX2_P|BRIDGE.B_Y2P|B5| -|D||||-|J1.171|LVDS1_TX3_N|BRIDGE.B_Y3N|A7| -|D||||-|J1.173|LVDS1_TX3_P|BRIDGE.B_Y3P|B7| -|D||||-|J1.175|DGND |DGND| -| -|G||||-| rowspan="2" |J1.177| rowspan="2" |SD2_CD_B| rowspan="2" |CPU.SD2_CD_B| rowspan="2" |AA26| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_CD_B|-|ALT5|GPIO2_IO12|-| rowspan="3" |J1.179| rowspan="3" |ECSPI1_SS0| rowspan="3" |CPU.ECSPI1_SS0| rowspan="3" |B6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_SS0|-|ALT1|UART3_RTS_B(Configure register IOMUXC_UART3_RTS_B_SELECT_INPUT for mode ALT1)|-|ALT5|GPIO5_IO09|-| rowspan="3" |J1.181| rowspan="3" |ECSPI1_SCLK| rowspan="3" |CPU.ECSPI1_SCLK| rowspan="3" |D6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_SCLK|-|ALT1|UART3_RX|-|ALT5|GPIO5_IO06|-| rowspan="3" |J1.183| rowspan="3" |ECSPI1_MISO| rowspan="3" |CPU.ECSPI1_MISO| rowspan="3" |A7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_MISO|-|ALT1|UART3_CTS_B|-|ALT5|GPIO5_IO08|-| rowspan="3" |J1.185| rowspan="3" |GPIO1_IO03| rowspan="3" |CPU.GPIO1_IO03| rowspan="3" |AF13| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |Internally used for PMIC interrupt, do not connect Pulled-up to NVCC_3V3|ALT0|GPIO1_IO03|-|ALT1|USDHC1_VSELECT|-|ALT5|SDMA1_EXT_EVENT0|-| rowspan="3" |J1.187| rowspan="3" |UART2_TXD| rowspan="3" |CPU.UART2_TXD| rowspan="3" |E15| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |used as default Linux console|ALT0|UART2_TX|-|ALT1|ECSPI3_SS0|-|ALT5|GPIO5_IO25|-| rowspan="3" |J1.189| rowspan="3" |UART2_RXD| rowspan="3" |CPU.UART2_RXD| rowspan="3" |F15| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |used as default Linux console|ALT0|UART2_RXD|-|ALT1|ECSPI3_MISO|-|ALT5|GPIO5_IO24|-| rowspan="3" |J1.191| rowspan="3" |UART4_TXD| rowspan="3" |CPU.UART4_TXD| rowspan="3" |F18| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART4_TX|-|ALT1|UART2_RTS_B(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT1)|-|ALT5|GPIO5_IO29|-| rowspan="4" |J1.193| rowspan="4" |UART4_RXD| rowspan="4" |CPU.UART4_RXD| rowspan="4" |F19| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|UART4_RX|-|ALT1|UART2_CTS_B|-|ALT2|PCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO5_IO28|-| rowspan="3" |J1.195| rowspan="3" |ECSPI1_MOSI| rowspan="3" |CPU.ECSPI1_MOSI| rowspan="3" |B7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_MOSI|-|ALT1|UART3_TX|-|ALT5|GPIO5_IO07|-| rowspan="5" |J1.197| rowspan="5" |GPIO1_IO14| rowspan="5" |CPU.GPIO1_IO14| rowspan="5" |AC9| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|GPIO1_IO14|-|ALT1|USB2_OTG_PWR|-|ALT4|USDHC3_CD_B(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT4)|-|ALT5|PWM3_OUT|-|ALT6|CCM_CLKO1|-| rowspan="3" |J1.199| rowspan="3" |GPIO1_IO04| rowspan="3" |CPU.GPIO1_IO04| rowspan="3" |AG12| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO04|-|ALT1|USDHC2_VSELECT|-|ALT5|SDMA1_EXT_EVENT1|-| rowspan="3" |J1.201| rowspan="3" |GPIO1_IO12| rowspan="3" |CPU.GPIO1_IO12| rowspan="3" |AB10| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO12|-|ALT1|USB1_OTG_PWR|-|ALT5|SDMA2_EXT_EVENT1|-|J1.203|DGND |DGND| -| -|G||||-|} ==SODIMM J1 EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" | Alternative Functions|-|J1.2|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J1.4|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S||||-|J1.6|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S||||-|J1.8|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S||||-|J1.10|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S||||-|J1.12|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J1.14|PMIC_LICELL |PMIC.LICELL|46| -|S||||-|J1.16|CPU_ONOFF|CPU.ONOFF|A25|NVCC_SNVS_1V8|I|internal pull-up 100k to NVCC_SNVS_1V8|||-|J1.18|BOARD_PGOOD| -| -|NVCC_3V3|O||||-|J1.20|BOOT_MODE_SEL|BOOT MODE SELECTION| -|NVCC_3V3|I|internal pull-up to NVCC_3V3|||-|J1.22|CPU_PORn|CPU.POR_BPMIC.RESET_MCU|B2421|NVCC_SNVS_1V8|I/O|internal pull-up 100k to NVCC_SNVS_1V8|||-|J1.24|PMIC_PWRON|PMIC.PWRON| 22| '''(*)''' 3.3VIN|I|internal pull-up 100k to VIN'''(*)''' default as ''Embedded'' power mode|||-| rowspan="5" |J1.26| rowspan="5" |SAI3_RXC| rowspan="5" |CPU.SAI3_RXC| rowspan="5" |AG7| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI3_RX_BCLK|-|ALT1|GPT1_CLK|-|ALT2|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|UART2_CTS_B|-|ALT5|GPIO4_IO29|-| rowspan="4" |J1.28| rowspan="4" |GPIO1_IO02| rowspan="4" |CPU.GPIO1_IO02| rowspan="4" |AG13| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" |Internally used for PMIC WDI, do not connect|ALT0|GPIO1_IO02|-|ALT1|WDOG1_WDOG_B|-|ALT5|WDOG1_WDOG_ANY|-|ALT7|SJC_DE_B|-|J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="5" |J1.32| rowspan="5" |SAI3_RXD| rowspan="5" |CPU.SAI3_RXD| rowspan="5" |AF7| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI3_RX_DATA0|-|ALT1|GPT1_COMPARE1|-|ALT2|SAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT2)|-|ALT4|UART2_RTS_B(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT4)|-|ALT5|GPIO4_IO30|-| rowspan="3" |J1.34| rowspan="3" |SAI2_MCLK| rowspan="3" |CPU.SAI2_MCLK| rowspan="3" |AD19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_MCLK|-|ALT1|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)|-|ALT5|GPIO4_IO27|-| rowspan="5" |J1.36| rowspan="5" |SAI3_RXFS| rowspan="5" |CPU.SAI3_RXFS| rowspan="5" |AG8| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI3_RX_SYNC|-|ALT1|GPT1_CAPTURE1|-|ALT2|SAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI3_RX_DATA1|-|ALT5|GPIO4_IO28|-| rowspan="4" |J1.38| rowspan="4" |I2C3_SCL| rowspan="4" |CPU.I2C3_SCL| rowspan="4" |E10| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|I2C3_SCL|-|ALT1|PWM4_OUT|-|ALT2|GPT2_CLK|-|ALT5|GPIO5_IO18|-| rowspan="6" |J1.40| rowspan="6" |SAI3_TXFS| rowspan="6" |CPU.SAI3_TXFS| rowspan="6" |AC6| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" ||ALT0|SAI3_TX_SYNC|-|ALT1|GPT1_CAPTURE2|-|ALT2|SAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT2)|-|ALT3|SAI3_TX_DATA1|-|ALT4|UART2_RX|-|ALT5|GPIO4_IO31|-| rowspan="3" |J1.42| rowspan="3" |SPDIF_RX| rowspan="3" |CPU.SPDIF_RX| rowspan="3" |AG9| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SPDIF1_IN|-|ALT1|PWM2_OUT|-|ALT5|GPIO5_IO04|-| rowspan="3" |J1.44| rowspan="3" |SPDIF_TX| rowspan="3" |CPU.SPDIF_TX| rowspan="3" |AF9| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SPDIF1_OUT|-|ALT1|PWM3_OUT|-|ALT5|GPIO5_IO03|-| rowspan="4" |J1.46| rowspan="4" |SAI3_MCLK| rowspan="4" |CPU.SAI3_MCLK| rowspan="4" |AD6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_MCLK|-|ALT1|PWM4_OUT|-|ALT2|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO5_IO02|-| rowspan="4" |J1.48| rowspan="4" |I2C3_SDA| rowspan="4" |CPU.I2C3_SDA| rowspan="4" |F10| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|I2C3_SDA|-|ALT1|PWM3_OUT|-|ALT2|GPT3_CLK|-|ALT5|GPIO5_IO19|-| rowspan="5" |J1.50| rowspan="5" |SAI3_TXC| rowspan="5" |CPU.SAI3_TXC| rowspan="5" |AG6| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI3_TX_BCLK|-|ALT1|GPT1_COMPARE2|-|ALT2|SAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT2)|-|ALT4|UART2_TX|-|ALT5|GPIO5_IO00|-| rowspan="4" |J1.52| rowspan="4" |SAI3_TXD| rowspan="4" |CPU.SAI3_TXD| rowspan="4" |AF6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_DATA0|-|ALT1|GPT1_COMPARE3|-|ALT2|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT2)|-|ALT5|GPIO5_IO01|-| rowspan="5" |J1.54| rowspan="5" |SAI1_MCLK| rowspan="5" |CPU.SAI1_MCLK| rowspan="5" |AB18| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI1_MCLK|-|ALT1|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI1_TX_BCLK(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT3|PDM_CLK|-|ALT5|GPIO4_IO20|-|J1.56|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="3" |J1.58| rowspan="3" |SAI5_MCLK| rowspan="3" |CPU.SAI5_MCLK| rowspan="3" |AD15| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT0)|-|ALT1|SAI1_TX_BCLK(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT5|GPIO3_IO25|-| rowspan="2" |J1.60| rowspan="2" |GPIO1_IO10| rowspan="2" |CPU.GPIO1_IO10| rowspan="2" |AD10| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0|GPIO1_IO10|-|ALT1|USB1_OTG_ID|-| rowspan="3" |J1.62| rowspan="3" |SAI5_RXFS| rowspan="3" |CPU.SAI5_RXFS| rowspan="3" |AB15| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT0)|-|ALT1|SAI1_TX_DATA0|-|ALT5|GPIO3_IO19|-| rowspan="4" |J1.64| rowspan="4" |SAI5_RXC| rowspan="4" |CPU.SAI5_RXC| rowspan="4" |AC15| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT0)|-|ALT1|SAI1_TX_DATA1|-|ALT4|PDM_CLK|-|ALT5|GPIO3_IO20|-| rowspan="3" |J1.66| rowspan="3" |SAI2_TXC| rowspan="3" |CPU.SAI2_TXC| rowspan="3" |AD22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_BCLK|-|ALT1|SAI5_TX_DATA2|-|ALT5|GPIO4_IO25|-| rowspan="3" |J1.68| rowspan="3" |SAI2_TXD0| rowspan="3" |CPU.SAI2_TXD0| rowspan="3" |AC22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_DATA0|-|ALT1|SAI5_TX_DATA3|-|ALT5|GPIO4_IO26|-| rowspan="5" |J1.70| rowspan="5" |SAI2_TXFS| rowspan="5" |CPU.SAI2_TXFS| rowspan="5" |AD23| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI2_TX_SYNC|-|ALT1|SAI5_TX_DATA1|-|ALT3|SAI2_TX_DATA1|-|ALT4|UART1_CTS_B|-|ALT5|GPIO4_IO24|-| rowspan="4" |J1.72| rowspan="4" |SAI2_RXD0| rowspan="4" |CPU.SAI2_RXD0| rowspan="4" |AC24| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI2_RX_DATA0|-|ALT1|SAI5_TX_DATA0|-|ALT4|UART1_RTS_B(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT4)|-|ALT5|GPIO4_IO23|-| rowspan="3" |J1.74| rowspan="3" |I2C4_SDA| rowspan="3" |CPU.I2C4_SDA| rowspan="3" |E13| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|I2C4_SDA |-|ALT1|PWM1_OUT|-|ALT5|GPIO5_IO21|-| rowspan="4" |J1.76| rowspan="4" |I2C4_SCL| rowspan="4" |CPU.I2C4_SCL| rowspan="4" |D13| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|I2C4_SCL|-|ALT1|PWM2_OUT|-|ALT2|PCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO5_IO20|-| rowspan="6" |J1.78| rowspan="6" |SAI5_RXD2| rowspan="6" |CPU.SAI5_RXD2| rowspan="6" |AD13| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" ||ALT0|SAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT0)|-|ALT1|SAI1_TX_DATA4|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT3)|-|ALT4|PDM_BIT_STREAM2(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT4)|-|ALT5|GPIO3_IO23|-| rowspan="6" |J1.80| rowspan="6" |SAI5_RXD3| rowspan="6" |CPU.SAI5_RXD3| rowspan="6" |AC13| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" ||ALT0|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT0)|-|ALT1|SAI1_TX_DATA5|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI5_TX_DATA0|-|ALT4|PDM_BIT_STREAM3(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT4)|-|ALT5|GPIO3_IO24|-|J1.82|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J1.84|PCIE1_REF_CLKN|CPU.PCIE_REF_CLK_N|A21|VDDA_1V8|D||||-|J1.86|PCIE1_REF_CLKP|CPU.PCIE_REF_CLK_P|B21|VDDA_1V8|D||||-|J1.88|CLKIN1|CPU.CLKIN1|H27|NVCC_3V3|I||||-|J1.90|CLKIN2|CPU.CLKIN2|J27|NVCC_3V3
|I
|
|-
|J1.92
|PCIE1_RXN|CPU.PCIE_RXN_N|A19|VDDA_1V8|D
|
|
|-
|J1.94
|PCIE1_RXP|CPU.PCIE_RXN_P|B19|VDDA_1V8|D
|
|
|-
|J1.96
|PCIE1_TXN|CPU.PCIE_TXN_N|A20|VDDA_1V8|D
|
|
|-
|J1.98
|PCIE1_TXP|CPU.PCIE_TXN_P|B20|VDDA_1V8|D
|
|
|-
|}
'''(*)''' PMIC_PWRON can be used in two configuration: ''Embedded-like'' (default mounting option) or ''Tablet-like''. In the first case, the system reboots in case of PMIC_PWR_ON signal activity.
 
In the second case, the system will shut down waiting for a CPU_ONOFF signal raising (like a button-mode in a tablet) and the PMIC_PWRON Voltage domain is NVCC_SNVS_1V8
Please contact [mailto:sales@dave.eu sales dept.] for more information
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[[Category:MITO 8M Mini]]
[[Category:MITO 8M Nano]]
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