Open main menu

DAVE Developer's Wiki β

Changes

MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table

8,097 bytes added, 18:06, 27 December 2023
no edit summary
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 14768|Dec 20202021/10/11}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2023/10/26
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Update pin information
|-
|}
=== Connectors description ===
In the following table are described all available connectors integrated on MITO 8M Mini/Nano SOM:
{| class="wikitable"
|-
|-
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini/Nano pinout specifications. See the images below for reference:
[[File:MITO_8M_Mini_MITO8M_Mini-_TOPconn-top.jpegpng|500px|thumb|MITO 8M Mini/Nano TOP view|none]][[File:MITO_8M_Mini_MITO8M_Mini-conn-_BOTTOMbottom.jpegpng|500px|thumb|MITO 8M Mini/Nano BOTTOM view|none]]
Below a detailed description of the pinout, grouped in the following tables:
|-
|'''Pin Name'''
| Pin (signal) name on the MITO 8M Mini connectors
|-
|'''Internal<br>connections'''
| Connections to the components
* CPU.<x> : pin connected to CPU pad named <x>(NXP iMX8MM)* PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210PF8121)
* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
| rowspan="5" | NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
|SAI1_TX_DATA3
|-
|
|ALT1
|SAI5_TX_DATA3
|-
|
|ALT4
|CORESIGHT_TRACE11
|-
|
|ALT5
|GPIO4_IO15
|-
|
|ALT6
|SRC_BOOT_CFG11
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.133
|DSI_CLK_N
|CPU.MIPI_DSI_CLK_N
|A11
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.135
|DSI_CLK_P
|CPU.MIPI_
|B11
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.137
|DSI_D0_N
|CPU.MIPI_DSI_D0_N
|A9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.139
|DSI_D0_P
|CPU.MIPI_DSI_D0_P
|B9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.141
|DSI_D1_N
|CPU.MIPI_DSI_D1_N
|A10
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.143
|DSI_D1_P
|CPU.MIPI_DSI_D1_P
|B10
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.145|DSI_D2_N|CPU.MIPI_DSI_D2_N|A12| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.147
|LVDS0_TX2_P
|BRIDGE.A_Y2P
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.147
|DSI_D2_P
|CPU.MIPI_DSI_D2_P
|B12
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.149
|DSI_D3_N
|CPU.MIPI_DSI_D3_N
|A13
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.151
|DSI_D3_P
|CPU.MIPI_DSI_D3_P
|B13
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for PMIC interrupt, do not connect Pulled-up to NVCC_3V3
|ALT0
|GPIO1_IO03
|PMIC.PWRON
| 22
| -'''(*)''' 3.3VIN
|I
|internal pull-up 100k to VIN
'''(*)''' default as ''Embedded'' power mode
|
|
|
|-
| rowspan="5" |J1.166|rowspan="5" |GPIO1_IO15|rowspan="5" |CPU.GPIO1_IO15|rowspan="5" |AB9|rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|GPIO1_IO15
|-
|J1.168|||||I/O||ALT1|USB2_OTG_OC
|-
|J1.170ALT4|USDHC3_WP||||I/O|||(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT4)
|-
|J1.172|||||I/O||ALT5|PWM4_OUT
|-
|J1.174|||||I/O||ALT6|CCM_CLKO2
|-
| rowspan="4" |J1.176168|rowspan="4" |GPIO1_IO07|rowspan="4" |CPU.GPIO1_IO07|rowspan="4" |AF11|rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO07
|-
|J1.178ALT1|ENET1_MDIO||||I/O|||(Configure register IOMUXC_ENET1_MDIO_SELECT_INPUT for mode ALT1)
|-
|J1.180|||||I/O||ALT5|USDHC1_WP
|-
|J1.182|||||I/O||ALT6|CCM_EXT_CLK4
|-
| rowspan="6" |J1.170| rowspan="6" |SAI1_TXD4| rowspan="6" |CPU.SAI1_TXD4| rowspan="6" |AG22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA4|-|ALT1|SAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_BCLK(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE12|-|ALT5|GPIO4_IO16|-|ALT6|SRC_BOOT_CFG12|-| rowspan="6" |J1.172| rowspan="6" |SAI1_TXD5| rowspan="6" |CPU.SAI1_TXD5| rowspan="6" |AF22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA5|-|ALT1|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT1)|-|ALT2|SAI6_TX_DATA0|-|ALT4|CORESIGHT_TRACE13|-|ALT5|GPIO4_IO17|-|ALT6|SRC_BOOT_CFG13|-| rowspan="6" |J1.174| rowspan="6" |SAI1_TXD6| rowspan="6" |CPU.SAI1_TXD6| rowspan="6" |AG23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA6|-|ALT1|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE14|-|ALT5|GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14|-| rowspan="6" |J1.176| rowspan="6" |SAI1_TXD7| rowspan="6" |CPU.SAI1_TXD7| rowspan="6" |AF23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT3|PDM_CLK|-|ALT4|CORESIGHT_TRACE15|-|ALT5|GPIO4_IO19|-|ALT6|SRC_BOOT_CFG15|-| rowspan="7" |J1.178| rowspan="7" |SAI1_RXD7| rowspan="7" |CPU.SAI1_RXD7| rowspan="7" |AF19| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI1_TX_DATA4|-|ALT4|CORESIGHT_TRACE7|-|ALT5|GPIO4_IO09|-|ALT6|SRC_BOOT_CFG7|-| rowspan="6" |J1.180| rowspan="6" |SAI1_RXD6| rowspan="6" |CPU.SAI1_RXD6| rowspan="6" |AG19| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA6|-|ALT1|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE6|-|ALT5|GPIO4_IO08|-|ALT6|SRC_BOOT_CFG6|-| rowspan="7" |J1.182| rowspan="7" |SAI1_RXD5| rowspan="7" |CPU.SAI1_RXD5| rowspan="7" |AF18| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA5|-|ALT1|SAI6_TX_DATA0|-|ALT2|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT2)|-|ALT3|SAI1_RX_SYNC(Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT3)|-|ALT4|CORESIGHT_TRACE5|-|ALT5|GPIO4_IO07|-|ALT6|SRC_BOOT_CFG|-| rowspan="6" |J1.184|rowspan="6" |SAI1_RXD4|rowspan="6" |CPU.SAI1_RXD4|rowspan="6" |AG18|rowspan="6" |NVCC_3V3| rowspan="6" |I/O|rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA4|-|ALT1|SAI1_RX_DATA4(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE4|-|ALT5|GPIO4_IO06|-|ALT6|SRC_BOOT_CFG4|-|J1.186|USB1_VBUS|CPU.USB1_VBUS|F22||S|Connected with 30K resistoron SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.188|USB2_VBUS|CPU.USB2_VBUS|F23||S|Connected with 30K resistoron SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.190|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J1.192|USB1_ID
|CPU.USB1_ID
|D22
|-
|}
'''(*)''' PMIC_PWRON can be used in two configuration: ''Embedded-like'' (default mounting option) or ''Tablet-like''. In the first case, the system reboots in case of PMIC_PWR_ON signal activity.
 
In the second case, the system will shut down waiting for a CPU_ONOFF signal raising (like a button-mode in a tablet) and the PMIC_PWRON Voltage domain is NVCC_SNVS_1V8
Please contact [mailto:sales@dave.eu sales dept.] for more information
----
[[Category:MITO 8M Mini]]
[[Category:MITO 8M Nano]]
U0007
Bureaucrats, dave_user, Administrators
8,221
edits
Retrieved from "https://wiki.dave.eu/index.php/Special:MobileDiff/12669...19005"