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MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table

8,592 bytes added, 18:06, 27 December 2023
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=== Connectors description ===
In the following table are described all available connectors integrated on MITO 8M Mini/Nano SOM:
{| class="wikitable"
|-
|-
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini/Nano pinout specifications. See the images below for reference:
[[File:MITO_8M_Mini_MITO8M_Mini-_TOPconn-top.jpegpng|500px|thumb|MITO 8M Mini/Nano TOP view|none]][[File:MITO_8M_Mini_MITO8M_Mini-conn-_BOTTOMbottom.jpegpng|500px|thumb|MITO 8M Mini/Nano BOTTOM view|none]]
Below a detailed description of the pinout, grouped in the following tables:
|-
|'''Pin Name'''
| Pin (signal) name on the MITO 8M Mini connectors
|-
|'''Internal<br>connections'''
| Connections to the components
* CPU.<x> : pin connected to CPU pad named <x>(NXP iMX8MM)* PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210PF8121)
* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
| rowspan="5" | NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
|SAI1_TX_DATA3
|-
|
|ALT1
|SAI5_TX_DATA3
|-
|
|ALT4
|CORESIGHT_TRACE11
|-
|
|ALT5
|GPIO4_IO15
|-
|
|ALT6
|SRC_BOOT_CFG11
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.133
|DSI_CLK_N
|CPU.MIPI_DSI_CLK_N
|A11
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.135
|DSI_CLK_P
|CPU.MIPI_
|B11
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.137
|DSI_D0_N
|CPU.MIPI_DSI_D0_N
|A9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.139
|DSI_D0_P
|CPU.MIPI_DSI_D0_P
|B9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.141
|DSI_D1_N
|CPU.MIPI_DSI_D1_N
|A10
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.143
|DSI_D1_P
|CPU.MIPI_DSI_D1_P
|B10
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.145|DSI_D2_N|CPU.MIPI_DSI_D2_N|A12| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.147
|LVDS0_TX2_P
|BRIDGE.A_Y2P
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.147
|DSI_D2_P
|CPU.MIPI_DSI_D2_P
|B12
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.149
|DSI_D3_N
|CPU.MIPI_DSI_D3_N
|A13
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.151
|DSI_D3_P
|CPU.MIPI_DSI_D3_P
|B13
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for PMIC interrupt, do not connect Pulled-up to NVCC_3V3
|ALT0
|GPIO1_IO03
|PMIC.PWRON
| 22
| -'''(*)''' 3.3VIN
|I
|internal pull-up 100k to VIN
'''(*)''' default as ''Embedded'' power mode
|
|
|-
|J1.84
|CLK2_NPCIE1_REF_CLKN|CPU.CLK2_NPCIE_REF_CLK_N|A21
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|-
|J1.86
|CLK2_PPCIE1_REF_CLKP|CPU.CLK2_PPCIE_REF_CLK_P|B21
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|-
|J1.88
|PCIE1_REF_CLKNCLKIN1|CPU.PCIE1_REF_PAD_CLK_NCLKIN1|H27|VDD_PHY_3V3NVCC_3V3|DI
|
|
|-
|J1.90
|PCIE1_REF_CLKPCLKIN2|CPU.PCIE1_REF_PAD_CLK_PCLKIN2|J27|VDD_PHY_3V3NVCC_3V3|DI
|
|
|J1.92
|PCIE1_RXN
|CPU.PCIE1_RXN_NPCIE_RXN_N|A19|VDD_PHY_3V3VDDA_1V8
|D
|
|J1.94
|PCIE1_RXP
|CPU.PCIE1_RXN_PPCIE_RXN_P|B19|VDD_PHY_3V3VDDA_1V8
|D
|
|J1.96
|PCIE1_TXN
|CPU.PCIE1_TXN_NPCIE_TXN_N|A20|VDD_PHY_3V3VDDA_1V8
|D
|
|J1.98
|PCIE1_TXP
|CPU.PCIE1_TXN_PPCIE_TXN_P|B20|VDD_PHY_3V3VDDA_1V8
|D
|
|-
|J1.102
|CSI1_CLK_NCSI_P1_CKN|CPU.MIPI_CSI1_CLK_NMIPI_CSI_CLK_N|A16
| -
|D
|-
|J1.104
|CSI1_CLK_PCSI_P1_CKP|CPU.MIPI_CSI1_CLK_PMIPI_CSI_CLK_P|B16
| -
|D
|-
|J1.106
|CSI1_D0_NCSI_P1_DN0|CPU.MIPI_CSI1_D0_NMIPI_CSI_D0_N|A14
| -
|D
|-
|J1.108
|CSI1_D0_PCSI_P1_DP0|CPU.MIPI_CSI1_D0_PMIPI_CSI_D0_P|B14
| -
|D
|-
|J1.110
|CSI1_D1_NCSI_P1_DN1|CPU.MIPI_CSI1_D1_NMIPI_CSI_D1_N|A15
| -
|D
|-
|J1.112
|CSI1_D1_PCSI_P1_DP1|CPU.MIPI_CSI1_D1_PMIPI_CSI_D1_P|B15
| -
|D
|-
|J1.114
|CSI1_D2_NCSI_P1_DN2|CPU.MIPI_CSI1_D2_NMIPI_CSI_D2_N|A17
| -
|D
|-
|J1.116
|CSI1_D2_PCSI_P1_DP2|CPU.MIPI_CSI1_D2_PMIPI_CSI_D2_P|B17
| -
|D
|-
|J1.118
|CSI1_D3_NCSI_P1_DN3|CPU.MIPI_CSI1_D3_NMIPI_CSI_D3_N|A18
| -
|D
|-
|J1.120
|CSI1_D3_PCSI_P1_DP3|CPU.MIPI_CSI1_D3_PMIPI_CSI_D3_P|B18
| -
|D
|NAND_DQS
|CPU.NAND_DQS
|R22
|NVCC_3V3
|I/O
| rowspan="3" |NAND_DQS
| rowspan="3" |CPU.NAND_DQS
| rowspan="3" |R22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|NAND_ALE
|CPU.NAND_ALE
|N22
|NVCC_3V3
|I/O
| rowspan="3" |NAND_ALE
| rowspan="3" |CPU.NAND_ALE
| rowspan="3" |N22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_CLK
| rowspan="2" |CPU.SD1_CLK
| rowspan="2" |V26
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_CE0_B
| rowspan="3" |CPU.NAND_CE0_B
| rowspan="3" |N24
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_CMD
| rowspan="2" |CPU.SD1_CMD
| rowspan="2" |V27
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
|GPIO2_IO01
|-
| rowspan="34" |J1.130
(eMMC on board)
| rowspan="34" |NAND_CE1_B| rowspan="34" |CPU.NAND_CE1_B| rowspan="34" |P27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_CE1_B
|ALT1
|QSPI_A_SS1_B
|-
|ALT2
|USDHC3_STROBE
|-
|ALT5
| rowspan="2" |SD1_RST_B
| rowspan="2" |CPU.SD1_RST_B
| rowspan="2" |R23
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
|GPIO2_IO10
|-
| rowspan="34" |J1.132
(eMMC on board)
| rowspan="34" |NAND_CE2_B| rowspan="34" |CPU.NAND_CE2_B| rowspan="34" |M27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_CE2_B
|ALT1
|QSPI_B_SS0_B
|-
|ALT2
|USDHC3_DATA5
|-
|ALT5
| rowspan="2" |SD1_STROBE
| rowspan="2" |CPU.SD1_STROBE
| rowspan="2" |R24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
|GPIO2_IO11
|-
| rowspan="34" |J1.134
(eMMC on board)
| rowspan="34" |NAND_CE3_B| rowspan="34" |CPU.NAND_CE3_B| rowspan="34" |L27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_CE3_B
|ALT1
|QSPI_B_SS1_B
|-
|ALT2
|USDHC3_DATA6
|-
|ALT5
|NAND_CLE
|CPU.NAND_CLE
|K27
|NVCC_3V3
|I/O
|
|-
| rowspan="34" |J1.136
(eMMC on board)
| rowspan="34" |NAND_CLE| rowspan="34" |CPU.NAND_CLE| rowspan="34" |K27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_CLE
|ALT1
|QSPI_B_SCLK
|-
|ALT2
|USDHC3_DATA7
|-
|ALT5
| rowspan="2" |SD1_DATA0
| rowspan="2" |CPU.SD1_DATA0
| rowspan="2" |Y27
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_DATA00
| rowspan="3" |CPU.NAND_DATA00
| rowspan="3" |P23
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_DATA1
| rowspan="2" |CPU.SD1_DATA1
| rowspan="2" |Y26
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_DATA01
| rowspan="3" |CPU.NAND_DATA01
| rowspan="3" |K24
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_DATA2
| rowspan="2" |CPU.SD1_DATA2
| rowspan="2" |T27
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
|GPIO2_IO04
|-
| rowspan="34" |J1.142
(eMMC on board)
| rowspan="34" |NAND_DATA02| rowspan="34" |CPU.NAND_DATA02| rowspan="34" |K23| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA02
|ALT1
|QSPI_A_DATA2
|-
|ALT2
|USDHC3_CD_B
(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
| rowspan="2" |SD1_DATA3
| rowspan="2" |CPU.SD1_DATA3
| rowspan="2" |T26
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
|GPIO2_IO05
|-
| rowspan="34" |J1.144
(eMMC on board)
| rowspan="34" |NAND_DATA03| rowspan="34" |CPU.NAND_DATA03| rowspan="34" |N23| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA03
|ALT1
|QSPI_A_DATA3
|-
|ALT2
|USDHC3_WP
(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)
|-
|ALT5
| rowspan="2" |SD1_DATA4
| rowspan="2" |CPU.SD1_DATA4
| rowspan="2" |U27
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
|GPIO2_IO06
|-
| rowspan="34" |J1.148
(eMMC on board)
| rowspan="34" |NAND_DATA04| rowspan="34" |CPU.NAND_DATA04| rowspan="34" |M26| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA04
|ALT1
|QSPI_B_DATA0
|-
|ALT2
|USDHC3_DATA0
|-
|ALT5
| rowspan="2" |SD1_DATA5
| rowspan="2" |CPU.SD1_DATA5
| rowspan="2" |U26
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
|GPIO2_IO07
|-
| rowspan="34" |J1.150
(eMMC on board)
| rowspan="34" |NAND_DATA05| rowspan="34" |CPU.NAND_DATA05| rowspan="34" |L26| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA05
|ALT1
|QSPI_B_DATA1
|-
|ALT2
|USDHC3_DATA1
|-
|ALT5
| rowspan="2" |SD1_DATA6
| rowspan="2" |CPU.SD1_DATA6
| rowspan="2" |W27
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
|GPIO2_IO08
|-
| rowspan="34" |J1.152
(eMMC on board)
| rowspan="34" |NAND_DATA06| rowspan="34" |CPU.NAND_DATA06| rowspan="34" |K26| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA06
|ALT1
|QSPI_B_DATA2
|-
|ALT2
|USDHC3_DATA2
|-
|ALT5
| rowspan="2" |SD1_DATA7
| rowspan="2" |CPU.SD1_DATA7
| rowspan="2" |W26
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
|GPIO2_IO09
|-
| rowspan="34" |J1.154
(eMMC on board)
| rowspan="34" |NAND_DATA07| rowspan="34" |CPU.NAND_DATA07| rowspan="34" |N26| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA07
|ALT1
|QSPI_B_DATA3
|-
|ALT2
|USDHC3_DATA3
|-
|ALT5
|NAND_RE_B
|CPU.NAND_RE_B
|N27
|NVCC_3V3
|I/O
|
|-
| rowspan="34" |J1.156
(eMMC on board)
| rowspan="34" |NAND_RE_B| rowspan="34" |CPU.NAND_RE_B| rowspan="34" |N27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_RE_B
|ALT1
|QSPI_B_DQS
|-
|ALT2
|USDHC3_DATA4
|-
|ALT5
|NAND_READY_B
|CPU.NAND_READY_B
|P26
|NVCC_3V3
|I/O
|
|-
| rowspan="23" |J1.158
(eMMC on board)
| rowspan="23" |NAND_READY_B| rowspan="23" |CPU.NAND_READY_B| rowspan="23" |P26| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |
|ALT0
|RAWNAND_READY_B
|-
|ALT2
|USDHC3_RESET_B
|-
|ALT5
|NAND_WE_B
|CPU.NAND_WE_B
|R26
|NVCC_3V3
|I/O
|
|-
| rowspan="23" |J1.160
(eMMC on board)
| rowspan="23" |NAND_WE_B| rowspan="23" |CPU.NAND_WE_B| rowspan="23" |R26| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |
|ALT0
|RAWNAND_WE_B
|-
|ALT2
|USDHC3_CLK
|-
|ALT5
|NAND_WP_B
|CPU.NAND_WP_B
|R27
|NVCC_3V3
|I/O
|
|-
| rowspan="23" |J1.162
(eMMC on board)
| rowspan="23" |NAND_WP_B| rowspan="23" |CPU.NAND_WP_B| rowspan="23" |R27| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |
|ALT0
|RAWNAND_WP_B
|-
|ALT2
|USDHC3_CMD
|-
|ALT5
|
|-
| rowspan="5" |J1.166|rowspan="5" |GPIO1_IO15|rowspan="5" |CPU.GPIO1_IO15|rowspan="5" |AB9|rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|GPIO1_IO15
|-
|J1.168|||||I/O||ALT1|USB2_OTG_OC
|-
|J1.170ALT4|USDHC3_WP||||I/O|||(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT4)
|-
|J1.172|||||I/O||ALT5|PWM4_OUT
|-
|J1.174|||||I/O||ALT6|CCM_CLKO2
|-
| rowspan="4" |J1.176168|rowspan="4" |GPIO1_IO07|rowspan="4" |CPU.GPIO1_IO07|rowspan="4" |AF11|rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO07
|-
|J1.178ALT1|ENET1_MDIO||||I/O|||(Configure register IOMUXC_ENET1_MDIO_SELECT_INPUT for mode ALT1)
|-
|J1.180|||||I/O||ALT5|USDHC1_WP
|-
|J1.182|||||I/O||ALT6|CCM_EXT_CLK4
|-
| rowspan="6" |J1.170| rowspan="6" |SAI1_TXD4| rowspan="6" |CPU.SAI1_TXD4| rowspan="6" |AG22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA4|-|ALT1|SAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_BCLK(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE12|-|ALT5|GPIO4_IO16|-|ALT6|SRC_BOOT_CFG12|-| rowspan="6" |J1.172| rowspan="6" |SAI1_TXD5| rowspan="6" |CPU.SAI1_TXD5| rowspan="6" |AF22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA5|-|ALT1|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT1)|-|ALT2|SAI6_TX_DATA0|-|ALT4|CORESIGHT_TRACE13|-|ALT5|GPIO4_IO17|-|ALT6|SRC_BOOT_CFG13|-| rowspan="6" |J1.174| rowspan="6" |SAI1_TXD6| rowspan="6" |CPU.SAI1_TXD6| rowspan="6" |AG23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA6|-|ALT1|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE14|-|ALT5|GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14|-| rowspan="6" |J1.176| rowspan="6" |SAI1_TXD7| rowspan="6" |CPU.SAI1_TXD7| rowspan="6" |AF23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT3|PDM_CLK|-|ALT4|CORESIGHT_TRACE15|-|ALT5|GPIO4_IO19|-|ALT6|SRC_BOOT_CFG15|-| rowspan="7" |J1.178| rowspan="7" |SAI1_RXD7| rowspan="7" |CPU.SAI1_RXD7| rowspan="7" |AF19| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI1_TX_DATA4|-|ALT4|CORESIGHT_TRACE7|-|ALT5|GPIO4_IO09|-|ALT6|SRC_BOOT_CFG7|-| rowspan="6" |J1.180| rowspan="6" |SAI1_RXD6| rowspan="6" |CPU.SAI1_RXD6| rowspan="6" |AG19| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA6|-|ALT1|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE6|-|ALT5|GPIO4_IO08|-|ALT6|SRC_BOOT_CFG6|-| rowspan="7" |J1.182| rowspan="7" |SAI1_RXD5| rowspan="7" |CPU.SAI1_RXD5| rowspan="7" |AF18| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA5|-|ALT1|SAI6_TX_DATA0|-|ALT2|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT2)|-|ALT3|SAI1_RX_SYNC(Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT3)|-|ALT4|CORESIGHT_TRACE5|-|ALT5|GPIO4_IO07|-|ALT6|SRC_BOOT_CFG|-| rowspan="6" |J1.184|rowspan="6" |SAI1_RXD4|rowspan="6" |CPU.SAI1_RXD4|rowspan="6" |AG18|rowspan="6" |NVCC_3V3| rowspan="6" |I/O|rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA4|-|ALT1|SAI1_RX_DATA4(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE4|-|ALT5|GPIO4_IO06|-|ALT6|SRC_BOOT_CFG4|-|J1.186|USB1_VBUS|CPU.USB1_VBUS|F22||S|Connected with 30K resistoron SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.188|USB2_VBUS|CPU.USB2_VBUS|F23||S|Connected with 30K resistoron SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.190|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J1.192|USB1_ID
|CPU.USB1_ID
|D22
|-
|}
'''(*)''' PMIC_PWRON can be used in two configuration: ''Embedded-like'' (default mounting option) or ''Tablet-like''. In the first case, the system reboots in case of PMIC_PWR_ON signal activity.
 
In the second case, the system will shut down waiting for a CPU_ONOFF signal raising (like a button-mode in a tablet) and the PMIC_PWRON Voltage domain is NVCC_SNVS_1V8
Please contact [mailto:sales@dave.eu sales dept.] for more information
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[[Category:MITO 8M Mini]]
[[Category:MITO 8M Nano]]
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