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MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table

13,597 bytes added, 18:06, 27 December 2023
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=== Connectors description ===
In the following table are described all available connectors integrated on MITO 8M Mini/Nano SOM:
{| class="wikitable"
|-
|-
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini/Nano pinout specifications. See the images below for reference:
[[File:MITO_8M_Mini_MITO8M_Mini-_TOPconn-top.jpegpng|500px|thumb|MITO 8M Mini/Nano TOP view|none]][[File:MITO_8M_Mini_MITO8M_Mini-conn-_BOTTOMbottom.jpegpng|500px|thumb|MITO 8M Mini/Nano BOTTOM view|none]]
Below a detailed description of the pinout, grouped in the following tables:
|-
|'''Pin Name'''
| Pin (signal) name on the MITO 8M Mini connectors
|-
|'''Internal<br>connections'''
| Connections to the components
* CPU.<x> : pin connected to CPU pad named <x>(NXP iMX8MM)* PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210PF8121)
* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
| rowspan="5" | NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
|SAI1_TX_DATA3
|-
|
|ALT1
|SAI5_TX_DATA3
|-
|
|ALT4
|CORESIGHT_TRACE11
|-
|
|ALT5
|GPIO4_IO15
|-
|
|ALT6
|SRC_BOOT_CFG11
|
|-
| rowspan="4" |J1.111| rowspan="4" |SAI1_TXFS| rowspan="4" |CPU.SAI1_TXFS|rowspan="4" |AB19| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_TX_SYNC (Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT0)
|-
|J1.113ALT1|SAI1_TXCSAI5_TX_SYNC|CPU.SAI1_TXC||NVCC_3V3|I/O|||(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
|-
|J1.115|SAI1_TXD0|CPU.SAI1_TXD0||NVCC_3V3|I/O|Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT4|CORESIGHT_EVENTO
|-
|ALT5|GPIO4_IO10|-| rowspan="4" |J1.117113|SAI1_TXD1rowspan="4" |SAI1_TXC| rowspan="4" |CPU.SAI1_TXD1SAI1_TXC|rowspan="4" |AC18| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|Internally used for BOOT mode configuration:rowspan="4" ||ALT0|SAI1_TX_BCLK
can be pulled(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)|-up or down depending on|ALT4[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]CORESIGHT_EVENTI|-|ALT5|GPIO4_IO11
|-
| rowspan="5" |J1.119115|SAI1_TXD2rowspan="5" |SAI1_TXD0| rowspan="5" |CPU.SAI1_TXD2SAI1_TXD0|rowspan="5" |AG20| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0|SAI1_TX_DATA0|-|ALT1|SAI5_TX_DATA0
|-
|J1.121ALT4|SAI1_RXFS|CPU.SAI1_RXFS||NVCC_3V3|I/OCORESIGHT_TRACE8|-|ALT5|GPIO4_IO12
|-
|J1.123|SAI1_RXC|CPU.SAI1_RXC||NVCC_3V3|I/O||ALT6|SRC_BOOT_CFG8
|-
| rowspan="5" |J1.125117|SAI1_RXD0rowspan="5" |SAI1_TXD1| rowspan="5" |CPU.SAI1_RXD0SAI1_TXD1|rowspan="5" |AF20| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0|SAI1_TX_DATA1
|-
|J1.127|SAI1_RXD1|CPU.SAI1_RXD1||NVCC_3V3|I/O|Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT1|SAI5_TX_DATA1
|-
|ALT4|CORESIGHT_TRACE9|-|ALT5|GPIO4_IO13|-|ALT6|SRC_BOOT_CFG9|-| rowspan="5" |J1.129119|SAI1_RXD2rowspan="5" |SAI1_TXD2| rowspan="5" |CPU.SAI1_RXD2SAI1_TXD2|rowspan="5" |AG21| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0|SAI1_TX_DATA2
|-
|J1.131|DGND |DGND| -| -|G||ALT1|SAI5_TX_DATA2
|-
|J1.133|LVDS0_CLK_N|BRIDGE.A_CLKN|F9| -|D||ALT4|CORESIGHT_TRACE10
|-
|J1.135|LVDS0_CLK_P|BRIDGE.A_CLKP|F8| -|D||ALT5|GPIO4_IO14
|-
|J1.137|LVDS0_TX0_N|BRIDGE.A_Y0N|C9| -|D||ALT6|SRC_BOOT_CFG10
|-
| rowspan="4" |J1.139121|LVDS0_TX0_Prowspan="4" |SAI1_RXFS|BRIDGErowspan="4" |CPU.A_Y0PSAI1_RXFS|C8rowspan="4" |AG16| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_SYNC (Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT0)
|-
|J1.141ALT1|LVDS0_TX1_NSAI5_RX_SYNC|BRIDGE.A_Y1N|D9(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT1)| -|D||ALT4|CORESIGHT_TRACE_CLK
|-
|J1.143|LVDS0_TX1_P|BRIDGE.A_Y1P|D8| -|D||ALT5|GPIO4_IO00
|-
| rowspan="4" |J1.145123|LVDS0_TX2_Nrowspan="4" |SAI1_RXC|BRIDGErowspan="4" |CPU.A_Y2NSAI1_RXC|E9rowspan="4" |AF16| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_BCLK
|-
|J1.147ALT1|LVDS0_TX2_PSAI5_RX_BCLK|BRIDGE.A_Y2P|E8| -|D|||(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT1)
|-
|J1.149|LVDS0_TX3_N|BRIDGE.A_Y3N|G9| -|D||ALT4|CORESIGHT_TRACE_CTL
|-
|J1.151|LVDS0_TX3_P|BRIDGE.A_Y3P|G8| -|D||ALT5|GPIO4_IO01
|-
| rowspan="7" |J1.153125| rowspan="7" |SAI1_RXD0| rowspan="7" |CPU.SAI1_RXD0|DGND rowspan="7" |AG15|DGNDrowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA0| -|GALT1|SAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT1)|-|ALT2|SAI1_TX_DATA1
|-
|J1.155ALT3|LVDS1_CLK_NPDM_BIT_STREAM0|BRIDGE.B_CLKN|A6| -|D|||(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT3)
|-
|J1.157|LVDS1_CLK_P|BRIDGE.B_CLKP|B6| -|D||ALT4|CORESIGHT_TRACE0
|-
|J1.159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D||ALT5|GPIO4_IO02
|-
|J1.161|LVDS1_TX0_P|BRIDGE.B_Y0P|B3| -|D||ALT6|SRC_BOOT_CFG0
|-
| rowspan="6" |J1.163127|LVDS1_TX1_Nrowspan="6" |SAI1_RXD1|BRIDGErowspan="6" |CPU.B_Y1NSAI1_RXD1| rowspan="6" |AF15| rowspan="6" |NVCC_3V3|A4rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on|D[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA1
|-
|J1.165ALT1|LVDS1_TX1_PSAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT1)|BRIDGE.B_Y1P-|B4ALT3| -PDM_BIT_STREAM1|D(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT3)|-|ALT4|CORESIGHT_TRACE1
|-
|J1.167|LVDS1_TX2_N|BRIDGE.B_Y2N|A5| -|D||ALT5|GPIO4_IO03
|-
|J1.169|LVDS1_TX2_P|BRIDGE.B_Y2P|B5| -|D||ALT6|SRC_BOOT_CFG1
|-
| rowspan="6" |J1.171129|LVDS1_TX3_Nrowspan="6" |SAI1_RXD2|BRIDGErowspan="6" |CPU.B_Y3NSAI1_RXD2| rowspan="6" |AG17| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|A7SAI1_RX_DATA2| -|DALT1|SAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT1)|-|ALT3|PDM_BIT_STREAM2(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT3)|-|ALT4|CORESIGHT_TRACE2|-|ALT5|GPIO4_IO04
|-
|J1.173|LVDS1_TX3_P|BRIDGE.B_Y3P|B7| -|D||ALT6|SRC_BOOT_CFG2
|-
|J1.175131
|DGND
|DGND
|
|-
| rowspan="2" |J1.177133| rowspan="2" |SD2_CD_BLVDS0_CLK_N| rowspan="2" |CPUBRIDGE.SD2_CD_BA_CLKN| rowspan="2" F9|-| rowspan="2" |NVCC_3V3D| rowspan="2" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="2" |N composition]]|ALT0|USDHC2_CD_B
|-
|ALT5J1.133|DSI_CLK_N|CPU.MIPI_DSI_CLK_N|A11| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO2_IO12
|-
| rowspan="3" |J1.179135| rowspan="3" |ECSPI1_SS0LVDS0_CLK_P| rowspan="3" |CPUBRIDGE.ECSPI1_SS0A_CLKP| rowspan="3" F8|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|ECSPI1_SS0
|-
|ALT1J1.135|DSI_CLK_P|CPU.MIPI_|B11| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||UART3_RTS_B
|-
|ALT5J1.137|LVDS0_TX0_N|BRIDGE.A_Y0N|C9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO09
|-
| rowspan="3" |J1.181137| rowspan="3" |ECSPI1_SCLKDSI_D0_N| rowspan="3" |CPU.ECSPI1_SCLKMIPI_DSI_D0_N| rowspan="3" A9|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|ECSPI1_SCLK
|-
|ALT1J1.139|LVDS0_TX0_P|BRIDGE.A_Y0P|C8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||UART3_RX
|-
|ALT5J1.139|DSI_D0_P|CPU.MIPI_DSI_D0_P|B9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO06
|-
| rowspan="3" |J1.183141| rowspan="3" |ECSPI1_MISOLVDS0_TX1_N| rowspan="3" |CPUBRIDGE.ECSPI1_MISOA_Y1N| rowspan="3" D9|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|ECSPI1_MISO
|-
|ALT1J1.141|DSI_D1_N|CPU.MIPI_DSI_D1_N|A10| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||UART3_CTS_B
|-
|ALT5J1.143|LVDS0_TX1_P|BRIDGE.A_Y1P|D8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO08
|-
| rowspan="3" |J1.185143| rowspan="3" |GPIO1_IO03DSI_D1_P| rowspan="3" |CPU.GPIO1_IO03MIPI_DSI_D1_P| rowspan="3" B10|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|GPIO1_IO03
|-
|ALT1J1.145|LVDS0_TX2_N|BRIDGE.A_Y2N|E9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||USDHC1_VSELECT
|-
|ALT5J1.145|DSI_D2_N|CPU.MIPI_DSI_D2_N|A12| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||SDMA1_EXT_EVENT0
|-
| rowspan="3" |J1.187147| rowspan="3" |UART2_TXDLVDS0_TX2_P| rowspan="3" |CPUBRIDGE.UART2_TXDA_Y2P| rowspan="3" E8|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |used as default Linux consoleN composition]]|ALT0|UART2_TX
|-
|ALT1J1.147|DSI_D2_P|CPU.MIPI_DSI_D2_P|B12| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_SS0
|-
|ALT5J1.149|LVDS0_TX3_N|BRIDGE.A_Y3N|G9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO25
|-
| rowspan="3" |J1.189149| rowspan="3" |UART2_RXDDSI_D3_N| rowspan="3" |CPU.UART2_RXDMIPI_DSI_D3_N| rowspan="3" A13|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |used as default Linux consoleN composition]]|ALT0|UART2_RXD
|-
|ALT1J1.151|ECSPI3_MISOLVDS0_TX3_P|BRIDGE.A_Y3P|G8|-|ALT5D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO24
|-
| rowspan="3" |J1.191151| rowspan="3" |UART1_TXDDSI_D3_P| rowspan="3" |CPU.UART1_TXDMIPI_DSI_D3_P| rowspan="3" B13|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|UART1_TX
|-
|ALT1J1.153|DGND |DGND| -| -|G|||ECSPI3_MOSI
|-
|ALT5J1.155|LVDS1_CLK_N|BRIDGE.B_CLKN|A6| -|D|||GPIO5_IO23
|-
| rowspan="3" |J1.193157| rowspan="3" |UART1_RXDLVDS1_CLK_P| rowspan="3" |CPUBRIDGE.UART1_RXDB_CLKP| rowspan="3" |B6| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|UART1_RXD
|-
|ALT1J1.159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D|||ECSPI3_SCLK
|-
|ALT5J1.161|LVDS1_TX0_P|BRIDGE.B_Y0P|B3| -|D|||GPIO5_IO22
|-
| rowspan="3" |J1.195163| rowspan="3" |ECSPI1_MOSILVDS1_TX1_N| rowspan="3" |CPUBRIDGE.ECSPI1_MOSIB_Y1N| rowspan="3" |A4| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|ECSPI1_MOSI
|-
|ALT1J1.165|UART3_TXLVDS1_TX1_P|BRIDGE.B_Y1P|B4|-|ALT5D|||GPIO5_IO07
|-
| rowspan="4" |J1.197167| rowspan="4" |GPIO1_IO14LVDS1_TX2_N| rowspan="4" |CPUBRIDGE.GPIO1_IO14B_Y2N| rowspan="4" |A5| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OD| rowspan="4" ||ALT0|GPIO1_IO14
|-
|ALT1J1.169|LVDS1_TX2_P|BRIDGE.B_Y2P|B5| -|D|||USB2_OTG_PWR
|-
|ALT5J1.171|PWM3_OUTLVDS1_TX3_N|BRIDGE.B_Y3N|A7|-|ALT6D|||CCM_CLKO1
|-
| rowspan="3" |J1.199173| rowspan="3" |GPIO1_IO04LVDS1_TX3_P| rowspan="3" |CPUBRIDGE.GPIO1_IO04B_Y3P| rowspan="3" |B7| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|GPIO1_IO04
|-
|ALT1J1.175|USDHC2_VSELECTDGND |DGND| -|-|ALT5G||||-| rowspan="2" |J1.177| rowspan="2" |SD2_CD_B| rowspan="2" |CPU.SD2_CD_B| rowspan="2" |AA26| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|SDMA1_EXT_EVENT1USDHC2_CD_B
|-
|ALT5|GPIO2_IO12|-| rowspan="3" |J1.201179| rowspan="3" |GPIO1_IO12ECSPI1_SS0| rowspan="3" |CPU.GPIO1_IO12ECSPI1_SS0| rowspan="3" |B6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|GPIO1_IO12ECSPI1_SS0
|-
|ALT1
|USB1_OTG_PWRUART3_RTS_B(Configure register IOMUXC_UART3_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|SDMA2_EXT_EVENT1GPIO5_IO09
|-
| rowspan="3" |J1.203181|DGND rowspan="3" |ECSPI1_SCLK|DGNDrowspan="3" |CPU.ECSPI1_SCLK| -rowspan="3" |D6| -rowspan="3" |NVCC_3V3|Growspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_SCLK
|-
|}ALT1 ==SODIMM J1 EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" | Alternative FunctionsUART3_RX
|-
|J1.2|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO5_IO06
|-
| rowspan="3" |J1.4183| rowspan="3" |ECSPI1_MISO|rowspan="3" |CPU.3VIN ECSPI1_MISO|INPUT VOLTAGErowspan="3" |A7| -rowspan="3" |NVCC_3V3| rowspan="3" |I/O|rowspan="3.3VIN" ||ALT0|SECSPI1_MISO|-|ALT1|UART3_CTS_B
|-
|J1.6|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S||ALT5|GPIO5_IO08
|-
| rowspan="3" |J1.8185| rowspan="3" |GPIO1_IO03|rowspan="3" |CPU.3VIN GPIO1_IO03|INPUT VOLTAGErowspan="3" |AF13| -rowspan="3" |NVCC_3V3|rowspan="3.3VIN" |I/O|Srowspan="3" |Internally used for PMIC interrupt, do not connect |Pulled-up to NVCC_3V3|ALT0|GPIO1_IO03
|-
|J1.10|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S||ALT1|USDHC1_VSELECT
|-
|J1.12|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|SDMA1_EXT_EVENT0
|-
| rowspan="3" |J1.14187|PMIC_LICELL rowspan="3" |UART2_TXD|PMICrowspan="3" |CPU.LICELLUART2_TXD|30rowspan="3" |E15| -rowspan="3" |NVCC_3V3|Srowspan="3" |I/O|rowspan="3" |used as default Linux console|ALT0|UART2_TX
|-
|J1.16|CPU_ONOFF|CPU.ONOFF|W21|NVCC_SNVS|I|internal pull-up 100k to NVCC_SNVS|ALT1|ECSPI3_SS0
|-
|J1.18|BOARD_PGOOD| -| -|NVCC_3V3|O||ALT5|GPIO5_IO25
|-
|J1.20|BOOT_MODE_SEL|BOOT MODE SELECTION| -|NVCC_3V3|I|internal pull-up to NVCC_3V3|||-|J1.22|CPU_PORn|CPU.POR_BPMIC.RESETMCU|W203|NVCC_SNVS|I/O|internal pull-up 100k to NVCC_SNVS|||-|J1.24|EXT_RESET|MASTER RESET| -| -|I|internal pull-up to NVCC_SNVS|||-| rowspan="43" |J1.26189| rowspan="43" |SAI3_RXCUART2_RXD| rowspan="43" |CPU.SAI3_RXCUART2_RXD| rowspan="43" |F4F15| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |used as default Linux console
|ALT0
|SAI3_RX_BCLKUART2_RXD
|-
|ALT1
|GPT1_CAPTURE2ECSPI3_MISO
|-
|ALT2ALT5|SAI5_RX_BCLKGPIO5_IO24
|-
|ALT5|GPIO4_IO29|-| rowspan="43" |J1.28191| rowspan="43" |GPIO1_IO02UART4_TXD| rowspan="43" |CPU.GPIO1_IO02UART4_TXD| rowspan="43" |R4F18| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02UART4_TX
|-
|ALT1
|WDOG1_WDOG_BUART2_RTS_B(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|WDOG1_WDOG_ANY|-|ALT7|SJC_DE_B|-|J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO5_IO29
|-
| rowspan="4" |J1.32193| rowspan="4" |SAI3_RXDUART4_RXD| rowspan="4" |CPU.SAI3_RXDUART4_RXD| rowspan="4" |F3F19
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI3_RX_DATA0UART4_RX
|-
|ALT1
|GPT1_COMPARE1UART2_CTS_B
|-
|ALT2
|SAI5_RX_DATA0PCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO4_IO30GPIO5_IO28
|-
| rowspan="3" |J1.34195| rowspan="3" |SAI2_MCLKECSPI1_MOSI| rowspan="3" |CPU.SAI2_MCLKECSPI1_MOSI| rowspan="3" |H5B7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_MCLKECSPI1_MOSI
|-
|ALT1
|SAI5_MCLKUART3_TX
|-
|ALT5
|GPIO4_IO27GPIO5_IO07
|-
| rowspan="45" |J1.36197| rowspan="45" |SAI3_RXFSGPIO1_IO14| rowspan="45" |CPU.SAI3_RXFSGPIO1_IO14| rowspan="45" |G4AC9| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |
|ALT0
|SAI3_RX_SYNCGPIO1_IO14
|-
|ALT1
|GPT1_CAPTURE1USB2_OTG_PWR
|-
|ALT2ALT4|SAI5_RX_SYNCUSDHC3_CD_B(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|GPIO4_IO28PWM3_OUT|-|ALT6|CCM_CLKO1
|-
| rowspan="43" |J1.38199| rowspan="43" |I2C3_SCLGPIO1_IO04| rowspan="43" |CPU.I2C3_SCLGPIO1_IO04| rowspan="43" |G8AG12| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C3_SCLGPIO1_IO04
|-
|ALT1
|PWM4_OUT|-|ALT2|GPT2_CLKUSDHC2_VSELECT
|-
|ALT5
|GPIO5_IO18SDMA1_EXT_EVENT1
|-
| rowspan="43" |J1.40201| rowspan="43" |SAI3_TXFSGPIO1_IO12| rowspan="43" |CPU.SAI3_TXFSGPIO1_IO12| rowspan="43" |G3AB10| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_TX_SYNCGPIO1_IO12
|-
|ALT1
|GPT1_CLK|-|ALT2|SAI5_RX_DATA1USB1_OTG_PWR
|-
|ALT5
|GPIO4_IO31SDMA2_EXT_EVENT1
|-
| rowspan="3" |J1.42203| rowspan="3" |SPDIF_RXDGND | rowspan="3" |CPU.SPDIF_RXDGND| rowspan="3" |G6-| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OG| rowspan="3" ||ALT0|SPDIF1_IN
|-
|ALT1} ==SODIMM J1 EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" |PWM2_OUTAlternative Functions
|-
|ALT5J1.2|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO5_IO04
|-
| rowspan="3" |J1.444| rowspan="3" |SPDIF_TX.3VIN | rowspan="3" |CPU.SPDIF_TXINPUT VOLTAGE| rowspan="3" |F6-| rowspan="3" |NVCC_3V3.3VIN| rowspan="3" |I/OS| rowspan="3" ||ALT0|SPDIF1_OUT
|-
|ALT1J1.6|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||PWM3_OUT
|-
|ALT5J1.8|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||GPIO5_IO03
|-
| rowspan="4" |J1.4610| rowspan="4" |SAI3_MCLK3.3VIN | rowspan="4" |CPU.SAI3_MCLKINPUT VOLTAGE| rowspan="4" |D3-| rowspan="4" |NVCC_3V33.3VIN| rowspan="4" |I/OS| rowspan="4" ||ALT0|SAI3_MCLK
|-
|ALT1J1.12|PWM4_OUTDGND|DGND|-|ALT2<nowiki>-</nowiki>|G|||SAI5_MCLK
|-
|ALT5J1.14|PMIC_LICELL |PMIC.LICELL|46| -|S|||GPIO5_IO02
|-
| rowspan="4" |J1.4816| rowspan="4" |I2C3_SDACPU_ONOFF| rowspan="4" |CPU.I2C3_SDAONOFF| rowspan="4" |E9A25| rowspan="4" |NVCC_3V3NVCC_SNVS_1V8| rowspan="4" |I/O| rowspan="4" |internal pull-up 100k to NVCC_SNVS_1V8|ALT0|I2C3_SDA
|-
|ALT1J1.18|PWM3_OUTBOARD_PGOOD|-|ALT2-|NVCC_3V3|O|||GPT3_CLK
|-
|ALT5J1.20|BOOT_MODE_SEL|BOOT MODE SELECTION| -|NVCC_3V3|I|internal pull-up to NVCC_3V3||GPIO5_IO19
|-
| rowspan="4" |J1.5022| rowspan="4" |SAI3_TXCCPU_PORn| rowspan="4" |CPU.SAI3_TXCPOR_BPMIC.RESET_MCU| rowspan="4" |C4B2421| rowspan="4" |NVCC_3V3NVCC_SNVS_1V8| rowspan="4" |I/O| rowspan="4" |internal pull-up 100k to NVCC_SNVS_1V8|ALT0|SAI3_TX_BCLK
|-
|J1.24|PMIC_PWRON|PMIC.PWRON| 22| '''(*)''' 3.3VIN|I|internal pull-up 100k to VIN'''(*)''' default as ''Embedded'' power mode|||-| rowspan="5" |J1.26| rowspan="5" |SAI3_RXC| rowspan="5" |CPU.SAI3_RXC| rowspan="5" |AG7| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI3_RX_BCLK|-|ALT1|GPT1_COMPARE2GPT1_CLK
|-
|ALT2
|SAI5_RX_DATA2SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|UART2_CTS_B
|-
|ALT5
|GPIO5_IO00GPIO4_IO29
|-
| rowspan="4" |J1.5228| rowspan="4" |SAI3_TXDGPIO1_IO02| rowspan="4" |CPU.SAI3_TXDGPIO1_IO02| rowspan="4" |C3AG13
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for PMIC WDI, do not connect
|ALT0
|SAI3_TX_DATA0GPIO1_IO02
|-
|ALT1
|GPT1_COMPARE3WDOG1_WDOG_B
|-
|ALT2ALT5|SAI5_RX_DATA3WDOG1_WDOG_ANY
|-
|ALT5ALT7|GPIO5_IO01SJC_DE_B
|-
| rowspan="2" |J1.54| rowspan="2" |GPIO1_IO10| rowspan="2" |CPU.GPIO1_IO10| rowspan="2" |M7| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0|GPIO1_IO10|-|ALT1|USB1_OTG_ID|-|J1.5630
|DGND
|DGND
|
|-
| rowspan="45" |J1.5832| rowspan="45" |SAI5_MCLKSAI3_RXD| rowspan="45" |CPU.SAI5_MCLKSAI3_RXD| rowspan="45" |K4AF7| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |
|ALT0
|SAI5_MCLKSAI3_RX_DATA0
|-
|ALT1
|SAI1_TX_BCLKGPT1_COMPARE1
|-
|ALT2
|SAI4_MCLKSAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT2)|-|ALT4|UART2_RTS_B(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|GPIO3_IO25GPIO4_IO30
|-
| rowspan="43" |J1.6034| rowspan="43" |GPIO1_IO15SAI2_MCLK| rowspan="43" |CPU.GPIO1_IO15SAI2_MCLK| rowspan="43" |J6AD19| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|GPIO1_IO15SAI2_MCLK
|-
|ALT1
|USB2_OTG_OCSAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)
|-
|ALT5
|PWM4_OUTGPIO4_IO27
|-
|ALT6|CCM_CLKO2|-| rowspan="35" |J1.6236| rowspan="35" |SAI5_RXFSSAI3_RXFS| rowspan="35" |CPU.SAI5_RXFSSAI3_RXFS| rowspan="35" |N4AG8| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|SAI5_RX_SYNCSAI3_RX_SYNC
|-
|ALT1
|SAI1_TX_DATA0GPT1_CAPTURE1
|-
|ALT5ALT2|GPIO3_IO19SAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT2)
|-
| rowspan="3" |J1.64| rowspan="3" |SAI5_RXC| rowspan="3" |CPU.SAI5_RXC| rowspan="3" |L5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_BCLK|-|ALT1ALT3|SAI1_TX_DATA1SAI3_RX_DATA1
|-
|ALT5
|GPIO3_IO20GPIO4_IO28
|-
| rowspan="34" |J1.6638| rowspan="34" |SAI2_TXCI2C3_SCL| rowspan="34" |CPU.SAI2_TXCI2C3_SCL| rowspan="34" |J5E10| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|SAI2_TX_BCLKI2C3_SCL
|-
|ALT1
|SAI5_TX_DATA2PWM4_OUT|-|ALT2|GPT2_CLK
|-
|ALT5
|GPIO4_IO25GPIO5_IO18
|-
| rowspan="36" |J1.6840| rowspan="36" |SAI2_TXD0SAI3_TXFS| rowspan="36" |CPU.SAI2_TXD0SAI3_TXFS| rowspan="36" |G5AC6| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|SAI2_TX_DATA0SAI3_TX_SYNC
|-
|ALT1
|SAI5_TX_DATA3GPT1_CAPTURE2
|-
|ALT5ALT2|GPIO4_IO26SAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT2)
|-
| rowspan="3" |J1.70| rowspan="3" |SAI2_TXFS| rowspan="3" |CPU.SAI2_TXFS| rowspan="3" |H4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0ALT3|SAI2_TX_SYNCSAI3_TX_DATA1
|-
|ALT1ALT4|SAI5_TX_DATA1UART2_RX
|-
|ALT5
|GPIO4_IO24GPIO4_IO31
|-
| rowspan="3" |J1.7242| rowspan="3" |SAI2_RXD0SPDIF_RX| rowspan="3" |CPU.SAI2_RXD0SPDIF_RX| rowspan="3" |H6AG9
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_RX_DATA0SPDIF1_IN
|-
|ALT1
|SAI5_TX_DATA0PWM2_OUT
|-
|ALT5
|GPIO4_IO23GPIO5_IO04
|-
| rowspan="3" |J1.7444| rowspan="3" |SAI5_RXD0SPDIF_TX| rowspan="3" |CPU.SAI5_RXD0SPDIF_TX| rowspan="3" |M5AF9
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI5_RX_DATA0 SPDIF1_OUT
|-
|ALT1
|SAI1_TX_DATA2PWM3_OUT
|-
|ALT5
|GPIO3_IO21GPIO5_IO03
|-
| rowspan="54" |J1.7646| rowspan="54" |SAI5_RXD1SAI3_MCLK| rowspan="54" |CPU.SAI5_RXD1SAI3_MCLK| rowspan="54" |L4AD6| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |
|ALT0
|SAI5_RX_DATA1SAI3_MCLK
|-
|ALT1
|SAI1_TX_DATA3PWM4_OUT
|-
|ALT2
|SAI1_TX_SYNCSAI5_MCLK|-|ALT3|SAI5_TX_SYNC(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO3_IO212GPIO5_IO02
|-
| rowspan="54" |J1.7848| rowspan="54" |SAI5_RXD2I2C3_SDA| rowspan="54" |CPU.SAI5_RXD2I2C3_SDA| rowspan="54" |M4F10| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |
|ALT0
|SAI5_RX_DATA2I2C3_SDA
|-
|ALT1
|SAI1_TX_DATA4PWM3_OUT
|-
|ALT2
|SAI1_TX_SYNC|-|ALT3|SAI5_TX_BCLKGPT3_CLK
|-
|ALT5
|GPIO3_IO23GPIO5_IO19
|-
| rowspan="5" |J1.8050| rowspan="5" |SAI5_RXD3SAI3_TXC| rowspan="5" |CPU.SAI5_RXD3SAI3_TXC| rowspan="5" |K5AG6
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
|ALT0
|SAI5_RX_DATA3SAI3_TX_BCLK
|-
|ALT1
|SAI1_TX_DATA5GPT1_COMPARE2
|-
|ALT2
|SAI1_TX_SYNCSAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT2)
|-
|ALT3ALT4|SAI5_TX_DATA0UART2_TX
|-
|ALT5
|GPIO3_IO24GPIO5_IO00
|-
| rowspan="4" |J1.8252|DGNDrowspan="4" |SAI3_TXD| rowspan="4" |CPU.SAI3_TXD|DGNDrowspan="4" |AF6| -rowspan="4" |NVCC_3V3|<nowiki>-<rowspan="4" |I/nowiki>O|Growspan="4" ||ALT0|SAI3_TX_DATA0
|-
|J1.84|CLK2_N|CPU.CLK2_N|T22|VDDA_1V8|D|Internally used for PCIe CLK, do not connect|ALT1|GPT1_COMPARE3
|-
|ALT2|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT2)|-|ALT5|GPIO5_IO01|-| rowspan="5" |J1.8654|CLK2_Prowspan="5" |SAI1_MCLK| rowspan="5" |CPU.CLK2_PSAI1_MCLK| rowspan="5" |AB18| rowspan="5" |NVCC_3V3| rowspan="5" |I/O|U22rowspan="5" ||VDDA_1V8ALT0|DSAI1_MCLK|Internally used -|ALT1|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for PCIe CLK, do not connectmode ALT1)|-|ALT2|SAI1_TX_BCLK(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT3|PDM_CLK
|-
|J1.88|PCIE1_REF_CLKN|CPU.PCIE1_REF_PAD_CLK_N|K24|VDD_PHY_3V3|D||ALT5|GPIO4_IO20
|-
|J1.9056|PCIE1_REF_CLKPDGND|CPU.PCIE1_REF_PAD_CLK_PDGND|K25-|VDD_PHY_3V3<nowiki>-</nowiki>|DG
|
|
|
|-
| rowspan="3" |J1.9258|PCIE1_RXNrowspan="3" |SAI5_MCLK| rowspan="3" |CPU.PCIE1_RXN_NSAI5_MCLK|H24rowspan="3" |AD15|VDD_PHY_3V3rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT0)
|-
|J1.94ALT1|PCIE1_RXPSAI1_TX_BCLK|CPU.PCIE1_RXN_P|H25|VDD_PHY_3V3|D|||(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|J1.96|PCIE1_TXN|CPU.PCIE1_TXN_N|J24|VDD_PHY_3V3|D||ALT5|GPIO3_IO25
|-
| rowspan="2" |J1.9860|PCIE1_TXProwspan="2" |GPIO1_IO10| rowspan="2" |CPU.PCIE1_TXN_PGPIO1_IO10|J25rowspan="2" |AD10| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" |Internally used for ETH PHY interrupt, do not connect|VDD_PHY_3V3ALT0|DGPIO1_IO10|-|ALT1|USB1_OTG_ID
|-
| rowspan="3" |J1.10062|DGNDrowspan="3" |SAI5_RXFS|DGNDrowspan="3" |CPU.SAI5_RXFS| -rowspan="3" |AB15|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|SAI5_RX_SYNC|(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT0)
|-
|J1.102|CSI1_CLK_N|CPU.MIPI_CSI1_CLK_N|A22| -|D||ALT1|SAI1_TX_DATA0
|-
|J1.104|CSI1_CLK_P|CPU.MIPI_CSI1_CLK_P|B22| -|D||ALT5|GPIO3_IO19
|-
| rowspan="4" |J1.10664|CSI1_D0_Nrowspan="4" |SAI5_RXC| rowspan="4" |CPU.MIPI_CSI1_D0_NSAI5_RXC|A23rowspan="4" |AC15| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT0)
|-
|J1.108|CSI1_D0_P|CPU.MIPI_CSI1_D0_P|B23| -|D||ALT1|SAI1_TX_DATA1
|-
|J1.110|CSI1_D1_N|CPU.MIPI_CSI1_D1_N|C22| -|D||ALT4|PDM_CLK
|-
|ALT5|GPIO3_IO20|-| rowspan="3" |J1.11266|CSI1_D1_Prowspan="3" |SAI2_TXC| rowspan="3" |CPU.MIPI_CSI1_D1_PSAI2_TXC|D22rowspan="3" |AD22| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_BCLK
|-
|J1.114|CSI1_D2_N|CPU.MIPI_CSI1_D2_N|B24| -|D||ALT1|SAI5_TX_DATA2
|-
|J1.116|CSI1_D2_P|CPU.MIPI_CSI1_D2_P|C23| -|D||ALT5|GPIO4_IO25
|-
| rowspan="3" |J1.11868|CSI1_D3_Nrowspan="3" |SAI2_TXD0| rowspan="3" |CPU.MIPI_CSI1_D3_NSAI2_TXD0|C21rowspan="3" |AC22| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_DATA0
|-
|J1.120|CSI1_D3_P|CPU.MIPI_CSI1_D3_P|D21| -|D||ALT1|SAI5_TX_DATA3
|-
|J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO4_IO26
|-
|J1.124(NAND on board)|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="35" |J1.124(eMMC on board)70| rowspan="35" |NAND_DQSSAI2_TXFS| rowspan="35" |CPU.NAND_DQSSAI2_TXFS| rowspan="35" |M20AD23| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|RAWNAND_DQSSAI2_TX_SYNC
|-
|ALT1
|QSPI_A_DQSSAI5_TX_DATA1|-|ALT3|SAI2_TX_DATA1|-|ALT4|UART1_CTS_B
|-
|ALT5
|GPIO3_IO14GPIO4_IO24
|-
| rowspan="4" |J1.12672(NAND on board)| rowspan="4" |SAI2_RXD0|NAND_ALErowspan="4" |CPU.NAND_ALESAI2_RXD0|G19rowspan="4" |AC24| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|Internally used rowspan="4" ||ALT0|SAI2_RX_DATA0|-|ALT1|SAI5_TX_DATA0|-|ALT4|UART1_RTS_B(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for NAND, do not connectmode ALT4)|-|ALT5|GPIO4_IO23
|-
| rowspan="3" |J1.126(eMMC on board)74| rowspan="3" |NAND_ALEI2C4_SDA| rowspan="3" |CPU.NAND_ALEI2C4_SDA| rowspan="3" |G19E13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_ALEI2C4_SDA
|-
|ALT1
|QSPI_A_SCLKPWM1_OUT
|-
|ALT5
|GPIO3_IO00GPIO5_IO21
|-
| rowspan="24" |J1.128(NAND on board)76| rowspan="24" |SD1_CLKI2C4_SCL| rowspan="24" |CPU.SD1_CLKI2C4_SCL| rowspan="24" |L25D13| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_CLKI2C4_SCL
|-
|ALT1|PWM2_OUT|-|ALT2|PCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO2_IO00GPIO5_IO20
|-
| rowspan="36" |J1.128(eMMC on board)78| rowspan="36" |NAND_CE0_BSAI5_RXD2| rowspan="36" |CPU.NAND_CE0_BSAI5_RXD2| rowspan="36" |H19AD13| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|RAWNAND_CE0_BSAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT0)
|-
|ALT1
|QSPI_A_SS0_BSAI1_TX_DATA4|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT3)|-|ALT4|PDM_BIT_STREAM2(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT4)
|-
|ALT5
|GPIO3_IO01GPIO3_IO23
|-
| rowspan="26" |J1.130(NAND on board)80| rowspan="26" |SD1_CMDSAI5_RXD3| rowspan="26" |CPU.SD1_CMDSAI5_RXD3| rowspan="26" |L24AC13| rowspan="26" |NVCC_3V3(NVCC_1V8 on request)| rowspan="26" |I/O| rowspan="26" |
|ALT0
|USDHC1_CMDSAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT0)|-|ALT1|SAI1_TX_DATA5
|-
|ALT5ALT2|GPIO2_IO01SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)
|-
| rowspan="3" |J1.130(eMMC on board)| rowspan="3" |NAND_CE1_B| rowspan="3" |CPU.NAND_CE1_B| rowspan="3" |G21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0ALT3|RAWNAND_CE1_BSAI5_TX_DATA0
|-
|ALT1ALT4|QSPI_A_SS1_BPDM_BIT_STREAM3(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT4)
|-
|ALT5
|GPIO3_IO02GPIO3_IO24
|-
| rowspan="2" |J1.132(NAND on board)| rowspan="2" |SD1_RST_B82| rowspan="2" |CPU.SD1_RST_BDGND| rowspan="2" |R24DGND| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I<nowiki>-</Onowiki>| rowspan="2" G||ALT0|USDHC1_RESET_B
|-
|ALT5J1.84|PCIE1_REF_CLKN|CPU.PCIE_REF_CLK_N|A21|VDDA_1V8|D|||GPIO2_IO10
|-
| rowspan="3" |J1.132(eMMC on board)86| rowspan="3" |NAND_CE2_BPCIE1_REF_CLKP| rowspan="3" |CPU.NAND_CE2_BPCIE_REF_CLK_P| rowspan="3" |F21B21| rowspan="3" |NVCC_3V3VDDA_1V8| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_CE2_B
|-
|ALT1J1.88|CLKIN1|CPU.CLKIN1|H27|NVCC_3V3|I|||QSPI_B_SS0_B
|-
|ALT5J1.90|CLKIN2|CPU.CLKIN2|J27|NVCC_3V3|I|||GPIO3_IO03
|-
| rowspan="2" |J1.134(NAND on board)92| rowspan="2" |SD1_STROBEPCIE1_RXN| rowspan="2" |CPU.SD1_STROBEPCIE_RXN_N| rowspan="2" |T24A19| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)VDDA_1V8| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_STROBE
|-
|ALT5J1.94|PCIE1_RXP|CPU.PCIE_RXN_P|B19|VDDA_1V8|D|||GPIO2_IO11
|-
| rowspan="3" |J1.134(eMMC on board)96| rowspan="3" |NAND_CE3_BPCIE1_TXN| rowspan="3" |CPU.NAND_CE3_BPCIE_TXN_N| rowspan="3" |H20A20| rowspan="3" |NVCC_3V3VDDA_1V8| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_CE3_B
|-
|ALT1|QSPI_B_SS1_B|-|ALT5|GPIO3_IO034|-|J1.136(NAND on board)98|NAND_CLEPCIE1_TXP|CPU.NAND_CLEPCIE_TXN_P|H21B20|NVCC_3V3VDDA_1V8|I/OD|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.136100(eMMC on board)| rowspan="3" |NAND_CLEDGND| rowspan="3" |CPU.NAND_CLEDGND| rowspan="3" |H21-| rowspan="3" |NVCC_3V3<nowiki>-</nowiki>| rowspan="3" |I/OG| rowspan="3" ||ALT0|RAWNAND_CLE
|-
|ALT1J1.102|CSI_P1_CKN|CPU.MIPI_CSI_CLK_N|A16| -|D|||QSPI_B_SCLK
|-
|ALT5J1.104|CSI_P1_CKP|CPU.MIPI_CSI_CLK_P|B16| -|D|||GPIO3_IO05
|-
| rowspan="2" |J1.138(NAND on board)106| rowspan="2" |SD1_DATA0CSI_P1_DN0| rowspan="2" |CPU.SD1_DATA0MIPI_CSI_D0_N| rowspan="2" |M25A14| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA0
|-
|ALT5J1.108|CSI_P1_DP0|CPU.MIPI_CSI_D0_P|B14| -|D|||GPIO2_IO02
|-
| rowspan="3" |J1.138(eMMC on board)110| rowspan="3" |NAND_DATA00CSI_P1_DN1| rowspan="3" |CPU.NAND_DATA00MIPI_CSI_D1_N| rowspan="3" |G20A15| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA00
|-
|ALT1J1.112|CSI_P1_DP1|CPU.MIPI_CSI_D1_P|B15| -|D|||QSPI_A_DATA0
|-
|ALT5J1.114|CSI_P1_DN2|CPU.MIPI_CSI_D2_N|A17| -|D|||GPIO3_IO06
|-
| rowspan="2" |J1.140(NAND on board)116| rowspan="2" |SD1_DATA1CSI_P1_DP2| rowspan="2" |CPU.SD1_DATA1MIPI_CSI_D2_P| rowspan="2" |M24B17| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA1
|-
|ALT5J1.118|CSI_P1_DN3|CPU.MIPI_CSI_D3_N|A18| -|D|||GPIO2_IO0
|-
| rowspan="3" |J1.140(eMMC on board)120| rowspan="3" |NAND_DATA01CSI_P1_DP3| rowspan="3" |CPU.NAND_DATA01MIPI_CSI_D3_P| rowspan="3" |J20B18| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA01
|-
|ALT1J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G|||QSPI_A_DATA1
|-
|ALT5|GPIO3_IO07|-| rowspan="2" |J1.142124
(NAND on board)
| rowspan="2" |SD1_DATA2NAND_DQS| rowspan="2" |CPU.SD1_DATA2NAND_DQS| rowspan="2" |N25R22| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" |Internally used for NAND, do not connect|ALT0|USDHC1_DATA2
|-
|ALT5|GPIO2_IO04|-| rowspan="3" |J1.142124
(eMMC on board)
| rowspan="3" |NAND_DATA02NAND_DQS| rowspan="3" |CPU.NAND_DATA02NAND_DQS| rowspan="3" |H22R22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA02RAWNAND_DQS
|-
|ALT1
|QSPI_A_DATA2QSPI_A_DQS
|-
|ALT5
|GPIO3_IO08GPIO3_IO14
|-
| rowspan="2" |J1.144126
(NAND on board)
| rowspan="2" |SD1_DATA3NAND_ALE| rowspan="2" |CPU.SD1_DATA3NAND_ALE| rowspan="2" |P25N22| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" |Internally used for NAND, do not connect|ALT0|USDHC1_DATA3
|-
|ALT5|GPIO2_IO05|-| rowspan="3" |J1.144126
(eMMC on board)
| rowspan="3" |NAND_DATA03NAND_ALE| rowspan="3" |CPU.NAND_DATA03NAND_ALE| rowspan="3" |J21N22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA03RAWNAND_ALE
|-
|ALT1
|QSPI_A_DATA3QSPI_A_SCLK
|-
|ALT5
|GPIO3_IO09GPIO3_IO00
|-
|J1.146|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="2" |J1.148128
(NAND on board)
| rowspan="2" |SD1_DATA4SD1_CLK| rowspan="2" |CPU.SD1_DATA4SD1_CLK| rowspan="2" |N24V26
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |
|ALT0
|USDHC1_DATA4USDHC1_CLK
|-
|ALT5
|GPIO2_IO06GPIO2_IO00
|-
| rowspan="3" |J1.148128
(eMMC on board)
| rowspan="3" |NAND_DATA04NAND_CE0_B| rowspan="3" |CPU.NAND_DATA04NAND_CE0_B| rowspan="3" |L20N24
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA04RAWNAND_CE0_B
|-
|ALT1
|QSPI_B_DATA0QSPI_A_SS0_B
|-
|ALT5
|GPIO3_IO10GPIO3_IO01
|-
| rowspan="2" |J1.150130
(NAND on board)
| rowspan="2" |SD1_DATA5SD1_CMD| rowspan="2" |CPU.SD1_DATA5SD1_CMD| rowspan="2" |P24V27
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |
|ALT0
|USDHC1_DATA5USDHC1_CMD
|-
|ALT5
|GPIO2_IO07GPIO2_IO01
|-
| rowspan="34" |J1.150130
(eMMC on board)
| rowspan="34" |NAND_DATA05NAND_CE1_B| rowspan="34" |CPU.NAND_DATA05NAND_CE1_B| rowspan="34" |J22P27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA05RAWNAND_CE1_B
|-
|ALT1
|QSPI_B_DATA1QSPI_A_SS1_B|-|ALT2|USDHC3_STROBE
|-
|ALT5
|GPIO3_IO11GPIO3_IO02
|-
| rowspan="2" |J1.152132
(NAND on board)
| rowspan="2" |SD1_DATA6SD1_RST_B| rowspan="2" |CPU.SD1_DATA6SD1_RST_B| rowspan="2" |R25R23
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |
|ALT0
|USDHC1_DATA6USDHC1_RESET_B
|-
|ALT5
|GPIO2_IO08GPIO2_IO10
|-
| rowspan="34" |J1.152132
(eMMC on board)
| rowspan="34" |NAND_DATA06NAND_CE2_B| rowspan="34" |CPU.NAND_DATA06NAND_CE2_B| rowspan="34" |L19M27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA06RAWNAND_CE2_B
|-
|ALT1
|QSPI_B_DATA2QSPI_B_SS0_B|-|ALT2|USDHC3_DATA5
|-
|ALT5
|GPIO3_IO12GPIO3_IO03
|-
| rowspan="2" |J1.154134
(NAND on board)
| rowspan="2" |SD1_DATA7SD1_STROBE| rowspan="2" |CPU.SD1_DATA7SD1_STROBE| rowspan="2" |T25R24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |
|ALT0
|USDHC1_DATA7USDHC1_STROBE
|-
|ALT5
|GPIO2_IO09GPIO2_IO11
|-
| rowspan="34" |J1.154134
(eMMC on board)
| rowspan="34" |NAND_DATA07NAND_CE3_B| rowspan="34" |CPU.NAND_DATA07NAND_CE3_B| rowspan="34" |M19L27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DATA07RAWNAND_CE3_B
|-
|ALT1
|QSPI_B_DATA3QSPI_B_SS1_B|-|ALT2|USDHC3_DATA6
|-
|ALT5
|GPIO3_IO13GPIO3_IO034
|-
|J1.156136
(NAND on board)
|NAND_RE_BNAND_CLE|CPU.NAND_RE_BNAND_CLE|K19K27
|NVCC_3V3
|I/O
|
|-
| rowspan="34" |J1.156136
(eMMC on board)
| rowspan="34" |NAND_RE_BNAND_CLE| rowspan="34" |CPU.NAND_RE_BNAND_CLE| rowspan="34" |K19K27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_RE_BRAWNAND_CLE
|-
|ALT1
|QSPI_B_DQSQSPI_B_SCLK|-|ALT2|USDHC3_DATA7
|-
|ALT5
|GPIO3_IO15GPIO3_IO05
|-
| rowspan="2" |J1.158138
(NAND on board)
|NAND_READY_B|CPU.NAND_READY_B|K20|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="2" |J1.158(eMMC on board)| rowspan="2" |NAND_READY_BSD1_DATA0| rowspan="2" |CPU.NAND_READY_BSD1_DATA0| rowspan="2" |K20Y27
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_READY_BUSDHC1_DATA0
|-
|ALT5
|GPIO3_IO16GPIO2_IO02
|-
|J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|K22|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="23" |J1.160138
(eMMC on board)
| rowspan="23" |NAND_WE_BNAND_DATA00| rowspan="23" |CPU.NAND_WE_BNAND_DATA00| rowspan="23" |K22P23| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |
|ALT0
|RAWNAND_WE_BRAWNAND_DATA00|-|ALT1|QSPI_A_DATA0
|-
|ALT5
|GPIO3_IO17GPIO3_IO06
|-
| rowspan="2" |J1.162140
(NAND on board)
|NAND_WP_B|CPU.NAND_WP_B|K21|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="2" |J1.162(eMMC on board)| rowspan="2" |NAND_WP_BSD1_DATA1| rowspan="2" |CPU.NAND_WP_BSD1_DATA1| rowspan="2" |K21Y26
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WP_BUSDHC1_DATA1
|-
|ALT5
|GPIO3_IO18GPIO2_IO0
|-
| rowspan="3" |J1.164140(eMMC on board)| rowspan="3" |DGNDNAND_DATA01|DGNDrowspan="3" |CPU.NAND_DATA01| -rowspan="3" |K24|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_DATA01
|-
|J1.166|CLK1_N|CPU.CLK1_N|T23||D||ALT1|QSPI_A_DATA1
|-
|J1.168|CLK1_P|CPU.CLK1_P|R23||D||ALT5|GPIO3_IO07
|-
| rowspan="2" |J1.170142(NAND on board)|USB2_RXNrowspan="2" |SD1_DATA2| rowspan="2" |CPU.USB2_RX_NSD1_DATA2|B8rowspan="2" |T27|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA2
|-
|J1.172|USB2_RXP|CPU.USB2_RX_P|A8||D||ALT5|GPIO2_IO04
|-
| rowspan="4" |J1.174142(eMMC on board)|USB2_TXNrowspan="4" |NAND_DATA02| rowspan="4" |CPU.USB2_TX_NNAND_DATA02|B9rowspan="4" |K23|rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA02
|-
|J1.176|USB2_TXP|CPU.USB2_TX_P|A9||D||ALT1|QSPI_A_DATA2
|-
|J1.178ALT2|USB1_RXNUSDHC3_CD_B|CPU.USB1_RX_N|B12||D|||(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)
|-
|J1.180|USB1_RXP|CPU.USB1_RX_P|A12||D||ALT5|GPIO3_IO08
|-
| rowspan="2" |J1.182144(NAND on board)|USB1_TXNrowspan="2" |SD1_DATA3| rowspan="2" |CPU.USB1_TX_NSD1_DATA3|B13rowspan="2" |T26|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3
|-
|J1.184|USB1_TXP|CPU.USB1_TX_P|A13||D||ALT5|GPIO2_IO05
|-
| rowspan="4" |J1.144(eMMC on board)| rowspan="4" |NAND_DATA03| rowspan="4" |CPU.NAND_DATA03| rowspan="4" |N23| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT2|USDHC3_WP(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO3_IO09|-|J1.146|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="2" |J1.148(NAND on board)| rowspan="2" |SD1_DATA4| rowspan="2" |CPU.SD1_DATA4| rowspan="2" |U27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4|-|ALT5|GPIO2_IO06|-| rowspan="4" |J1.148(eMMC on board)| rowspan="4" |NAND_DATA04| rowspan="4" |CPU.NAND_DATA04| rowspan="4" |M26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA04|-|ALT1|QSPI_B_DATA0|-|ALT2|USDHC3_DATA0|-|ALT5|GPIO3_IO10|-| rowspan="2" |J1.150(NAND on board)| rowspan="2" |SD1_DATA5| rowspan="2" |CPU.SD1_DATA5| rowspan="2" |U26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA5|-|ALT5|GPIO2_IO07|-| rowspan="4" |J1.150(eMMC on board)| rowspan="4" |NAND_DATA05| rowspan="4" |CPU.NAND_DATA05| rowspan="4" |L26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA05|-|ALT1|QSPI_B_DATA1|-|ALT2|USDHC3_DATA1|-|ALT5|GPIO3_IO11|-| rowspan="2" |J1.152(NAND on board)| rowspan="2" |SD1_DATA6| rowspan="2" |CPU.SD1_DATA6| rowspan="2" |W27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA6|-|ALT5|GPIO2_IO08|-| rowspan="4" |J1.152(eMMC on board)| rowspan="4" |NAND_DATA06| rowspan="4" |CPU.NAND_DATA06| rowspan="4" |K26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA06|-|ALT1|QSPI_B_DATA2|-|ALT2|USDHC3_DATA2|-|ALT5|GPIO3_IO12|-| rowspan="2" |J1.154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |W26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09|-| rowspan="4" |J1.154(eMMC on board)| rowspan="4" |NAND_DATA07| rowspan="4" |CPU.NAND_DATA07| rowspan="4" |N26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT2|USDHC3_DATA3|-|ALT5|GPIO3_IO13|-|J1.156(NAND on board)|NAND_RE_B|CPU.NAND_RE_B|N27|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="4" |J1.156(eMMC on board)| rowspan="4" |NAND_RE_B| rowspan="4" |CPU.NAND_RE_B| rowspan="4" |N27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_RE_B|-|ALT1|QSPI_B_DQS|-|ALT2|USDHC3_DATA4|-|ALT5|GPIO3_IO15|-|J1.158(NAND on board)|NAND_READY_B|CPU.NAND_READY_B|P26|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.158(eMMC on board)| rowspan="3" |NAND_READY_B| rowspan="3" |CPU.NAND_READY_B| rowspan="3" |P26| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_READY_B|-|ALT2|USDHC3_RESET_B|-|ALT5|GPIO3_IO16|-|J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|R26|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.160(eMMC on board)| rowspan="3" |NAND_WE_B| rowspan="3" |CPU.NAND_WE_B| rowspan="3" |R26| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_WE_B|-|ALT2|USDHC3_CLK|-|ALT5|GPIO3_IO17|-|J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|R27|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.162(eMMC on board)| rowspan="3" |NAND_WP_B| rowspan="3" |CPU.NAND_WP_B| rowspan="3" |R27| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_WP_B|-|ALT2|USDHC3_CMD|-|ALT5|GPIO3_IO18|-|J1.164|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="5" |J1.166| rowspan="5" |GPIO1_IO15| rowspan="5" |CPU.GPIO1_IO15| rowspan="5" |AB9| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|GPIO1_IO15|-|ALT1|USB2_OTG_OC|-|ALT4|USDHC3_WP(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT4)|-|ALT5|PWM4_OUT|-|ALT6|CCM_CLKO2|-| rowspan="4" |J1.168| rowspan="4" |GPIO1_IO07| rowspan="4" |CPU.GPIO1_IO07| rowspan="4" |AF11| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO07|-|ALT1|ENET1_MDIO(Configure register IOMUXC_ENET1_MDIO_SELECT_INPUT for mode ALT1)|-|ALT5|USDHC1_WP|-|ALT6|CCM_EXT_CLK4|-| rowspan="6" |J1.170| rowspan="6" |SAI1_TXD4| rowspan="6" |CPU.SAI1_TXD4| rowspan="6" |AG22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA4|-|ALT1|SAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_BCLK(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE12|-|ALT5|GPIO4_IO16|-|ALT6|SRC_BOOT_CFG12|-| rowspan="6" |J1.172| rowspan="6" |SAI1_TXD5| rowspan="6" |CPU.SAI1_TXD5| rowspan="6" |AF22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA5|-|ALT1|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT1)|-|ALT2|SAI6_TX_DATA0|-|ALT4|CORESIGHT_TRACE13|-|ALT5|GPIO4_IO17|-|ALT6|SRC_BOOT_CFG13|-| rowspan="6" |J1.174| rowspan="6" |SAI1_TXD6| rowspan="6" |CPU.SAI1_TXD6| rowspan="6" |AG23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA6|-|ALT1|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE14|-|ALT5|GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14|-| rowspan="6" |J1.176| rowspan="6" |SAI1_TXD7| rowspan="6" |CPU.SAI1_TXD7| rowspan="6" |AF23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT3|PDM_CLK|-|ALT4|CORESIGHT_TRACE15|-|ALT5|GPIO4_IO19|-|ALT6|SRC_BOOT_CFG15|-| rowspan="7" |J1.178| rowspan="7" |SAI1_RXD7| rowspan="7" |CPU.SAI1_RXD7| rowspan="7" |AF19| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI1_TX_DATA4|-|ALT4|CORESIGHT_TRACE7|-|ALT5|GPIO4_IO09|-|ALT6|SRC_BOOT_CFG7|-| rowspan="6" |J1.180| rowspan="6" |SAI1_RXD6| rowspan="6" |CPU.SAI1_RXD6| rowspan="6" |AG19| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA6|-|ALT1|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE6|-|ALT5|GPIO4_IO08|-|ALT6|SRC_BOOT_CFG6|-| rowspan="7" |J1.182| rowspan="7" |SAI1_RXD5| rowspan="7" |CPU.SAI1_RXD5| rowspan="7" |AF18| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA5|-|ALT1|SAI6_TX_DATA0|-|ALT2|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT2)|-|ALT3|SAI1_RX_SYNC(Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT3)|-|ALT4|CORESIGHT_TRACE5|-|ALT5|GPIO4_IO07|-|ALT6|SRC_BOOT_CFG|-| rowspan="6" |J1.184| rowspan="6" |SAI1_RXD4| rowspan="6" |CPU.SAI1_RXD4| rowspan="6" |AG18| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA4|-|ALT1|SAI1_RX_DATA4(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE4|-|ALT5|GPIO4_IO06|-|ALT6|SRC_BOOT_CFG4|-|J1.186|USB1_VBUS|CPU.USB1_VBUS|D14F22| -|S|Connected with 30K resistor on SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.188|USB2_VBUS|CPU.USB2_VBUS|D9F23| -|S|Connected with 30K resistor on SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.190|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J1.192|USB1_ID|CPU.USB1_ID|C14D22|VDD_PHY_3V3VDDA_1V8|I||||-|J1.194|USB2_ID|CPU.USB2_ID|C9D23|VDD_PHY_3V3VDDA_1V8
|I
|
|USB1_DN
|CPU.USB1_DN
|B14A22
| -
|D
|USB1_DP
|CPU.USB1_DP
|A14B22
| -
|D
|USB2_DP
|CPU.USB2_DP
|A10B23
| -
|D
|USB2_DN
|CPU.USB2_DN
|B10A23
| -
|D
|-
|}
'''(*)''' PMIC_PWRON can be used in two configuration: ''Embedded-like'' (default mounting option) or ''Tablet-like''. In the first case, the system reboots in case of PMIC_PWR_ON signal activity.
 
In the second case, the system will shut down waiting for a CPU_ONOFF signal raising (like a button-mode in a tablet) and the PMIC_PWRON Voltage domain is NVCC_SNVS_1V8
Please contact [mailto:sales@dave.eu sales dept.] for more information
----
[[Category:MITO 8M Mini]]
[[Category:MITO 8M Nano]]
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