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MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table

14,607 bytes added, 18:06, 27 December 2023
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=== Connectors description ===
In the following table are described all available connectors integrated on MITO 8M Mini/Nano SOM:
{| class="wikitable"
|-
|-
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini/Nano pinout specifications. See the images below for reference:
[[File:MITO_8M_Mini_MITO8M_Mini-_TOPconn-top.jpegpng|500px|thumb|MITO 8M Mini/Nano TOP view|none]][[File:MITO_8M_Mini_MITO8M_Mini-conn-_BOTTOMbottom.jpegpng|500px|thumb|MITO 8M Mini/Nano BOTTOM view|none]]
Below a detailed description of the pinout, grouped in the following tables:
|-
|'''Pin Name'''
| Pin (signal) name on the MITO 8M Mini connectors
|-
|'''Internal<br>connections'''
| Connections to the components
* CPU.<x> : pin connected to CPU pad named <x>(NXP iMX8MM)* PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210PF8121)
* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition| MITO 8M Mini SOM P/N composition]] (boot from eMMC, NAND, etc.)
|ALT0
|SAI1_RX_DATA3
|SRC_BOOT_CFG3
|-
| rowspan="5" |J1.107|HDMI_AUX_Prowspan="5" |SAI1_TXD3| rowspan="5" |CPU.HDMI_AUX_PSAI1_TXD3| rowspan="5" |AF21| rowspan="5" | NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA3|-|ALT1|SAI5_TX_DATA3|-|ALT4|CORESIGHT_TRACE11| -|DALT5|connected with capacitor in seriesGPIO4_IO15|-|ALT6|SRC_BOOT_CFG11
|-
|J1.109
|
|-
| rowspan="4" |J1.111|HDMI_TX_M_LN_3rowspan="4" |SAI1_TXFS| rowspan="4" |CPU.HDMI_TX_M_LN_3SAI1_TXFS|rowspan="4" |AB19| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O|connected with capacitor in seriesrowspan="4" ||ALT0|SAI1_TX_SYNC (Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT0)
|-
|J1.113ALT1|HDMI_TX_P_LN_3SAI5_TX_SYNC|CPU.HDMI_TX_P_LN_3|| -|D|connected with capacitor in series||(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
|-
|J1.115|HDMI_TX_M_LN_0|CPU.HDMI_TX_M_LN_0|| -|D|connected with capacitor in series|ALT4|CORESIGHT_EVENTO
|-
|J1.117|HDMI_TX_P_LN_0|CPU.HDMI_TX_P_LN_0|| -|D|connected with capacitor in series|ALT5|GPIO4_IO10
|-
| rowspan="4" |J1.119113|HDMI_TX_M_LN_1rowspan="4" |SAI1_TXC| rowspan="4" |CPU.HDMI_TX_M_LN_1SAI1_TXC|rowspan="4" |AC18| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O|connected with capacitor in seriesrowspan="4" ||ALT0|SAI1_TX_BCLK (Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT0)
|-
|J1.121ALT1|HDMI_TX_P_LN_1SAI5_TX_BCLK|CPU.HDMI_TX_P_LN_1|| -|D|connected with capacitor in series||(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|ALT4|CORESIGHT_EVENTI|-|ALT5|GPIO4_IO11|-| rowspan="5" |J1.123115|HDMI_TX_M_LN_2rowspan="5" |SAI1_TXD0| rowspan="5" |CPU.HDMI_TX_M_LN_2SAI1_TXD0| rowspan="5" |AG20| rowspan="5" |NVCC_3V3|rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on|D[[MITO 8M Mini SOM/Part number composition|connected with capacitor in seriesMITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA0
|-
|J1.125|HDMI_TX_P_LN_2|CPU.HDMI_TX_P_LN_2|| -|D|connected with capacitor in series|ALT1|SAI5_TX_DATA0
|-
|J1.127|HDMI_CEC|CPU.HDMI_CEC||VDD_PHY_1V8|I/O||ALT4|CORESIGHT_TRACE8
|-
|J1.129|HDMI_HPD|CPU.HDMI_HPD||VDD_PHY_1V8|I/O||ALT5|GPIO4_IO12
|-
|J1.131|DGND |DGND| -| -|G||ALT6|SRC_BOOT_CFG8
|-
| rowspan="5" |J1.133117|LVDS0_CLK_Nrowspan="5" |SAI1_TXD1|BRIDGErowspan="5" |CPU.A_CLKNSAI1_TXD1| rowspan="5" |AF20| rowspan="5" |NVCC_3V3|F9rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on|D[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA1
|-
|J1.135|LVDS0_CLK_P|BRIDGE.A_CLKP|F8| -|D||ALT1|SAI5_TX_DATA1
|-
|J1.137|LVDS0_TX0_N|BRIDGE.A_Y0N|C9| -|D||ALT4|CORESIGHT_TRACE9
|-
|J1.139|LVDS0_TX0_P|BRIDGE.A_Y0P|C8| -|D||ALT5|GPIO4_IO13
|-
|J1.141|LVDS0_TX1_N|BRIDGE.A_Y1N|D9| -|D||ALT6|SRC_BOOT_CFG9
|-
| rowspan="5" |J1.143119|LVDS0_TX1_Prowspan="5" |SAI1_TXD2|BRIDGErowspan="5" |CPU.A_Y1PSAI1_TXD2| rowspan="5" |AG21| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|D8MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA2| -|DALT1|SAI5_TX_DATA2|-|ALT4|CORESIGHT_TRACE10
|-
|J1.145|LVDS0_TX2_N|BRIDGE.A_Y2N|E9| -|D||ALT5|GPIO4_IO14
|-
|J1.147|LVDS0_TX2_P|BRIDGE.A_Y2P|E8| -|D||ALT6|SRC_BOOT_CFG10
|-
| rowspan="4" |J1.149121|LVDS0_TX3_Nrowspan="4" |SAI1_RXFS|BRIDGErowspan="4" |CPU.A_Y3NSAI1_RXFS| rowspan="4" |AG16| rowspan="4" |NVCC_3V3|G9rowspan="4" |I/O| -rowspan="4" ||DALT0|SAI1_RX_SYNC (Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT1)
|-
|J1.151|LVDS0_TX3_P|BRIDGE.A_Y3P|G8| -|D||ALT4|CORESIGHT_TRACE_CLK
|-
|J1.153|DGND |DGND| -| -|G||ALT5|GPIO4_IO00
|-
| rowspan="4" |J1.155123|LVDS1_CLK_Nrowspan="4" |SAI1_RXC|BRIDGErowspan="4" |CPU.B_CLKNSAI1_RXC| rowspan="4" |AF16| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|A6rowspan="4" || -ALT0|DSAI1_RX_BCLK|-|ALT1|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT1)
|-
|J1.157|LVDS1_CLK_P|BRIDGE.B_CLKP|B6| -|D||ALT4|CORESIGHT_TRACE_CTL
|-
|J1.159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D||ALT5|GPIO4_IO01
|-
| rowspan="7" |J1.161125|LVDS1_TX0_Prowspan="7" |SAI1_RXD0|BRIDGErowspan="7" |CPU.B_Y0PSAI1_RXD0| rowspan="7" |AG15| rowspan="7" |NVCC_3V3|B3rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on|D[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA0
|-
|J1.163ALT1|LVDS1_TX1_NSAI5_RX_DATA0|BRIDGE.B_Y1N|A4| -|D|||(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT1)
|-
|J1.165|LVDS1_TX1_P|BRIDGE.B_Y1P|B4| -|D||ALT2|SAI1_TX_DATA1
|-
|J1.167ALT3|LVDS1_TX2_NPDM_BIT_STREAM0|BRIDGE.B_Y2N|A5(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT3)| -|D||ALT4|CORESIGHT_TRACE0
|-
|J1.169|LVDS1_TX2_P|BRIDGE.B_Y2P|B5| -|D||ALT5|GPIO4_IO02
|-
|J1.171|LVDS1_TX3_N|BRIDGE.B_Y3N|A7| -|D||ALT6|SRC_BOOT_CFG0
|-
| rowspan="6" |J1.173127|LVDS1_TX3_Prowspan="6" |SAI1_RXD1|BRIDGErowspan="6" |CPU.B_Y3PSAI1_RXD1| rowspan="6" |AF15|B7rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|DALT0|SAI1_RX_DATA1|-|ALT1|SAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT1)
|-
|J1.175ALT3|DGND PDM_BIT_STREAM1|DGND| -| -|G|||(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT3)
|-
| rowspan="2" |J1.177| rowspan="2" |SD2_CD_B| rowspan="2" |CPU.SD2_CD_B| rowspan="2" || rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0ALT4|USDHC2_CD_BCORESIGHT_TRACE1
|-
|ALT5
|GPIO2_IO12GPIO4_IO03
|-
|ALT6|SRC_BOOT_CFG1|-| rowspan="36" |J1.179129| rowspan="36" |ECSPI1_SS0SAI1_RXD2| rowspan="36" |CPU.ECSPI1_SS0SAI1_RXD2| rowspan="36" |AG17| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|ECSPI1_SS0SAI1_RX_DATA2
|-
|ALT1
|UART3_RTS_BSAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT1)
|-
|ALT5ALT3|GPIO5_IO09PDM_BIT_STREAM2(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT3)
|-
| rowspan="3" |J1.181| rowspan="3" |ECSPI1_SCLK| rowspan="3" |CPU.ECSPI1_SCLK| rowspan="3" || rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_SCLK|-|ALT1ALT4|UART3_RXCORESIGHT_TRACE2
|-
|ALT5
|GPIO5_IO06GPIO4_IO04
|-
| rowspan="3" |J1.183| rowspan="3" |ECSPI1_MISO| rowspan="3" |CPU.ECSPI1_MISO| rowspan="3" || rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0ALT6|ECSPI1_MISOSRC_BOOT_CFG2
|-
|ALT1J1.131|DGND |DGND| -| -|G|||UART3_CTS_B
|-
|ALT5J1.133|LVDS0_CLK_N|BRIDGE.A_CLKN|F9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO08
|-
| rowspan="3" |J1.185133| rowspan="3" |GPIO1_IO03DSI_CLK_N| rowspan="3" |CPU.GPIO1_IO03MIPI_DSI_CLK_N| rowspan="3" A11|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|GPIO1_IO03
|-
|ALT1J1.135|LVDS0_CLK_P|BRIDGE.A_CLKP|F8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||USDHC1_VSELECT
|-
|ALT5J1.135|DSI_CLK_P|CPU.MIPI_|B11| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||SDMA1_EXT_EVENT0
|-
| rowspan="3" J1.137|LVDS0_TX0_N|J1BRIDGE.187A_Y0N| rowspan="3" C9|UART2_TXD-| rowspan="3" D|CPUDepending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.UART2_TXD137| rowspan="3" DSI_D0_N|CPU.MIPI_DSI_D0_N| rowspan="3" A9|NVCC_3V3-| rowspan="3" D|IDepending on [[MITO 8M Mini SOM/OPart number composition| rowspan="3" |used as default Linux consoleMITO 8M Mini SOM P/N composition]]|ALT0|UART2_TX
|-
|ALT1J1.139|LVDS0_TX0_P|BRIDGE.A_Y0P|C8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_SS0
|-
|ALT5J1.139|DSI_D0_P|CPU.MIPI_DSI_D0_P|B9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO25
|-
| rowspan="3" |J1.189141| rowspan="3" |UART2_RXDLVDS0_TX1_N| rowspan="3" |CPUBRIDGE.UART2_RXDA_Y1N| rowspan="3" D9|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |used as default Linux consoleN composition]]|ALT0|UART2_RXD
|-
|ALT1J1.141|DSI_D1_N|CPU.MIPI_DSI_D1_N|A10| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_MISO
|-
|ALT5J1.143|LVDS0_TX1_P|BRIDGE.A_Y1P|D8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO24
|-
| rowspan="3" |J1.191143| rowspan="3" |UART1_TXDDSI_D1_P| rowspan="3" |CPU.UART1_TXDMIPI_DSI_D1_P| rowspan="3" B10|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|UART1_TX
|-
|ALT1J1.145|LVDS0_TX2_N|BRIDGE.A_Y2N|E9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_MOSI
|-
|ALT5J1.145|DSI_D2_N|CPU.MIPI_DSI_D2_N|A12| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO23
|-
| rowspan="3" J1.147|LVDS0_TX2_P|J1BRIDGE.193A_Y2P| rowspan="3" E8|UART1_RXD-| rowspan="3" D|CPUDepending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|||-|J1.UART1_RXD147| rowspan="3" DSI_D2_P|CPU.MIPI_DSI_D2_P| rowspan="3" B12|NVCC_3V3-| rowspan="3" D|IDepending on [[MITO 8M Mini SOM/O| rowspan="3" Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|UART1_RXD
|-
|ALT1J1.149|LVDS0_TX3_N|BRIDGE.A_Y3N|G9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_SCLK
|-
|ALT5J1.149|DSI_D3_N|CPU.MIPI_DSI_D3_N|A13| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO22
|-
| rowspan="3" |J1.195151| rowspan="3" |ECSPI1_MOSILVDS0_TX3_P| rowspan="3" |CPUBRIDGE.ECSPI1_MOSIA_Y3P| rowspan="3" G8|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|ECSPI1_MOSI
|-
|ALT1J1.151|DSI_D3_P|CPU.MIPI_DSI_D3_P|B13| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||UART3_TX
|-
|ALT5J1.153|DGND |DGND| -| -|G|||GPIO5_IO07
|-
| rowspan="4" |J1.197155| rowspan="4" |GPIO1_IO14LVDS1_CLK_N| rowspan="4" |CPUBRIDGE.GPIO1_IO14B_CLKN| rowspan="4" |A6| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OD| rowspan="4" ||ALT0|GPIO1_IO14
|-
|ALT1J1.157|LVDS1_CLK_P|BRIDGE.B_CLKP|B6| -|D|||USB2_OTG_PWR
|-
|ALT5J1.159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D|||PWM3_OUT
|-
|ALT6J1.161|LVDS1_TX0_P|BRIDGE.B_Y0P|B3| -|D|||CCM_CLKO1
|-
| rowspan="3" |J1.199163| rowspan="3" |GPIO1_IO04LVDS1_TX1_N| rowspan="3" |CPUBRIDGE.GPIO1_IO04B_Y1N| rowspan="3" |A4| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|GPIO1_IO04
|-
|ALT1J1.165|LVDS1_TX1_P|BRIDGE.B_Y1P|B4| -|D|||USDHC2_VSELECT
|-
|ALT5J1.167|LVDS1_TX2_N|BRIDGE.B_Y2N|A5| -|D|||SDMA1_EXT_EVENT1
|-
| rowspan="3" |J1.201169| rowspan="3" |GPIO1_IO12LVDS1_TX2_P| rowspan="3" |CPUBRIDGE.GPIO1_IO12| rowspan="3" || rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO12|-|ALT1|USB1_OTG_PWR|-|ALT5|SDMA2_EXT_EVENT1|-|J1.203|DGND B_Y2P|DGNDB5
| -
| -|GD
|
|
|
|-
|} ==SODIMM J1 EVEN pins declaration ==.171 {| class="wikitable" LVDS1_TX3_N! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" | Alternative Functions|-|J1BRIDGE.2|DGNDB_Y3N|DGNDA7
| -
|<nowiki>-</nowiki>|GD
|
|
|
|-
|J1.4173|3LVDS1_TX3_P|BRIDGE.3VIN B_Y3P|INPUT VOLTAGEB7
| -
|3.3VIN|SD
|
|
|
|-
|J1.6175|3.3VIN DGND |INPUT VOLTAGEDGND
| -
|3.3VIN
|S
|
|
|
|-
|J1.8
|3.3VIN
|INPUT VOLTAGE
| -
|3.3VIN|SG
|
|
|
|-
| rowspan="2" |J1.10177|3rowspan="2" |SD2_CD_B| rowspan="2" |CPU.3VIN SD2_CD_B|INPUT VOLTAGErowspan="2" |AA26| -rowspan="2" |NVCC_3V3|3.3VINrowspan="2" |I/O|Srowspan="2" ||ALT0|USDHC2_CD_B
|-
|J1.12|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO2_IO12
|-
| rowspan="3" |J1.14179|PMIC_LICELL rowspan="3" |ECSPI1_SS0|PMICrowspan="3" |CPU.LICELLECSPI1_SS0|30rowspan="3" |B6| -rowspan="3" |NVCC_3V3|Srowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_SS0
|-
|J1.16ALT1|CPU_ONOFFUART3_RTS_B|CPU.ONOFF|W21|NVCC_SNVS|I|internal pull-up 100k to NVCC_SNVS||(Configure register IOMUXC_UART3_RTS_B_SELECT_INPUT for mode ALT1)
|-
|J1.18|BOARD_PGOOD| -| -|NVCC_3V3|O||ALT5|GPIO5_IO09
|-
| rowspan="3" |J1.20181|BOOT_MODE_SELrowspan="3" |ECSPI1_SCLK|BOOT MODE SELECTIONrowspan="3" |CPU.ECSPI1_SCLK| -rowspan="3" |D6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internal pull-up to NVCC_3V3rowspan="3" ||ALT0|ECSPI1_SCLK
|-
|J1.22|CPU_PORn|CPU.POR_BPMIC.RESETMCU|W203|NVCC_SNVS|I/O|internal pull-up 100k to NVCC_SNVS|ALT1|UART3_RX
|-
|J1.24|EXT_RESET|MASTER RESET| -| -|I|internal pull-up to NVCC_SNVS|ALT5|GPIO5_IO06
|-
| rowspan="43" |J1.26183| rowspan="43" |SAI3_RXCECSPI1_MISO| rowspan="43" |CPU.SAI3_RXCECSPI1_MISO| rowspan="43" |F4A7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_RX_BCLKECSPI1_MISO
|-
|ALT1
|GPT1_CAPTURE2|-|ALT2|SAI5_RX_BCLKUART3_CTS_B
|-
|ALT5
|GPIO4_IO29GPIO5_IO08
|-
| rowspan="43" |J1.28185| rowspan="43" |GPIO1_IO02GPIO1_IO03| rowspan="43" |CPU.GPIO1_IO02GPIO1_IO03| rowspan="43" |R4AF13| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |Internally used for SW resetPMIC interrupt, do not connect Pulled-up to NVCC_3V3
|ALT0
|GPIO1_IO02GPIO1_IO03
|-
|ALT1
|WDOG1_WDOG_BUSDHC1_VSELECT
|-
|ALT5
|WDOG1_WDOG_ANYSDMA1_EXT_EVENT0
|-
|ALT7|SJC_DE_B|-|J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="43" |J1.32187| rowspan="43" |SAI3_RXDUART2_TXD| rowspan="43" |CPU.SAI3_RXDUART2_TXD| rowspan="43" |F3E15| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |used as default Linux console
|ALT0
|SAI3_RX_DATA0UART2_TX
|-
|ALT1
|GPT1_COMPARE1|-|ALT2|SAI5_RX_DATA0ECSPI3_SS0
|-
|ALT5
|GPIO4_IO30GPIO5_IO25
|-
| rowspan="3" |J1.34189| rowspan="3" |SAI2_MCLKUART2_RXD| rowspan="3" |CPU.SAI2_MCLKUART2_RXD| rowspan="3" |H5F15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|SAI2_MCLKUART2_RXD
|-
|ALT1
|SAI5_MCLKECSPI3_MISO
|-
|ALT5
|GPIO4_IO27GPIO5_IO24
|-
| rowspan="43" |J1.36191| rowspan="43" |SAI3_RXFSUART4_TXD| rowspan="43" |CPU.SAI3_RXFSUART4_TXD| rowspan="43" |G4F18| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_RX_SYNCUART4_TX
|-
|ALT1
|GPT1_CAPTURE1UART2_RTS_B|-|ALT2|SAI5_RX_SYNC(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO4_IO28GPIO5_IO29
|-
| rowspan="4" |J1.38193| rowspan="4" |I2C3_SCLUART4_RXD| rowspan="4" |CPU.I2C3_SCLUART4_RXD| rowspan="4" |G8F19
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C3_SCLUART4_RX
|-
|ALT1
|PWM4_OUTUART2_CTS_B
|-
|ALT2
|GPT2_CLKPCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO5_IO18GPIO5_IO28
|-
| rowspan="43" |J1.40195| rowspan="43" |SAI3_TXFSECSPI1_MOSI| rowspan="43" |CPU.SAI3_TXFSECSPI1_MOSI| rowspan="43" |G3B7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_TX_SYNCECSPI1_MOSI
|-
|ALT1
|GPT1_CLK|-|ALT2|SAI5_RX_DATA1UART3_TX
|-
|ALT5
|GPIO4_IO31GPIO5_IO07
|-
| rowspan="35" |J1.42197| rowspan="35" |SPDIF_RXGPIO1_IO14| rowspan="35" |CPU.SPDIF_RXGPIO1_IO14| rowspan="35" |G6AC9| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|SPDIF1_INGPIO1_IO14
|-
|ALT1
|PWM2_OUTUSB2_OTG_PWR|-|ALT4|USDHC3_CD_B(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|GPIO5_IO04PWM3_OUT
|-
|ALT6|CCM_CLKO1|-| rowspan="3" |J1.44199| rowspan="3" |SPDIF_TXGPIO1_IO04| rowspan="3" |CPU.SPDIF_TXGPIO1_IO04| rowspan="3" |F6AG12
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_OUTGPIO1_IO04
|-
|ALT1
|PWM3_OUTUSDHC2_VSELECT
|-
|ALT5
|GPIO5_IO03SDMA1_EXT_EVENT1
|-
| rowspan="43" |J1.46201| rowspan="43" |SAI3_MCLKGPIO1_IO12| rowspan="43" |CPU.SAI3_MCLKGPIO1_IO12| rowspan="43" |D3AB10| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_MCLKGPIO1_IO12
|-
|ALT1
|PWM4_OUT|-|ALT2|SAI5_MCLKUSB1_OTG_PWR
|-
|ALT5
|GPIO5_IO02SDMA2_EXT_EVENT1
|-
| rowspan="4" |J1.48203| rowspan="4" |I2C3_SDADGND | rowspan="4" |CPU.I2C3_SDADGND| rowspan="4" |E9-| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OG| rowspan="4" ||ALT0|I2C3_SDA
|-
|ALT1} ==SODIMM J1 EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" |PWM3_OUTAlternative Functions
|-
|ALT2J1.2|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPT3_CLK
|-
|ALT5J1.4|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||GPIO5_IO19
|-
| rowspan="4" |J1.506| rowspan="4" |SAI3_TXC3.3VIN | rowspan="4" |CPU.SAI3_TXCINPUT VOLTAGE| rowspan="4" |C4-| rowspan="4" |NVCC_3V33.3VIN| rowspan="4" |I/OS| rowspan="4" ||ALT0|SAI3_TX_BCLK
|-
|ALT1J1.8|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||GPT1_COMPARE2
|-
|ALT2J1.10|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||SAI5_RX_DATA2
|-
|ALT5J1.12|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO5_IO00
|-
| rowspan="4" |J1.52| rowspan="4" |SAI3_TXD| rowspan="4" |CPU.SAI3_TXD| rowspan="4" |C3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_DATA0|-|ALT1|GPT1_COMPARE3|-|ALT2|SAI5_RX_DATA3|-|ALT5|GPIO5_IO01|-| rowspan="2" |J1.5414| rowspan="2" |GPIO1_IO10PMIC_LICELL | rowspan="2" |CPUPMIC.GPIO1_IO10LICELL| rowspan="2" |M7| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0|GPIO1_IO10|-|ALT1|USB1_OTG_ID|-|J1.56|DGND|DGND| -46|<nowiki>-</nowiki>|GS
|
|
|
|-
| rowspan="4" |J1.5816| rowspan="4" |SAI5_MCLKCPU_ONOFF| rowspan="4" |CPU.SAI5_MCLKONOFF| rowspan="4" |K4A25| rowspan="4" |NVCC_3V3NVCC_SNVS_1V8| rowspan="4" |I/O| rowspan="4" |internal pull-up 100k to NVCC_SNVS_1V8|ALT0|SAI5_MCLK
|-
|ALT1J1.18|BOARD_PGOOD| -| -|NVCC_3V3|O|||SAI1_TX_BCLK
|-
|ALT2J1.20|BOOT_MODE_SEL|BOOT MODE SELECTION| -|NVCC_3V3|I|internal pull-up to NVCC_3V3||SAI4_MCLK
|-
|ALT5J1.22|CPU_PORn|CPU.POR_BPMIC.RESET_MCU|B2421|NVCC_SNVS_1V8|I/O|internal pull-up 100k to NVCC_SNVS_1V8|||-|J1.24|PMIC_PWRON|PMIC.PWRON| 22| '''(*)''' 3.3VIN|I|internal pull-up 100k to VIN'''(*)''' default as ''Embedded'' power mode||GPIO3_IO25|-| rowspan="45" |J1.6026| rowspan="45" |GPIO1_IO15SAI3_RXC| rowspan="45" |CPU.GPIO1_IO15SAI3_RXC| rowspan="45" |J6AG7| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |
|ALT0
|GPIO1_IO15SAI3_RX_BCLK
|-
|ALT1
|USB2_OTG_OCGPT1_CLK|-|ALT2|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|UART2_CTS_B
|-
|ALT5
|PWM4_OUTGPIO4_IO29
|-
|ALT6|CCM_CLKO2|-| rowspan="34" |J1.6228| rowspan="34" |SAI5_RXFSGPIO1_IO02| rowspan="34" |CPU.SAI5_RXFSGPIO1_IO02| rowspan="34" |N4AG13| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |Internally used for PMIC WDI, do not connect|ALT0|SAI5_RX_SYNCGPIO1_IO02
|-
|ALT1
|SAI1_TX_DATA0WDOG1_WDOG_B
|-
|ALT5
|GPIO3_IO19WDOG1_WDOG_ANY|-|ALT7|SJC_DE_B|-|J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G|||
|-
| rowspan="35" |J1.6432| rowspan="35" |SAI5_RXCSAI3_RXD| rowspan="35" |CPU.SAI5_RXCSAI3_RXD| rowspan="35" |L5AF7| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|SAI5_RX_BCLKSAI3_RX_DATA0
|-
|ALT1
|SAI1_TX_DATA1GPT1_COMPARE1
|-
|ALT5ALT2|GPIO3_IO20SAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT2)
|-
| rowspan="3" |J1.66| rowspan="3" |SAI2_TXC| rowspan="3" |CPU.SAI2_TXC| rowspan="3" |J5| rowspan="3" |NVCC_3V3| rowspan="3" |I/OALT4| rowspan="3" |UART2_RTS_B|ALT0|SAI2_TX_BCLK|-|ALT1|SAI5_TX_DATA2(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|GPIO4_IO25GPIO4_IO30
|-
| rowspan="3" |J1.6834| rowspan="3" |SAI2_TXD0SAI2_MCLK| rowspan="3" |CPU.SAI2_TXD0SAI2_MCLK| rowspan="3" |G5AD19
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_TX_DATA0SAI2_MCLK
|-
|ALT1
|SAI5_TX_DATA3SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO4_IO26GPIO4_IO27
|-
| rowspan="35" |J1.7036| rowspan="35" |SAI2_TXFSSAI3_RXFS| rowspan="35" |CPU.SAI2_TXFSSAI3_RXFS| rowspan="35" |H4AG8| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|SAI2_TX_SYNCSAI3_RX_SYNC
|-
|ALT1
|SAI5_TX_DATA1GPT1_CAPTURE1|-|ALT2|SAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI3_RX_DATA1
|-
|ALT5
|GPIO4_IO24GPIO4_IO28
|-
| rowspan="34" |J1.7238| rowspan="34" |SAI2_RXD0I2C3_SCL| rowspan="34" |CPU.SAI2_RXD0I2C3_SCL| rowspan="34" |H6E10| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|SAI2_RX_DATA0I2C3_SCL
|-
|ALT1
|SAI5_TX_DATA0PWM4_OUT|-|ALT2|GPT2_CLK
|-
|ALT5
|GPIO4_IO23GPIO5_IO18
|-
| rowspan="36" |J1.7440| rowspan="36" |SAI5_RXD0SAI3_TXFS| rowspan="36" |CPU.SAI5_RXD0SAI3_TXFS| rowspan="36" |M5AC6| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|SAI5_RX_DATA0 SAI3_TX_SYNC
|-
|ALT1
|SAI1_TX_DATA2GPT1_CAPTURE2
|-
|ALT5|GPIO3_IO21|-| rowspan="5" |J1.76| rowspan="5" |SAI5_RXD1| rowspan="5" |CPU.SAI5_RXD1| rowspan="5" |L4| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0ALT2
|SAI5_RX_DATA1
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT2)
|-
|ALT1ALT3|SAI1_TX_DATA3SAI3_TX_DATA1
|-
|ALT2ALT4|SAI1_TX_SYNC|-|ALT3|SAI5_TX_SYNCUART2_RX
|-
|ALT5
|GPIO3_IO212GPIO4_IO31
|-
| rowspan="53" |J1.7842| rowspan="53" |SAI5_RXD2SPDIF_RX| rowspan="53" |CPU.SAI5_RXD2SPDIF_RX| rowspan="53" |M4AG9| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |
|ALT0
|SAI5_RX_DATA2SPDIF1_IN
|-
|ALT1
|SAI1_TX_DATA4PWM2_OUT
|-
|ALT2ALT5|SAI1_TX_SYNCGPIO5_IO04
|-
|ALT3rowspan="3" |J1.44| rowspan="3" |SPDIF_TX| rowspan="3" |CPU.SPDIF_TX| rowspan="3" |AF9| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SPDIF1_OUT|-|ALT1|SAI5_TX_BCLKPWM3_OUT
|-
|ALT5
|GPIO3_IO23GPIO5_IO03
|-
| rowspan="54" |J1.8046| rowspan="54" |SAI5_RXD3SAI3_MCLK| rowspan="54" |CPU.SAI5_RXD3SAI3_MCLK| rowspan="54" |K5AD6| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |
|ALT0
|SAI5_RX_DATA3SAI3_MCLK
|-
|ALT1
|SAI1_TX_DATA5PWM4_OUT
|-
|ALT2
|SAI1_TX_SYNCSAI5_MCLK|-|ALT3|SAI5_TX_DATA0(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO3_IO24GPIO5_IO02
|-
| rowspan="4" |J1.8248|DGNDrowspan="4" |I2C3_SDA|DGNDrowspan="4" |CPU.I2C3_SDA| -rowspan="4" |F10| rowspan="4" |NVCC_3V3|<nowiki>-<rowspan="4" |I/nowiki>O| rowspan="4" ||ALT0|GI2C3_SDA|-|ALT1|PWM3_OUT
|-
|J1.84|CLK2_N|CPU.CLK2_N|T22|VDDA_1V8|D|Internally used for PCIe CLK, do not connect|ALT2|GPT3_CLK
|-
|J1.86|CLK2_P|CPU.CLK2_P|U22|VDDA_1V8|D|Internally used for PCIe CLK, do not connect|ALT5|GPIO5_IO19
|-
| rowspan="5" |J1.8850|PCIE1_REF_CLKNrowspan="5" |SAI3_TXC| rowspan="5" |CPU.PCIE1_REF_PAD_CLK_NSAI3_TXC|K24rowspan="5" |AG6|VDD_PHY_3V3rowspan="5" |NVCC_3V3|Drowspan="5" |I/O| rowspan="5" ||ALT0|SAI3_TX_BCLK
|-
|J1.90|PCIE1_REF_CLKP|CPU.PCIE1_REF_PAD_CLK_P|K25|VDD_PHY_3V3|D||ALT1|GPT1_COMPARE2
|-
|J1.92ALT2|PCIE1_RXNSAI5_RX_DATA2|CPU.PCIE1_RXN_N|H24|VDD_PHY_3V3|D|||(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT2)
|-
|J1.94|PCIE1_RXP|CPU.PCIE1_RXN_P|H25|VDD_PHY_3V3|D||ALT4|UART2_TX
|-
|ALT5|GPIO5_IO00|-| rowspan="4" |J1.9652|PCIE1_TXNrowspan="4" |SAI3_TXD| rowspan="4" |CPU.PCIE1_TXN_NSAI3_TXD|J24rowspan="4" |AF6|VDD_PHY_3V3rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_DATA0
|-
|J1.98|PCIE1_TXP|CPU.PCIE1_TXN_P|J25|VDD_PHY_3V3|D||ALT1|GPT1_COMPARE3
|-
|J1.100ALT2|DGNDSAI5_RX_DATA3|DGND| -|<nowiki>-</nowiki>|G|||(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT2)
|-
|ALT5|GPIO5_IO01|-| rowspan="5" |J1.10254|CSI1_CLK_Nrowspan="5" |SAI1_MCLK| rowspan="5" |CPU.MIPI_CSI1_CLK_NSAI1_MCLK| rowspan="5" |AB18| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI1_MCLK|-|A22ALT1|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)| -|DALT2|SAI1_TX_BCLK(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT3|PDM_CLK
|-
|J1.104|CSI1_CLK_P|CPU.MIPI_CSI1_CLK_P|B22| -|D||ALT5|GPIO4_IO20
|-
|J1.10656|CSI1_D0_NDGND|CPU.MIPI_CSI1_D0_N|A23DGND
| -
|D<nowiki>-</nowiki>|G
|
|
|
|-
| rowspan="3" |J1.10858|CSI1_D0_Prowspan="3" |SAI5_MCLK| rowspan="3" |CPU.MIPI_CSI1_D0_PSAI5_MCLK|B23rowspan="3" |AD15| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT0)
|-
|J1.110ALT1|CSI1_D1_NSAI1_TX_BCLK|CPU.MIPI_CSI1_D1_N|C22| -|D|||(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|J1.112|CSI1_D1_P|CPU.MIPI_CSI1_D1_P|D22| -|D||ALT5|GPIO3_IO25
|-
| rowspan="2" |J1.11460|CSI1_D2_Nrowspan="2" |GPIO1_IO10| rowspan="2" |CPU.MIPI_CSI1_D2_NGPIO1_IO10|B24rowspan="2" |AD10| -rowspan="2" |NVCC_3V3|Drowspan="2" |I/O|rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0|GPIO1_IO10
|-
|J1.116|CSI1_D2_P|CPU.MIPI_CSI1_D2_P|C23| -|D||ALT1|USB1_OTG_ID
|-
| rowspan="3" |J1.11862|CSI1_D3_Nrowspan="3" |SAI5_RXFS| rowspan="3" |CPU.MIPI_CSI1_D3_NSAI5_RXFS|C21rowspan="3" |AB15| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT0)
|-
|J1.120|CSI1_D3_P|CPU.MIPI_CSI1_D3_P|D21| -|D||ALT1|SAI1_TX_DATA0
|-
|J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO3_IO19
|-
|J1.124(NAND on board)|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="34" |J1.124(eMMC on board)64| rowspan="34" |NAND_DQSSAI5_RXC| rowspan="34" |CPU.NAND_DQSSAI5_RXC| rowspan="34" |M20AC15| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DQSSAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT0)
|-
|ALT1
|QSPI_A_DQSSAI1_TX_DATA1|-|ALT4|PDM_CLK
|-
|ALT5
|GPIO3_IO14GPIO3_IO20
|-
|J1.126(NAND on board)|NAND_ALE|CPU.NAND_ALE|G19|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.126(eMMC on board)66| rowspan="3" |NAND_ALESAI2_TXC| rowspan="3" |CPU.NAND_ALESAI2_TXC| rowspan="3" |G19AD22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_ALESAI2_TX_BCLK
|-
|ALT1
|QSPI_A_SCLKSAI5_TX_DATA2
|-
|ALT5
|GPIO3_IO00GPIO4_IO25
|-
| rowspan="23" |J1.128(NAND on board)68| rowspan="23" |SD1_CLKSAI2_TXD0| rowspan="23" |CPU.SD1_CLKSAI2_TXD0| rowspan="23" |L25AC22| rowspan="23" |NVCC_3V3(NVCC_1V8 on request)| rowspan="23" |I/O| rowspan="23" |
|ALT0
|USDHC1_CLKSAI2_TX_DATA0|-|ALT1|SAI5_TX_DATA3
|-
|ALT5
|GPIO2_IO00GPIO4_IO26
|-
| rowspan="35" |J1.128(eMMC on board)70| rowspan="35" |NAND_CE0_BSAI2_TXFS| rowspan="35" |CPU.NAND_CE0_BSAI2_TXFS| rowspan="35" |H19AD23| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|RAWNAND_CE0_BSAI2_TX_SYNC
|-
|ALT1
|QSPI_A_SS0_BSAI5_TX_DATA1|-|ALT3|SAI2_TX_DATA1|-|ALT4|UART1_CTS_B
|-
|ALT5
|GPIO3_IO01GPIO4_IO24
|-
| rowspan="24" |J1.130(NAND on board)72| rowspan="24" |SD1_CMDSAI2_RXD0| rowspan="24" |CPU.SD1_CMDSAI2_RXD0| rowspan="24" |L24AC24| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_CMDSAI2_RX_DATA0|-|ALT1|SAI5_TX_DATA0|-|ALT4|UART1_RTS_B(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|GPIO2_IO01GPIO4_IO23
|-
| rowspan="3" |J1.130(eMMC on board)74| rowspan="3" |NAND_CE1_BI2C4_SDA| rowspan="3" |CPU.NAND_CE1_BI2C4_SDA| rowspan="3" |G21E13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE1_BI2C4_SDA
|-
|ALT1
|QSPI_A_SS1_BPWM1_OUT
|-
|ALT5
|GPIO3_IO02GPIO5_IO21
|-
| rowspan="24" |J1.132(NAND on board)76| rowspan="24" |SD1_RST_BI2C4_SCL| rowspan="24" |CPU.SD1_RST_BI2C4_SCL| rowspan="24" |R24D13| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_RESET_BI2C4_SCL|-|ALT1|PWM2_OUT|-|ALT2|PCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO2_IO10GPIO5_IO20
|-
| rowspan="36" |J1.132(eMMC on board)78| rowspan="36" |NAND_CE2_BSAI5_RXD2| rowspan="36" |CPU.NAND_CE2_BSAI5_RXD2| rowspan="36" |F21AD13| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|RAWNAND_CE2_BSAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT0)
|-
|ALT1
|QSPI_B_SS0_BSAI1_TX_DATA4|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)
|-
|ALT5ALT3|GPIO3_IO03SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT3)
|-
| rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_STROBE| rowspan="2" |T24ALT4| rowspan="2" |NVCC_3V3PDM_BIT_STREAM2(NVCC_1V8 on requestConfigure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT4)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_STROBE
|-
|ALT5
|GPIO2_IO11GPIO3_IO23
|-
| rowspan="36" |J1.134(eMMC on board)80| rowspan="36" |NAND_CE3_BSAI5_RXD3| rowspan="36" |CPU.NAND_CE3_BSAI5_RXD3| rowspan="36" |H20AC13| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|RAWNAND_CE3_BSAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT0)
|-
|ALT1
|QSPI_B_SS1_BSAI1_TX_DATA5
|-
|ALT5ALT2|GPIO3_IO034SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)
|-
|J1.136(NAND on board)|NAND_CLE|CPU.NAND_CLE|H21|NVCC_3V3|I/O|Internally used for NAND, do not connect|ALT3|SAI5_TX_DATA0
|-
| rowspan="3" ALT4|J1.136PDM_BIT_STREAM3(eMMC on boardConfigure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT4)| rowspan="3" |NAND_CLE| rowspan="3" |CPU.NAND_CLE| rowspan="3" |H21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CLE|-|ALT1|QSPI_B_SCLK
|-
|ALT5
|GPIO3_IO05GPIO3_IO24
|-
| rowspan="2" |J1.138(NAND on board)| rowspan="2" |SD1_DATA082| rowspan="2" |CPU.SD1_DATA0DGND| rowspan="2" |M25DGND| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I<nowiki>-</Onowiki>| rowspan="2" G||ALT0|USDHC1_DATA0
|-
|ALT5J1.84|PCIE1_REF_CLKN|CPU.PCIE_REF_CLK_N|A21|VDDA_1V8|D|||GPIO2_IO02
|-
| rowspan="3" |J1.138(eMMC on board)86| rowspan="3" |NAND_DATA00PCIE1_REF_CLKP| rowspan="3" |CPU.NAND_DATA00PCIE_REF_CLK_P| rowspan="3" |G20B21| rowspan="3" |NVCC_3V3VDDA_1V8| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA00
|-
|ALT1J1.88|CLKIN1|CPU.CLKIN1|H27|NVCC_3V3|I|||QSPI_A_DATA0
|-
|ALT5J1.90|CLKIN2|CPU.CLKIN2|J27|NVCC_3V3|I|||GPIO3_IO06
|-
| rowspan="2" |J1.140(NAND on board)92| rowspan="2" |SD1_DATA1PCIE1_RXN| rowspan="2" |CPU.SD1_DATA1PCIE_RXN_N| rowspan="2" |M24A19| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)VDDA_1V8| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA1
|-
|ALT5J1.94|PCIE1_RXP|CPU.PCIE_RXN_P|B19|VDDA_1V8|D|||GPIO2_IO0
|-
| rowspan="3" |J1.140(eMMC on board)96| rowspan="3" |NAND_DATA01PCIE1_TXN| rowspan="3" |CPU.NAND_DATA01PCIE_TXN_N| rowspan="3" |J20A20| rowspan="3" |NVCC_3V3VDDA_1V8| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA01
|-
|ALT1J1.98|PCIE1_TXP|CPU.PCIE_TXN_P|B20|VDDA_1V8|D|||QSPI_A_DATA1
|-
|ALT5J1.100|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO3_IO07
|-
| rowspan="2" |J1.142(NAND on board)102| rowspan="2" |SD1_DATA2CSI_P1_CKN| rowspan="2" |CPU.SD1_DATA2MIPI_CSI_CLK_N| rowspan="2" |N25A16| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA2
|-
|ALT5J1.104|CSI_P1_CKP|CPU.MIPI_CSI_CLK_P|B16| -|D|||GPIO2_IO04
|-
| rowspan="3" |J1.142(eMMC on board)106| rowspan="3" |NAND_DATA02CSI_P1_DN0| rowspan="3" |CPU.NAND_DATA02MIPI_CSI_D0_N| rowspan="3" |H22A14| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA02
|-
|ALT1J1.108|CSI_P1_DP0|CPU.MIPI_CSI_D0_P|B14| -|D|||QSPI_A_DATA2
|-
|ALT5|GPIO3_IO08|-| rowspan="2" |J1.144(NAND on board)110| rowspan="2" |SD1_DATA3CSI_P1_DN1| rowspan="2" |CPU.SD1_DATA3MIPI_CSI_D1_N| rowspan="2" |P25A15| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA3
|-
|ALT5|GPIO2_IO05|-| rowspan="3" |J1.144112(eMMC on board)| rowspan="3" |NAND_DATA03CSI_P1_DP1| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.146|DGNDMIPI_CSI_D1_P|DGNDB15
| -
|<nowiki>-</nowiki>|GD
|
|
|
|-
| rowspan="2" |J1.148(NAND on board)114| rowspan="2" |SD1_DATA4CSI_P1_DN2| rowspan="2" |CPU.SD1_DATA4MIPI_CSI_D2_N| rowspan="2" |N24A17| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA4
|-
|ALT5J1.116|CSI_P1_DP2|CPU.MIPI_CSI_D2_P|B17| -|D|||GPIO2_IO06
|-
| rowspan="3" |J1.148(eMMC on board)118| rowspan="3" |NAND_DATA04CSI_P1_DN3| rowspan="3" |CPU.NAND_DATA04MIPI_CSI_D3_N| rowspan="3" |L20A18| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA04
|-
|ALT1J1.120|CSI_P1_DP3|CPU.MIPI_CSI_D3_P|B18| -|D|||QSPI_B_DATA0
|-
|ALT5J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO3_IO10
|-
| rowspan="2" |J1.150124
(NAND on board)
| rowspan="2" |SD1_DATA5NAND_DQS| rowspan="2" |CPU.SD1_DATA5NAND_DQS| rowspan="2" |P24R22| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" |Internally used for NAND, do not connect|ALT0|USDHC1_DATA5
|-
|ALT5|GPIO2_IO07|-| rowspan="3" |J1.150124
(eMMC on board)
| rowspan="3" |NAND_DATA05NAND_DQS| rowspan="3" |CPU.NAND_DATA05NAND_DQS| rowspan="3" |J22R22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA05RAWNAND_DQS
|-
|ALT1
|QSPI_B_DATA1QSPI_A_DQS
|-
|ALT5
|GPIO3_IO11GPIO3_IO14
|-
| rowspan="2" |J1.152126
(NAND on board)
| rowspan="2" |SD1_DATA6NAND_ALE| rowspan="2" |CPU.SD1_DATA6NAND_ALE| rowspan="2" |R25N22| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" |Internally used for NAND, do not connect|ALT0|USDHC1_DATA6
|-
|ALT5|GPIO2_IO08|-| rowspan="3" |J1.152126
(eMMC on board)
| rowspan="3" |NAND_DATA06NAND_ALE| rowspan="3" |CPU.NAND_DATA06NAND_ALE| rowspan="3" |L19N22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA06RAWNAND_ALE
|-
|ALT1
|QSPI_B_DATA2QSPI_A_SCLK
|-
|ALT5
|GPIO3_IO12GPIO3_IO00
|-
| rowspan="2" |J1.154128
(NAND on board)
| rowspan="2" |SD1_DATA7SD1_CLK| rowspan="2" |CPU.SD1_DATA7SD1_CLK| rowspan="2" |T25V26
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |
|ALT0
|USDHC1_DATA7USDHC1_CLK
|-
|ALT5
|GPIO2_IO09GPIO2_IO00
|-
| rowspan="3" |J1.154128
(eMMC on board)
| rowspan="3" |NAND_DATA07NAND_CE0_B| rowspan="3" |CPU.NAND_DATA07NAND_CE0_B| rowspan="3" |M19N24
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA07RAWNAND_CE0_B
|-
|ALT1
|QSPI_B_DATA3QSPI_A_SS0_B
|-
|ALT5
|GPIO3_IO13GPIO3_IO01
|-
| rowspan="2" |J1.156130
(NAND on board)
|NAND_RE_Browspan="2" |SD1_CMD| rowspan="2" |CPU.NAND_RE_BSD1_CMD|K19rowspan="2" |V27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|Internally used for NAND, do not connectrowspan="2" ||ALT0|USDHC1_CMD|-|ALT5|GPIO2_IO01
|-
| rowspan="34" |J1.156130
(eMMC on board)
| rowspan="34" |NAND_RE_BNAND_CE1_B| rowspan="34" |CPU.NAND_RE_BNAND_CE1_B| rowspan="34" |K19P27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_RE_BRAWNAND_CE1_B
|-
|ALT1
|QSPI_B_DQSQSPI_A_SS1_B|-|ALT2|USDHC3_STROBE
|-
|ALT5
|GPIO3_IO15GPIO3_IO02
|-
| rowspan="2" |J1.158132
(NAND on board)
|NAND_READY_B|CPU.NAND_READY_B|K20|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="2" |J1.158(eMMC on board)| rowspan="2" |NAND_READY_BSD1_RST_B| rowspan="2" |CPU.NAND_READY_BSD1_RST_B| rowspan="2" |K20R23
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_READY_BUSDHC1_RESET_B|-|ALT5|GPIO2_IO10|-| rowspan="4" |J1.132(eMMC on board)| rowspan="4" |NAND_CE2_B| rowspan="4" |CPU.NAND_CE2_B| rowspan="4" |M27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_CE2_B|-|ALT1|QSPI_B_SS0_B|-|ALT2|USDHC3_DATA5
|-
|ALT5
|GPIO3_IO16GPIO3_IO03
|-
| rowspan="2" |J1.160134
(NAND on board)
|NAND_WE_B|CPU.NAND_WE_B|K22|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="2" |J1.160(eMMC on board)| rowspan="2" |NAND_WE_BSD1_STROBE| rowspan="2" |CPU.NAND_WE_BSD1_STROBE| rowspan="2" |K22R24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WE_BUSDHC1_STROBE
|-
|ALT5
|GPIO3_IO17GPIO2_IO11|-| rowspan="4" |J1.134(eMMC on board)| rowspan="4" |NAND_CE3_B| rowspan="4" |CPU.NAND_CE3_B| rowspan="4" |L27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_CE3_B|-|ALT1|QSPI_B_SS1_B|-|ALT2|USDHC3_DATA6|-|ALT5|GPIO3_IO034
|-
|J1.162136
(NAND on board)
|NAND_WP_BNAND_CLE|CPU.NAND_WP_BNAND_CLE|K21K27
|NVCC_3V3
|I/O
|
|-
| rowspan="24" |J1.162136
(eMMC on board)
| rowspan="24" |NAND_WP_BNAND_CLE| rowspan="24" |CPU.NAND_WP_BNAND_CLE| rowspan="24" |K21K27| rowspan="24" |NVCC_3V3| rowspan="24" |I/O| rowspan="24" |
|ALT0
|RAWNAND_WP_BRAWNAND_CLE|-|ALT1|QSPI_B_SCLK
|-
|ALT5ALT2|GPIO3_IO18USDHC3_DATA7
|-
|J1.164|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO3_IO05
|-
| rowspan="2" |J1.166138(NAND on board)|CLK1_Nrowspan="2" |SD1_DATA0| rowspan="2" |CPU.CLK1_NSD1_DATA0|T23rowspan="2" |Y27|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA0
|-
|J1.168|CLK1_P|CPU.CLK1_P|R23||D||ALT5|GPIO2_IO02
|-
| rowspan="3" |J1.170138(eMMC on board)|USB2_RXNrowspan="3" |NAND_DATA00| rowspan="3" |CPU.USB2_RX_NNAND_DATA00|B8rowspan="3" |P23|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA00
|-
|J1.172|USB2_RXP|CPU.USB2_RX_P|A8||D||ALT1|QSPI_A_DATA0
|-
|J1.174|USB2_TXN|CPU.USB2_TX_N|B9||D||ALT5|GPIO3_IO06
|-
| rowspan="2" |J1.176140(NAND on board)|USB2_TXProwspan="2" |SD1_DATA1| rowspan="2" |CPU.USB2_TX_PSD1_DATA1| rowspan="2" |Y26|A9rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|DUSDHC1_DATA1|-|ALT5|GPIO2_IO0
|-
| rowspan="3" |J1.178140(eMMC on board)|USB1_RXNrowspan="3" |NAND_DATA01| rowspan="3" |CPU.USB1_RX_NNAND_DATA01|B12rowspan="3" |K24|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA01
|-
|J1.180|USB1_RXP|CPU.USB1_RX_P|A12||D||ALT1|QSPI_A_DATA1
|-
|ALT5|GPIO3_IO07|-| rowspan="2" |J1.142(NAND on board)| rowspan="2" |SD1_DATA2| rowspan="2" |CPU.SD1_DATA2| rowspan="2" |T27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA2|-|ALT5|GPIO2_IO04|-| rowspan="4" |J1.142(eMMC on board)| rowspan="4" |NAND_DATA02| rowspan="4" |CPU.NAND_DATA02| rowspan="4" |K23| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA02|-|ALT1|QSPI_A_DATA2|-|ALT2|USDHC3_CD_B(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO3_IO08|-| rowspan="2" |J1.144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |T26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="4" |J1.144(eMMC on board)| rowspan="4" |NAND_DATA03| rowspan="4" |CPU.NAND_DATA03| rowspan="4" |N23| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT2|USDHC3_WP(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO3_IO09|-|J1.146|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="2" |J1.148(NAND on board)| rowspan="2" |SD1_DATA4| rowspan="2" |CPU.SD1_DATA4| rowspan="2" |U27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4|-|ALT5|GPIO2_IO06|-| rowspan="4" |J1.148(eMMC on board)| rowspan="4" |NAND_DATA04| rowspan="4" |CPU.NAND_DATA04| rowspan="4" |M26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA04|-|ALT1|QSPI_B_DATA0|-|ALT2|USDHC3_DATA0|-|ALT5|GPIO3_IO10|-| rowspan="2" |J1.150(NAND on board)| rowspan="2" |SD1_DATA5| rowspan="2" |CPU.SD1_DATA5| rowspan="2" |U26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA5|-|ALT5|GPIO2_IO07|-| rowspan="4" |J1.150(eMMC on board)| rowspan="4" |NAND_DATA05| rowspan="4" |CPU.NAND_DATA05| rowspan="4" |L26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA05|-|ALT1|QSPI_B_DATA1|-|ALT2|USDHC3_DATA1|-|ALT5|GPIO3_IO11|-| rowspan="2" |J1.152(NAND on board)| rowspan="2" |SD1_DATA6| rowspan="2" |CPU.SD1_DATA6| rowspan="2" |W27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA6|-|ALT5|GPIO2_IO08|-| rowspan="4" |J1.152(eMMC on board)| rowspan="4" |NAND_DATA06| rowspan="4" |CPU.NAND_DATA06| rowspan="4" |K26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA06|-|ALT1|QSPI_B_DATA2|-|ALT2|USDHC3_DATA2|-|ALT5|GPIO3_IO12|-| rowspan="2" |J1.154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |W26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09|-| rowspan="4" |J1.154(eMMC on board)| rowspan="4" |NAND_DATA07| rowspan="4" |CPU.NAND_DATA07| rowspan="4" |N26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT2|USDHC3_DATA3|-|ALT5|GPIO3_IO13|-|J1.156(NAND on board)|NAND_RE_B|CPU.NAND_RE_B|N27|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="4" |J1.156(eMMC on board)| rowspan="4" |NAND_RE_B| rowspan="4" |CPU.NAND_RE_B| rowspan="4" |N27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_RE_B|-|ALT1|QSPI_B_DQS|-|ALT2|USDHC3_DATA4|-|ALT5|GPIO3_IO15|-|J1.158(NAND on board)|NAND_READY_B|CPU.NAND_READY_B|P26|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.158(eMMC on board)| rowspan="3" |NAND_READY_B| rowspan="3" |CPU.NAND_READY_B| rowspan="3" |P26| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_READY_B|-|ALT2|USDHC3_RESET_B|-|ALT5|GPIO3_IO16|-|J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|R26|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.160(eMMC on board)| rowspan="3" |NAND_WE_B| rowspan="3" |CPU.NAND_WE_B| rowspan="3" |R26| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_WE_B|-|ALT2|USDHC3_CLK|-|ALT5|GPIO3_IO17|-|J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|R27|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.162(eMMC on board)| rowspan="3" |NAND_WP_B| rowspan="3" |CPU.NAND_WP_B| rowspan="3" |R27| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_WP_B|-|ALT2|USDHC3_CMD|-|ALT5|GPIO3_IO18|-|J1.164|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="5" |J1.166| rowspan="5" |GPIO1_IO15| rowspan="5" |CPU.GPIO1_IO15| rowspan="5" |AB9| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|GPIO1_IO15|-|ALT1|USB2_OTG_OC|-|ALT4|USDHC3_WP(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT4)|-|ALT5|PWM4_OUT|-|ALT6|CCM_CLKO2|-| rowspan="4" |J1.168| rowspan="4" |GPIO1_IO07| rowspan="4" |CPU.GPIO1_IO07| rowspan="4" |AF11| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO07|-|ALT1|ENET1_MDIO(Configure register IOMUXC_ENET1_MDIO_SELECT_INPUT for mode ALT1)|-|ALT5|USDHC1_WP|-|ALT6|CCM_EXT_CLK4|-| rowspan="6" |J1.170| rowspan="6" |SAI1_TXD4| rowspan="6" |CPU.SAI1_TXD4| rowspan="6" |AG22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA4|-|ALT1|SAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_BCLK(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE12|-|ALT5|GPIO4_IO16|-|ALT6|SRC_BOOT_CFG12|-| rowspan="6" |J1.172| rowspan="6" |SAI1_TXD5| rowspan="6" |CPU.SAI1_TXD5| rowspan="6" |AF22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA5|-|ALT1|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT1)|-|ALT2|SAI6_TX_DATA0|-|ALT4|CORESIGHT_TRACE13|-|ALT5|GPIO4_IO17|-|ALT6|SRC_BOOT_CFG13|-| rowspan="6" |J1.174| rowspan="6" |SAI1_TXD6| rowspan="6" |CPU.SAI1_TXD6| rowspan="6" |AG23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA6|-|ALT1|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE14|-|ALT5|GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14|-| rowspan="6" |J1.176| rowspan="6" |SAI1_TXD7| rowspan="6" |CPU.SAI1_TXD7| rowspan="6" |AF23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT3|PDM_CLK|-|ALT4|CORESIGHT_TRACE15|-|ALT5|GPIO4_IO19|-|ALT6|SRC_BOOT_CFG15|-| rowspan="7" |J1.178| rowspan="7" |SAI1_RXD7| rowspan="7" |CPU.SAI1_RXD7| rowspan="7" |AF19| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI1_TX_DATA4|-|ALT4|CORESIGHT_TRACE7|-|ALT5|GPIO4_IO09|-|ALT6|SRC_BOOT_CFG7|-| rowspan="6" |J1.180| rowspan="6" |SAI1_RXD6| rowspan="6" |CPU.SAI1_RXD6| rowspan="6" |AG19| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA6|-|ALT1|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE6|-|ALT5|GPIO4_IO08|-|ALT6|SRC_BOOT_CFG6|-| rowspan="7" |J1.182|USB1_TXNrowspan="7" |SAI1_RXD5| rowspan="7" |CPU.USB1_TX_NSAI1_RXD5|B13rowspan="7" |AF18| rowspan="7" |NVCC_3V3|rowspan="7" |I/O|Drowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA5|-|ALT1|SAI6_TX_DATA0|-|ALT2|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT2)|-|ALT3|SAI1_RX_SYNC(Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT3)|-|ALT4|CORESIGHT_TRACE5|-|ALT5|GPIO4_IO07|-|ALT6|SRC_BOOT_CFG|-| rowspan="6" |J1.184|USB1_TXProwspan="6" |SAI1_RXD4| rowspan="6" |CPU.USB1_TX_PSAI1_RXD4| rowspan="6" |AG18| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA4|-|ALT1|SAI1_RX_DATA4(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT1)|A13-|ALT2|DSAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE4|-|ALT5|GPIO4_IO06|-|ALT6|SRC_BOOT_CFG4|-|J1.186|USB1_VBUS|CPU.USB1_VBUS|D14F22| -|S|Connected with 30K resistor on SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.188|USB2_VBUS|CPU.USB2_VBUS|D9F23| -|S|Connected with 30K resistor on SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.190|DGND|DGND| -|<nowiki>-</nowiki>|G|||
|-
|J1.192
|USB1_ID
|CPU.USB1_ID
|C14D22|VDD_PHY_3V3VDDA_1V8
|I
|
|USB2_ID
|CPU.USB2_ID
|C9D23|VDD_PHY_3V3VDDA_1V8
|I
|
|USB1_DN
|CPU.USB1_DN
|B14A22
| -
|D
|USB1_DP
|CPU.USB1_DP
|A14B22
| -
|D
|USB2_DP
|CPU.USB2_DP
|A10B23
| -
|D
|USB2_DN
|CPU.USB2_DN
|B10A23
| -
|D
|-
|}
'''(*)''' PMIC_PWRON can be used in two configuration: ''Embedded-like'' (default mounting option) or ''Tablet-like''. In the first case, the system reboots in case of PMIC_PWR_ON signal activity.
 
In the second case, the system will shut down waiting for a CPU_ONOFF signal raising (like a button-mode in a tablet) and the PMIC_PWRON Voltage domain is NVCC_SNVS_1V8
Please contact [mailto:sales@dave.eu sales dept.] for more information
----
[[Category:MITO 8M Mini]]
[[Category:MITO 8M Nano]]
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