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MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table

15,621 bytes added, 18:06, 27 December 2023
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=== Connectors description ===
In the following table are described all available connectors integrated on MITO 8M Mini/Nano SOM:
{| class="wikitable"
|-
|-
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini/Nano pinout specifications. See the images below for reference:
[[File:MITO_8M_Mini_MITO8M_Mini-_TOPconn-top.jpegpng|500px|thumb|MITO 8M Mini/Nano TOP view|none]][[File:MITO_8M_Mini_MITO8M_Mini-conn-_BOTTOMbottom.jpegpng|500px|thumb|MITO 8M Mini/Nano BOTTOM view|none]]
Below a detailed description of the pinout, grouped in the following tables:
|-
|'''Pin Name'''
| Pin (signal) name on the MITO 8M Mini connectors
|-
|'''Internal<br>connections'''
| Connections to the components
* CPU.<x> : pin connected to CPU pad named <x>(NXP iMX8MM)* PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210PF8121)
* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
|GPIO2_IO19
|-
| rowspan="4" |J1.101|HDMI_DDC_SCLrowspan="4" |I2C2_SCL| rowspan="4" |CPU.HDMI_DDC_SCLI2C2_SCL|rowspan="4" |D10|VDD_PHY_1V8rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|I2C2_SCL
|-
|J1.103|HDMI_DDC_SDA|CPU.HDMI_DDC_SDA||VDD_PHY_1V8|I/O||ALT1|ENET1_1588_EVENT1_IN
|-
|J1.105ALT2|HDMI_AUX_NUSDHC3_CD_B|CPU.HDMI_AUX_N|| -|D|connected with capacitor in series||(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)
|-
|J1.107|HDMI_AUX_P|CPU.HDMI_AUX_P|| -|D|connected with capacitor in series|ALT5|GPIO5_IO16
|-
| rowspan="4" |J1.109103|DGND rowspan="4" |I2C2_SDA|DGNDrowspan="4" |CPU.I2C2_SDA| -rowspan="4" |D9| -rowspan="4" |NVCC_3V3|Growspan="4" |I/O| rowspan="4" ||ALT0|I2C2_SDA
|-
|J1.111|HDMI_TX_M_LN_3|CPU.HDMI_TX_M_LN_3|| -|D|connected with capacitor in series|ALT1|ENET1_1588_EVENT1_OUT
|-
|J1.113ALT2|HDMI_TX_P_LN_3USDHC3_WP|CPU.HDMI_TX_P_LN_3|| -|D|connected with capacitor in series||(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)
|-
|J1.115|HDMI_TX_M_LN_0|CPU.HDMI_TX_M_LN_0|| -|D|connected with capacitor in series|ALT5|GPIO5_IO17
|-
| rowspan="6" |J1.117105|HDMI_TX_P_LN_0rowspan="6" |SAI1_RXD3| rowspan="6" |CPU.HDMI_TX_P_LN_0SAI1_RXD3| rowspan="6" |AF17| rowspan="6" | NVCC_3V3|rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on|D[[MITO 8M Mini SOM/Part number composition|connected with capacitor in seriesMITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA3
|-
|J1.119ALT1|HDMI_TX_M_LN_1SAI5_RX_DATA3|CPU.HDMI_TX_M_LN_1|| -|D|connected with capacitor in series||(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT1)
|-
|J1.121ALT3|HDMI_TX_P_LN_1PDM_BIT_STREAM3|CPU.HDMI_TX_P_LN_1|| -|D|connected with capacitor in series||(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT3)
|-
|J1.123|HDMI_TX_M_LN_2|CPU.HDMI_TX_M_LN_2|| -|D|connected with capacitor in series|ALT4|CORESIGHT_TRACE3
|-
|J1.125|HDMI_TX_P_LN_2|CPU.HDMI_TX_P_LN_2|| -|D|connected with capacitor in series|ALT5|GPIO4_IO05
|-
|J1.127|HDMI_CEC|CPU.HDMI_CEC||VDD_PHY_1V8|I/O||ALT6|SRC_BOOT_CFG3
|-
| rowspan="5" |J1.129107|HDMI_HPDrowspan="5" |SAI1_TXD3| rowspan="5" |CPU.HDMI_HPDSAI1_TXD3|rowspan="5" |AF21|VDD_PHY_1V8rowspan="5" | NVCC_3V3| rowspan="5" |I/O|rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA3|-|ALT1|SAI5_TX_DATA3|-|ALT4|CORESIGHT_TRACE11|-|ALT5|GPIO4_IO15|-|ALT6|SRC_BOOT_CFG11
|-
|J1.131109
|DGND
|DGND
|
|-
| rowspan="4" |J1.133111|LVDS0_CLK_Nrowspan="4" |SAI1_TXFS|BRIDGErowspan="4" |CPU.A_CLKNSAI1_TXFS|F9rowspan="4" |AB19| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_TX_SYNC (Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT0)
|-
|J1.135ALT1|LVDS0_CLK_PSAI5_TX_SYNC|BRIDGE.A_CLKP|F8| -|D|||(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
|-
|J1.137|LVDS0_TX0_N|BRIDGE.A_Y0N|C9| -|D||ALT4|CORESIGHT_EVENTO
|-
|J1.139|LVDS0_TX0_P|BRIDGE.A_Y0P|C8| -|D||ALT5|GPIO4_IO10
|-
| rowspan="4" |J1.141113|LVDS0_TX1_Nrowspan="4" |SAI1_TXC|BRIDGErowspan="4" |CPU.A_Y1NSAI1_TXC| rowspan="4" |AC18| rowspan="4" |NVCC_3V3|D9rowspan="4" |I/O| -rowspan="4" ||DALT0|SAI1_TX_BCLK (Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|J1.143|LVDS0_TX1_P|BRIDGE.A_Y1P|D8| -|D||ALT4|CORESIGHT_EVENTI
|-
|J1.145|LVDS0_TX2_N|BRIDGE.A_Y2N|E9| -|D||ALT5|GPIO4_IO11
|-
| rowspan="5" |J1.147115|LVDS0_TX2_Prowspan="5" |SAI1_TXD0|BRIDGErowspan="5" |CPU.A_Y2PSAI1_TXD0| rowspan="5" |AG20|E8rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|DMITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA0|-|ALT1|SAI5_TX_DATA0
|-
|J1.149|LVDS0_TX3_N|BRIDGE.A_Y3N|G9| -|D||ALT4|CORESIGHT_TRACE8
|-
|J1.151|LVDS0_TX3_P|BRIDGE.A_Y3P|G8| -|D||ALT5|GPIO4_IO12
|-
|J1.153|DGND |DGND| -| -|G||ALT6|SRC_BOOT_CFG8
|-
| rowspan="5" |J1.155117|LVDS1_CLK_Nrowspan="5" |SAI1_TXD1|BRIDGErowspan="5" |CPU.B_CLKNSAI1_TXD1| rowspan="5" |AF20| rowspan="5" |NVCC_3V3|A6rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on|D[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA1
|-
|J1.157|LVDS1_CLK_P|BRIDGE.B_CLKP|B6| -|D||ALT1|SAI5_TX_DATA1
|-
|J1.159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D||ALT4|CORESIGHT_TRACE9
|-
|J1.161|LVDS1_TX0_P|BRIDGE.B_Y0P|B3| -|D||ALT5|GPIO4_IO13
|-
|J1.163|LVDS1_TX1_N|BRIDGE.B_Y1N|A4| -|D||ALT6|SRC_BOOT_CFG9
|-
| rowspan="5" |J1.165119|LVDS1_TX1_Prowspan="5" |SAI1_TXD2|BRIDGErowspan="5" |CPU.B_Y1PSAI1_TXD2| rowspan="5" |AG21|B4rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|DMITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA2|-|ALT1|SAI5_TX_DATA2
|-
|J1.167|LVDS1_TX2_N|BRIDGE.B_Y2N|A5| -|D||ALT4|CORESIGHT_TRACE10
|-
|J1.169|LVDS1_TX2_P|BRIDGE.B_Y2P|B5| -|D||ALT5|GPIO4_IO14
|-
|ALT6|SRC_BOOT_CFG10|-| rowspan="4" |J1.171121|LVDS1_TX3_Nrowspan="4" |SAI1_RXFS|BRIDGErowspan="4" |CPU.B_Y3NSAI1_RXFS|A7rowspan="4" |AG16| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_SYNC (Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT0)
|-
|J1.173ALT1|LVDS1_TX3_PSAI5_RX_SYNC|BRIDGE.B_Y3P|B7| -|D|||(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT1)
|-
|J1.175|DGND |DGND| -| -|G||ALT4|CORESIGHT_TRACE_CLK
|-
|ALT5|GPIO4_IO00|-| rowspan="24" |J1.177123| rowspan="24" |SD2_CD_BSAI1_RXC| rowspan="24" |CPU.SD2_CD_BSAI1_RXC| rowspan="24" |AF16| rowspan="24" |NVCC_3V3| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC2_CD_BSAI1_RX_BCLK|-|ALT1|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT4|CORESIGHT_TRACE_CTL
|-
|ALT5
|GPIO2_IO12GPIO4_IO01
|-
| rowspan="37" |J1.179125| rowspan="37" |ECSPI1_SS0SAI1_RXD0| rowspan="37" |CPU.ECSPI1_SS0SAI1_RXD0| rowspan="37" |AG15| rowspan="37" |NVCC_3V3| rowspan="37" |I/O| rowspan="37" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|ECSPI1_SS0SAI1_RX_DATA0
|-
|ALT1
|UART3_RTS_BSAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT1)
|-
|ALT5ALT2|GPIO5_IO09SAI1_TX_DATA1
|-
| rowspan="3" |J1.181| rowspan="3" |ECSPI1_SCLK| rowspan="3" |CPU.ECSPI1_SCLK| rowspan="3" || rowspan="3" |NVCC_3V3| rowspan="3" |I/OALT3| rowspan="3" |PDM_BIT_STREAM0|ALT0|ECSPI1_SCLK(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT3)
|-
|ALT1ALT4|UART3_RXCORESIGHT_TRACE0
|-
|ALT5
|GPIO5_IO06GPIO4_IO02|-|ALT6|SRC_BOOT_CFG0
|-
| rowspan="36" |J1.183127| rowspan="36" |ECSPI1_MISOSAI1_RXD1| rowspan="36" |CPU.ECSPI1_MISOSAI1_RXD1| rowspan="36" |AF15| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|ECSPI1_MISOSAI1_RX_DATA1
|-
|ALT1
|UART3_CTS_BSAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT1)
|-
|ALT5ALT3|GPIO5_IO08PDM_BIT_STREAM1(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT3)
|-
| rowspan="3" |J1.185| rowspan="3" |GPIO1_IO03| rowspan="3" |CPU.GPIO1_IO03| rowspan="3" || rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0ALT4|GPIO1_IO03CORESIGHT_TRACE1
|-
|ALT1ALT5|USDHC1_VSELECTGPIO4_IO03
|-
|ALT5ALT6|SDMA1_EXT_EVENT0SRC_BOOT_CFG1
|-
| rowspan="36" |J1.187129| rowspan="36" |UART2_TXDSAI1_RXD2| rowspan="36" |CPU.UART2_TXDSAI1_RXD2| rowspan="36" |AG17| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |Internally used as default Linux consolefor BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|UART2_TXSAI1_RX_DATA2
|-
|ALT1
|ECSPI3_SS0SAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT1)|-|ALT3|PDM_BIT_STREAM2(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT3)|-|ALT4|CORESIGHT_TRACE2
|-
|ALT5
|GPIO5_IO25GPIO4_IO04
|-
| rowspan="3" |J1.189| rowspan="3" |UART2_RXD| rowspan="3" |CPU.UART2_RXD| rowspan="3" || rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |used as default Linux console|ALT0ALT6|UART2_RXDSRC_BOOT_CFG2
|-
|ALT1J1.131|DGND |DGND| -| -|G|||ECSPI3_MISO
|-
|ALT5J1.133|LVDS0_CLK_N|BRIDGE.A_CLKN|F9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO24
|-
| rowspan="3" |J1.191133| rowspan="3" |UART1_TXDDSI_CLK_N| rowspan="3" |CPU.UART1_TXDMIPI_DSI_CLK_N| rowspan="3" A11|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|UART1_TX
|-
|ALT1J1.135|LVDS0_CLK_P|BRIDGE.A_CLKP|F8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_MOSI
|-
|ALT5J1.135|DSI_CLK_P|CPU.MIPI_|B11| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO23
|-
| rowspan="3" |J1.193137| rowspan="3" |UART1_RXDLVDS0_TX0_N| rowspan="3" |CPUBRIDGE.UART1_RXDA_Y0N| rowspan="3" C9|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|UART1_RXD
|-
|ALT1J1.137|DSI_D0_N|CPU.MIPI_DSI_D0_N|A9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_SCLK
|-
|ALT5J1.139|LVDS0_TX0_P|BRIDGE.A_Y0P|C8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO22
|-
| rowspan="3" |J1.195139| rowspan="3" |ECSPI1_MOSIDSI_D0_P| rowspan="3" |CPU.ECSPI1_MOSIMIPI_DSI_D0_P| rowspan="3" B9|-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|ECSPI1_MOSI
|-
|ALT1J1.141|LVDS0_TX1_N|BRIDGE.A_Y1N|D9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||UART3_TX
|-
|ALT5J1.141|DSI_D1_N|CPU.MIPI_DSI_D1_N|A10| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO07
|-
| rowspan="4" |J1.197143| rowspan="4" |GPIO1_IO14LVDS0_TX1_P| rowspan="4" |CPUBRIDGE.GPIO1_IO14A_Y1P| rowspan="4" D8|-| rowspan="4" |NVCC_3V3D| rowspan="4" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="4" |N composition]]|ALT0|GPIO1_IO14
|-
|ALT1J1.143|DSI_D1_P|CPU.MIPI_DSI_D1_P|B10| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||USB2_OTG_PWR
|-
|ALT5J1.145|LVDS0_TX2_N|BRIDGE.A_Y2N|E9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||PWM3_OUT
|-
|ALT6J1.145|DSI_D2_N|CPU.MIPI_DSI_D2_N|A12| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||CCM_CLKO1
|-
| rowspan="3" |J1.199147| rowspan="3" |GPIO1_IO04LVDS0_TX2_P| rowspan="3" |CPUBRIDGE.GPIO1_IO04| rowspan="3" || rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO04|-|ALT1|USDHC2_VSELECT|-|ALT5|SDMA1_EXT_EVENT1|-| rowspan="3" |J1.201| rowspan="3" |GPIO1_IO12| rowspan="3" |CPU.GPIO1_IO12| rowspan="3" || rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO12|-|ALT1|USB1_OTG_PWR|-|ALT5|SDMA2_EXT_EVENT1|-|J1.203|DGND A_Y2P|DGNDE8
| -
| -D|GDepending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|} ==SODIMM J1 EVEN pins declaration ==.147 {| class="wikitable" DSI_D2_P! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" | Alternative Functions|-|J1CPU.2|DGNDMIPI_DSI_D2_P|DGNDB12
| -
|<nowiki>-</nowiki>D|GDepending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.4149|3LVDS0_TX3_N|BRIDGE.3VIN A_Y3N|INPUT VOLTAGEG9
| -
|3.3VIND|SDepending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.6149|3DSI_D3_N|CPU.3VIN MIPI_DSI_D3_N|INPUT VOLTAGEA13
| -
|3.3VIND|SDepending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.8151|3LVDS0_TX3_P|BRIDGE.3VIN A_Y3P|INPUT VOLTAGEG8
| -
|3.3VIND|SDepending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.10151|3DSI_D3_P|CPU.3VIN MIPI_DSI_D3_P|INPUT VOLTAGEB13
| -
|3.3VIND|SDepending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.12153|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
|J1.14155|PMIC_LICELL LVDS1_CLK_N|PMICBRIDGE.LICELLB_CLKN|30A6
| -
|SD
|
|
|
|-
|J1.16157|CPU_ONOFFLVDS1_CLK_P|CPUBRIDGE.ONOFFB_CLKP|W21B6|NVCC_SNVS-|ID|internal pull-up 100k to NVCC_SNVS
|
|
|-
|J1.18159|BOARD_PGOODLVDS1_TX0_N|BRIDGE.B_Y0N|A3
| -
| -|NVCC_3V3|OD
|
|
|
|-
|J1.20161|BOOT_MODE_SELLVDS1_TX0_P|BOOT MODE SELECTIONBRIDGE.B_Y0P|B3
| -
|NVCC_3V3D|I|internal pull-up to NVCC_3V3
|
|
|-
|J1.22163|CPU_PORnLVDS1_TX1_N|CPUBRIDGE.POR_BPMIC.RESETMCUB_Y1N|W203A4|NVCC_SNVS-|I/OD|internal pull-up 100k to NVCC_SNVS
|
|
|-
|J1.24165|EXT_RESETLVDS1_TX1_P|MASTER RESETBRIDGE.B_Y1P|B4
| -
|D
|
|
|
|-
|J1.167
|LVDS1_TX2_N
|BRIDGE.B_Y2N
|A5
| -
|ID|internal pull-up to NVCC_SNVS
|
|
|-
| rowspan="4" |J1.26169| rowspan="4" |SAI3_RXCLVDS1_TX2_P| rowspan="4" |CPUBRIDGE.SAI3_RXCB_Y2P| rowspan="4" |F4B5| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI3_RX_BCLK
|-
|ALT1J1.171|LVDS1_TX3_N|BRIDGE.B_Y3N|A7| -|D|||GPT1_CAPTURE2
|-
|ALT2J1.173|LVDS1_TX3_P|BRIDGE.B_Y3P|B7| -|D|||SAI5_RX_BCLK
|-
|ALT5|GPIO4_IO29|-| rowspan="4" |J1.28| rowspan="4" |GPIO1_IO02| rowspan="4" |CPU.GPIO1_IO02| rowspan="4" |R4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" |Internally used for SW reset, do not connect|ALT0|GPIO1_IO02|-|ALT1|WDOG1_WDOG_B|-|ALT5|WDOG1_WDOG_ANY|-|ALT7|SJC_DE_B|-|J1.30175|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|-
| rowspan="42" |J1.32177| rowspan="42" |SAI3_RXDSD2_CD_B| rowspan="42" |CPU.SAI3_RXDSD2_CD_B| rowspan="42" |F3AA26| rowspan="42" |NVCC_3V3| rowspan="42" |I/O| rowspan="42" |
|ALT0
|SAI3_RX_DATA0|-|ALT1|GPT1_COMPARE1|-|ALT2|SAI5_RX_DATA0USDHC2_CD_B
|-
|ALT5
|GPIO4_IO30GPIO2_IO12
|-
| rowspan="3" |J1.34179| rowspan="3" |SAI2_MCLKECSPI1_SS0| rowspan="3" |CPU.SAI2_MCLKECSPI1_SS0| rowspan="3" |H5B6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_MCLKECSPI1_SS0
|-
|ALT1
|SAI5_MCLKUART3_RTS_B(Configure register IOMUXC_UART3_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO4_IO27GPIO5_IO09
|-
| rowspan="43" |J1.36181| rowspan="43" |SAI3_RXFSECSPI1_SCLK| rowspan="43" |CPU.SAI3_RXFSECSPI1_SCLK| rowspan="43" |G4D6| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_RX_SYNCECSPI1_SCLK
|-
|ALT1
|GPT1_CAPTURE1|-|ALT2|SAI5_RX_SYNCUART3_RX
|-
|ALT5
|GPIO4_IO28GPIO5_IO06
|-
| rowspan="43" |J1.38183| rowspan="43" |I2C3_SCLECSPI1_MISO| rowspan="43" |CPU.I2C3_SCLECSPI1_MISO| rowspan="43" |G8A7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C3_SCLECSPI1_MISO
|-
|ALT1
|PWM4_OUT|-|ALT2|GPT2_CLKUART3_CTS_B
|-
|ALT5
|GPIO5_IO18GPIO5_IO08
|-
| rowspan="43" |J1.40185| rowspan="43" |SAI3_TXFSGPIO1_IO03| rowspan="43" |CPU.SAI3_TXFSGPIO1_IO03| rowspan="43" |G3AF13| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |Internally used for PMIC interrupt, do not connect Pulled-up to NVCC_3V3|ALT0|SAI3_TX_SYNCGPIO1_IO03
|-
|ALT1
|GPT1_CLK|-|ALT2|SAI5_RX_DATA1USDHC1_VSELECT
|-
|ALT5
|GPIO4_IO31SDMA1_EXT_EVENT0
|-
| rowspan="3" |J1.42187| rowspan="3" |SPDIF_RXUART2_TXD| rowspan="3" |CPU.SPDIF_RXUART2_TXD| rowspan="3" |G6E15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|SPDIF1_INUART2_TX
|-
|ALT1
|PWM2_OUTECSPI3_SS0
|-
|ALT5
|GPIO5_IO04GPIO5_IO25
|-
| rowspan="3" |J1.44189| rowspan="3" |SPDIF_TXUART2_RXD| rowspan="3" |CPU.SPDIF_TXUART2_RXD| rowspan="3" |F6F15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|SPDIF1_OUTUART2_RXD
|-
|ALT1
|PWM3_OUTECSPI3_MISO
|-
|ALT5
|GPIO5_IO03GPIO5_IO24
|-
| rowspan="43" |J1.46191| rowspan="43" |SAI3_MCLKUART4_TXD| rowspan="43" |CPU.SAI3_MCLKUART4_TXD| rowspan="43" |D3F18| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_MCLKUART4_TX
|-
|ALT1
|PWM4_OUTUART2_RTS_B|-|ALT2|SAI5_MCLK(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO5_IO02GPIO5_IO29
|-
| rowspan="4" |J1.48193| rowspan="4" |I2C3_SDAUART4_RXD| rowspan="4" |CPU.I2C3_SDAUART4_RXD| rowspan="4" |E9F19
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C3_SDAUART4_RX
|-
|ALT1
|PWM3_OUTUART2_CTS_B
|-
|ALT2
|GPT3_CLKPCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO5_IO19GPIO5_IO28
|-
| rowspan="43" |J1.50195| rowspan="43" |SAI3_TXCECSPI1_MOSI| rowspan="43" |CPU.SAI3_TXCECSPI1_MOSI| rowspan="43" |C4B7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_TX_BCLKECSPI1_MOSI
|-
|ALT1
|GPT1_COMPARE2|-|ALT2|SAI5_RX_DATA2UART3_TX
|-
|ALT5
|GPIO5_IO00GPIO5_IO07
|-
| rowspan="45" |J1.52197| rowspan="45" |SAI3_TXDGPIO1_IO14| rowspan="45" |CPU.SAI3_TXDGPIO1_IO14| rowspan="45" |C3AC9| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |
|ALT0
|SAI3_TX_DATA0GPIO1_IO14
|-
|ALT1
|GPT1_COMPARE3USB2_OTG_PWR
|-
|ALT2ALT4|SAI5_RX_DATA3USDHC3_CD_B(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|GPIO5_IO01PWM3_OUT
|-
| rowspan="2" |J1.54| rowspan="2" |GPIO1_IO10| rowspan="2" |CPU.GPIO1_IO10| rowspan="2" |M7| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0ALT6|GPIO1_IO10CCM_CLKO1
|-
|ALT1|USB1_OTG_ID|-|J1.56|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="43" |J1.58199| rowspan="43" |SAI5_MCLKGPIO1_IO04| rowspan="43" |CPU.SAI5_MCLKGPIO1_IO04| rowspan="43" |K4AG12| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI5_MCLKGPIO1_IO04
|-
|ALT1
|SAI1_TX_BCLK|-|ALT2|SAI4_MCLKUSDHC2_VSELECT
|-
|ALT5
|GPIO3_IO25SDMA1_EXT_EVENT1
|-
| rowspan="4" |J1.60| rowspan="4" |GPIO1_IO15| rowspan="4" |CPU.GPIO1_IO15| rowspan="4" |J6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO15|-|ALT1|USB2_OTG_OC|-|ALT5|PWM4_OUT|-|ALT6|CCM_CLKO2|-| rowspan="3" |J1.62201| rowspan="3" |SAI5_RXFSGPIO1_IO12| rowspan="3" |CPU.SAI5_RXFSGPIO1_IO12| rowspan="3" |N4AB10
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI5_RX_SYNCGPIO1_IO12
|-
|ALT1
|SAI1_TX_DATA0USB1_OTG_PWR
|-
|ALT5
|GPIO3_IO19SDMA2_EXT_EVENT1
|-
| rowspan="3" |J1.64203| rowspan="3" |SAI5_RXCDGND | rowspan="3" |CPU.SAI5_RXCDGND| rowspan="3" |L5-| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OG| rowspan="3" ||ALT0|SAI5_RX_BCLK
|-
|ALT1} ==SODIMM J1 EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" |SAI1_TX_DATA1Alternative Functions
|-
|ALT5J1.2|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO3_IO20
|-
| rowspan="3" |J1.664| rowspan="3" |SAI2_TXC.3VIN | rowspan="3" |CPU.SAI2_TXCINPUT VOLTAGE| rowspan="3" |J5-| rowspan="3" |NVCC_3V3.3VIN| rowspan="3" |I/OS| rowspan="3" ||ALT0|SAI2_TX_BCLK
|-
|ALT1J1.6|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||SAI5_TX_DATA2
|-
|ALT5|GPIO4_IO25|-| rowspan="3" |J1.688| rowspan="3" |SAI2_TXD0.3VIN | rowspan="3" |CPU.SAI2_TXD0INPUT VOLTAGE| rowspan="3" |G5-| rowspan="3" |NVCC_3V3.3VIN| rowspan="3" |I/OS| rowspan="3" ||ALT0|SAI2_TX_DATA0
|-
|ALT1J1.10|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||SAI5_TX_DATA3
|-
|ALT5J1.12|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO4_IO26
|-
| rowspan="3" |J1.7014| rowspan="3" |SAI2_TXFSPMIC_LICELL | rowspan="3" |CPUPMIC.SAI2_TXFSLICELL| rowspan="3" |H446| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OS| rowspan="3" ||ALT0|SAI2_TX_SYNC
|-
|ALT1J1.16|CPU_ONOFF|CPU.ONOFF|A25|NVCC_SNVS_1V8|I|internal pull-up 100k to NVCC_SNVS_1V8||SAI5_TX_DATA1
|-
|ALT5J1.18|BOARD_PGOOD| -| -|NVCC_3V3|O|||GPIO4_IO24
|-
| rowspan="3" |J1.7220| rowspan="3" |SAI2_RXD0BOOT_MODE_SEL| rowspan="3" |CPU.SAI2_RXD0BOOT MODE SELECTION| rowspan="3" |H6-| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |internal pull-up to NVCC_3V3|ALT0|SAI2_RX_DATA0
|-
|ALT1J1.22|CPU_PORn|CPU.POR_BPMIC.RESET_MCU|B2421|NVCC_SNVS_1V8|I/O|internal pull-up 100k to NVCC_SNVS_1V8||SAI5_TX_DATA0
|-
|ALT5J1.24|PMIC_PWRON|PMIC.PWRON| 22| '''(*)''' 3.3VIN|I|internal pull-up 100k to VIN'''(*)''' default as ''Embedded'' power mode||GPIO4_IO23
|-
| rowspan="35" |J1.7426| rowspan="35" |SAI5_RXD0SAI3_RXC| rowspan="35" |CPU.SAI5_RXD0SAI3_RXC| rowspan="35" |M5AG7| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|SAI5_RX_DATA0 SAI3_RX_BCLK
|-
|ALT1
|SAI1_TX_DATA2GPT1_CLK
|-
|ALT5ALT2|GPIO3_IO21SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2)
|-
| rowspan="5" |J1.76| rowspan="5" |SAI5_RXD1| rowspan="5" |CPU.SAI5_RXD1| rowspan="5" |L4| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI5_RX_DATA1|-|ALT1|SAI1_TX_DATA3|-|ALT2|SAI1_TX_SYNC|-|ALT3ALT4|SAI5_TX_SYNCUART2_CTS_B
|-
|ALT5
|GPIO3_IO212GPIO4_IO29
|-
| rowspan="54" |J1.7828| rowspan="54" |SAI5_RXD2GPIO1_IO02| rowspan="54" |CPU.SAI5_RXD2GPIO1_IO02| rowspan="54" |M4AG13| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |Internally used for PMIC WDI, do not connect
|ALT0
|SAI5_RX_DATA2GPIO1_IO02
|-
|ALT1
|SAI1_TX_DATA4WDOG1_WDOG_B
|-
|ALT2ALT5|SAI1_TX_SYNCWDOG1_WDOG_ANY
|-
|ALT3ALT7|SAI5_TX_BCLKSJC_DE_B
|-
|ALT5J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO3_IO23
|-
| rowspan="5" |J1.8032| rowspan="5" |SAI5_RXD3SAI3_RXD| rowspan="5" |CPU.SAI5_RXD3SAI3_RXD| rowspan="5" |K5AF7
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
|ALT0
|SAI5_RX_DATA3SAI3_RX_DATA0
|-
|ALT1
|SAI1_TX_DATA5GPT1_COMPARE1
|-
|ALT2
|SAI1_TX_SYNCSAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT2)
|-
|ALT3ALT4|SAI5_TX_DATA0UART2_RTS_B(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|GPIO3_IO24GPIO4_IO30
|-
| rowspan="3" |J1.8234|DGNDrowspan="3" |SAI2_MCLK| rowspan="3" |CPU.SAI2_MCLK|DGNDrowspan="3" |AD19| -rowspan="3" |NVCC_3V3|<nowiki>-<rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|SAI2_MCLK
|-
|J1.84ALT1|CLK2_NSAI5_MCLK|CPU.CLK2_N|T22|VDDA_1V8|D|Internally used (Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for PCIe CLK, do not connect||mode ALT1)
|-
|J1.86|CLK2_P|CPU.CLK2_P|U22|VDDA_1V8|D|Internally used for PCIe CLK, do not connect|ALT5|GPIO4_IO27
|-
| rowspan="5" |J1.8836|PCIE1_REF_CLKNrowspan="5" |SAI3_RXFS| rowspan="5" |CPU.PCIE1_REF_PAD_CLK_NSAI3_RXFS|K24rowspan="5" |AG8|VDD_PHY_3V3rowspan="5" |NVCC_3V3|Drowspan="5" |I/O| rowspan="5" ||ALT0|SAI3_RX_SYNC
|-
|J1.90|PCIE1_REF_CLKP|CPU.PCIE1_REF_PAD_CLK_P|K25|VDD_PHY_3V3|D||ALT1|GPT1_CAPTURE1
|-
|J1.92ALT2|PCIE1_RXNSAI5_RX_SYNC|CPU.PCIE1_RXN_N|H24|VDD_PHY_3V3|D|||(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT2)
|-
|J1.94|PCIE1_RXP|CPU.PCIE1_RXN_P|H25|VDD_PHY_3V3|D||ALT3|SAI3_RX_DATA1
|-
|J1.96|PCIE1_TXN|CPU.PCIE1_TXN_N|J24|VDD_PHY_3V3|D||ALT5|GPIO4_IO28
|-
| rowspan="4" |J1.9838|PCIE1_TXProwspan="4" |I2C3_SCL| rowspan="4" |CPU.PCIE1_TXN_PI2C3_SCL|J25rowspan="4" |E10| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||VDD_PHY_3V3ALT0|DI2C3_SCL|-|ALT1|PWM4_OUT
|-
|J1.100|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT2|GPT2_CLK
|-
|J1.102|CSI1_CLK_N|CPU.MIPI_CSI1_CLK_N|A22| -|D||ALT5|GPIO5_IO18
|-
| rowspan="6" |J1.10440|CSI1_CLK_Prowspan="6" |SAI3_TXFS| rowspan="6" |CPU.MIPI_CSI1_CLK_PSAI3_TXFS| rowspan="6" |AC6|B22rowspan="6" |NVCC_3V3| -rowspan="6" |I/O| rowspan="6" ||ALT0|DSAI3_TX_SYNC|-|ALT1|GPT1_CAPTURE2
|-
|J1.106ALT2|CSI1_D0_NSAI5_RX_DATA1|CPU.MIPI_CSI1_D0_N|A23| -|D|||(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT2)
|-
|J1.108|CSI1_D0_P|CPU.MIPI_CSI1_D0_P|B23| -|D||ALT3|SAI3_TX_DATA1
|-
|J1.110|CSI1_D1_N|CPU.MIPI_CSI1_D1_N|C22| -|D||ALT4|UART2_RX
|-
|J1.112|CSI1_D1_P|CPU.MIPI_CSI1_D1_P|D22| -|D||ALT5|GPIO4_IO31
|-
| rowspan="3" |J1.11442|CSI1_D2_Nrowspan="3" |SPDIF_RX| rowspan="3" |CPU.MIPI_CSI1_D2_NSPDIF_RX|B24rowspan="3" |AG9| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SPDIF1_IN
|-
|J1.116|CSI1_D2_P|CPU.MIPI_CSI1_D2_P|C23| -|D||ALT1|PWM2_OUT
|-
|ALT5|GPIO5_IO04|-| rowspan="3" |J1.11844|CSI1_D3_Nrowspan="3" |SPDIF_TX| rowspan="3" |CPU.MIPI_CSI1_D3_NSPDIF_TX|C21rowspan="3" |AF9| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SPDIF1_OUT
|-
|J1.120|CSI1_D3_P|CPU.MIPI_CSI1_D3_P|D21| -|D||ALT1|PWM3_OUT
|-
|J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO5_IO03
|-
|J1.124(NAND on board)|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="34" |J1.124(eMMC on board)46| rowspan="34" |NAND_DQSSAI3_MCLK| rowspan="34" |CPU.NAND_DQSSAI3_MCLK| rowspan="34" |M20AD6| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_DQSSAI3_MCLK
|-
|ALT1
|QSPI_A_DQSPWM4_OUT|-|ALT2|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO3_IO14GPIO5_IO02
|-
|J1.126(NAND on board)|NAND_ALE|CPU.NAND_ALE|G19|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="34" |J1.126(eMMC on board)48| rowspan="34" |NAND_ALEI2C3_SDA| rowspan="34" |CPU.NAND_ALEI2C3_SDA| rowspan="34" |G19F10| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_ALEI2C3_SDA
|-
|ALT1
|QSPI_A_SCLKPWM3_OUT|-|ALT2|GPT3_CLK
|-
|ALT5
|GPIO3_IO00GPIO5_IO19
|-
| rowspan="25" |J1.128(NAND on board)50| rowspan="25" |SD1_CLKSAI3_TXC| rowspan="25" |CPU.SD1_CLKSAI3_TXC| rowspan="25" |L25AG6| rowspan="25" |NVCC_3V3(NVCC_1V8 on request)| rowspan="25" |I/O| rowspan="25" ||ALT0|USDHC1_CLKSAI3_TX_BCLK|-|ALT1|GPT1_COMPARE2|-|ALT2|SAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT2)|-|ALT4|UART2_TX
|-
|ALT5
|GPIO2_IO00GPIO5_IO00
|-
| rowspan="34" |J1.128(eMMC on board)52| rowspan="34" |NAND_CE0_BSAI3_TXD| rowspan="34" |CPU.NAND_CE0_BSAI3_TXD| rowspan="34" |H19AF6| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_CE0_BSAI3_TX_DATA0
|-
|ALT1
|QSPI_A_SS0_BGPT1_COMPARE3|-|ALT2|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT2)
|-
|ALT5
|GPIO3_IO01GPIO5_IO01
|-
| rowspan="25" |J1.130(NAND on board)54| rowspan="25" |SD1_CMDSAI1_MCLK| rowspan="25" |CPU.SD1_CMDSAI1_MCLK| rowspan="25" |L24AB18| rowspan="25" |NVCC_3V3(NVCC_1V8 on request)| rowspan="25" |I/O| rowspan="25" |
|ALT0
|USDHC1_CMDSAI1_MCLK
|-
|ALT5ALT1|GPIO2_IO01SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)
|-
| rowspan="3" ALT2|J1.130SAI1_TX_BCLK(eMMC on boardConfigure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT2)| rowspan="3" |NAND_CE1_B| rowspan="3" |CPU.NAND_CE1_B| rowspan="3" |G21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE1_B
|-
|ALT1ALT3|QSPI_A_SS1_BPDM_CLK
|-
|ALT5
|GPIO3_IO02GPIO4_IO20
|-
| rowspan="2" |J1.132(NAND on board)| rowspan="2" |SD1_RST_B56| rowspan="2" |CPU.SD1_RST_BDGND| rowspan="2" |R24DGND| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I<nowiki>-</Onowiki>| rowspan="2" G||ALT0|USDHC1_RESET_B
|-
|ALT5|GPIO2_IO10|-| rowspan="3" |J1.132(eMMC on board)58| rowspan="3" |NAND_CE2_BSAI5_MCLK| rowspan="3" |CPU.NAND_CE2_BSAI5_MCLK| rowspan="3" |F21AD15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE2_BSAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT0)
|-
|ALT1
|QSPI_B_SS0_BSAI1_TX_BCLK(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO3_IO03GPIO3_IO25
|-
| rowspan="2" |J1.134(NAND on board)60| rowspan="2" |SD1_STROBEGPIO1_IO10| rowspan="2" |CPU.SD1_STROBEGPIO1_IO10| rowspan="2" |T24AD10
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |Internally used for ETH PHY interrupt, do not connect
|ALT0
|USDHC1_STROBEGPIO1_IO10
|-
|ALT5ALT1|GPIO2_IO11USB1_OTG_ID
|-
| rowspan="3" |J1.134(eMMC on board)62| rowspan="3" |NAND_CE3_BSAI5_RXFS| rowspan="3" |CPU.NAND_CE3_BSAI5_RXFS| rowspan="3" |H20AB15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE3_BSAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT0)
|-
|ALT1
|QSPI_B_SS1_BSAI1_TX_DATA0
|-
|ALT5
|GPIO3_IO034GPIO3_IO19
|-
| rowspan="4" |J1.13664(NAND on board)| rowspan="4" |SAI5_RXC|NAND_CLErowspan="4" |CPU.NAND_CLESAI5_RXC|H21rowspan="4" |AC15| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|Internally used for NAND, do not connectrowspan="4" ||ALT0|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT0)
|-
| rowspan="3" |J1.136(eMMC on board)| rowspan="3" |NAND_CLE| rowspan="3" |CPU.NAND_CLE| rowspan="3" |H21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0ALT1|RAWNAND_CLESAI1_TX_DATA1
|-
|ALT1ALT4|QSPI_B_SCLKPDM_CLK
|-
|ALT5
|GPIO3_IO05GPIO3_IO20
|-
| rowspan="2" |J1.138(NAND on board)| rowspan="2" |SD1_DATA0| rowspan="2" |CPU.SD1_DATA0| rowspan="2" |M25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA0|-|ALT5|GPIO2_IO02|-| rowspan="3" |J1.138(eMMC on board)66| rowspan="3" |NAND_DATA00SAI2_TXC| rowspan="3" |CPU.NAND_DATA00SAI2_TXC| rowspan="3" |G20AD22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA00SAI2_TX_BCLK
|-
|ALT1
|QSPI_A_DATA0SAI5_TX_DATA2
|-
|ALT5
|GPIO3_IO06GPIO4_IO25
|-
| rowspan="2" |J1.140(NAND on board)| rowspan="2" |SD1_DATA1| rowspan="2" |CPU.SD1_DATA1| rowspan="2" |M24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA1|-|ALT5|GPIO2_IO0|-| rowspan="3" |J1.140(eMMC on board)68| rowspan="3" |NAND_DATA01SAI2_TXD0| rowspan="3" |CPU.NAND_DATA01SAI2_TXD0| rowspan="3" |J20AC22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA01SAI2_TX_DATA0
|-
|ALT1
|QSPI_A_DATA1SAI5_TX_DATA3
|-
|ALT5
|GPIO3_IO07GPIO4_IO26
|-
| rowspan="25" |J1.14270(NAND on board)| rowspan="5" |SAI2_TXFS| rowspan="5" |CPU.SAI2_TXFS| rowspan="5" |AD23| rowspan="25" |SD1_DATA2NVCC_3V3| rowspan="5" |I/O| rowspan="25" ||ALT0|SAI2_TX_SYNC|-|ALT1|SAI5_TX_DATA1|-|ALT3|SAI2_TX_DATA1|-|ALT4|UART1_CTS_B|-|ALT5|GPIO4_IO24|-| rowspan="4" |J1.72| rowspan="4" |SAI2_RXD0| rowspan="4" |CPU.SD1_DATA2SAI2_RXD0| rowspan="24" |N25AC24| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_DATA2SAI2_RX_DATA0|-|ALT1|SAI5_TX_DATA0|-|ALT4|UART1_RTS_B(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|GPIO2_IO04GPIO4_IO23
|-
| rowspan="3" |J1.142(eMMC on board)74| rowspan="3" |NAND_DATA02I2C4_SDA| rowspan="3" |CPU.NAND_DATA02I2C4_SDA| rowspan="3" |H22E13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA02I2C4_SDA
|-
|ALT1
|QSPI_A_DATA2PWM1_OUT
|-
|ALT5
|GPIO3_IO08GPIO5_IO21
|-
| rowspan="24" |J1.144(NAND on board)76| rowspan="24" |SD1_DATA3I2C4_SCL| rowspan="24" |CPU.SD1_DATA3I2C4_SCL| rowspan="24" |P25D13| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_DATA3I2C4_SCL|-|ALT1|PWM2_OUT|-|ALT2|PCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO2_IO05GPIO5_IO20
|-
| rowspan="36" |J1.144(eMMC on board)78| rowspan="36" |NAND_DATA03SAI5_RXD2| rowspan="36" |CPU.NAND_DATA03SAI5_RXD2| rowspan="36" |J21AD13| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|RAWNAND_DATA03SAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT0)
|-
|ALT1
|QSPI_A_DATA3SAI1_TX_DATA4
|-
|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT3)|-|ALT4|PDM_BIT_STREAM2(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT4)|-|ALT5|GPIO3_IO09GPIO3_IO23
|-
| rowspan="6" |J1.14680| rowspan="6" |SAI5_RXD3| rowspan="6" |CPU.SAI5_RXD3| rowspan="6" |AC13| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" ||ALT0|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT0)|-|ALT1|SAI1_TX_DATA5|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI5_TX_DATA0|-|ALT4|PDM_BIT_STREAM3(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT4)|-|ALT5|GPIO3_IO24|-|J1.82
|DGND
|DGND
|
|-
| rowspan="2" |J1.148(NAND on board)84| rowspan="2" |SD1_DATA4PCIE1_REF_CLKN| rowspan="2" |CPU.SD1_DATA4PCIE_REF_CLK_N| rowspan="2" |N24A21| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)VDDA_1V8| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA4
|-
|ALT5J1.86|PCIE1_REF_CLKP|CPU.PCIE_REF_CLK_P|B21|VDDA_1V8|D|||GPIO2_IO06
|-
| rowspan="3" |J1.148(eMMC on board)88| rowspan="3" |NAND_DATA04CLKIN1| rowspan="3" |CPU.NAND_DATA04CLKIN1| rowspan="3" |L20H27| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA04
|-
|ALT1J1.90|CLKIN2|CPU.CLKIN2|J27|NVCC_3V3|I|||QSPI_B_DATA0
|-
|ALT5J1.92|PCIE1_RXN|CPU.PCIE_RXN_N|A19|VDDA_1V8|D|||GPIO3_IO10
|-
| rowspan="2" |J1.150(NAND on board)94| rowspan="2" |SD1_DATA5PCIE1_RXP| rowspan="2" |CPU.SD1_DATA5PCIE_RXN_P| rowspan="2" |P24B19| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)VDDA_1V8| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA5
|-
|ALT5J1.96|PCIE1_TXN|CPU.PCIE_TXN_N|A20|VDDA_1V8|D|||GPIO2_IO07
|-
| rowspan="3" |J1.150(eMMC on board)98| rowspan="3" |NAND_DATA05PCIE1_TXP| rowspan="3" |CPU.NAND_DATA05PCIE_TXN_P| rowspan="3" |J22B20| rowspan="3" |NVCC_3V3VDDA_1V8| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA05
|-
|ALT1J1.100|DGND|DGND| -|<nowiki>-</nowiki>|G|||QSPI_B_DATA1
|-
|ALT5J1.102|CSI_P1_CKN|CPU.MIPI_CSI_CLK_N|A16| -|D|||GPIO3_IO11
|-
| rowspan="2" |J1.152(NAND on board)104| rowspan="2" |SD1_DATA6CSI_P1_CKP| rowspan="2" |CPU.SD1_DATA6MIPI_CSI_CLK_P| rowspan="2" |R25B16| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA6
|-
|ALT5J1.106|CSI_P1_DN0|CPU.MIPI_CSI_D0_N|A14| -|D|||GPIO2_IO08
|-
| rowspan="3" |J1.152(eMMC on board)108| rowspan="3" |NAND_DATA06CSI_P1_DP0| rowspan="3" |CPU.NAND_DATA06MIPI_CSI_D0_P| rowspan="3" |L19B14| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA06
|-
|ALT1J1.110|CSI_P1_DN1|CPU.MIPI_CSI_D1_N|A15| -|D|||QSPI_B_DATA2
|-
|ALT5J1.112|CSI_P1_DP1|CPU.MIPI_CSI_D1_P|B15| -|D|||GPIO3_IO12
|-
| rowspan="2" |J1.154(NAND on board)114| rowspan="2" |SD1_DATA7CSI_P1_DN2| rowspan="2" |CPU.SD1_DATA7MIPI_CSI_D2_N| rowspan="2" |T25A17| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA7
|-
|ALT5|GPIO2_IO09|-| rowspan="3" |J1.154(eMMC on board)116| rowspan="3" |NAND_DATA07CSI_P1_DP2| rowspan="3" |CPU.NAND_DATA07| rowspan="3" |M19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-MIPI_CSI_D2_P|ALT5|GPIO3_IO13B17|-|J1.156(NAND on board)|NAND_RE_B|CPU.NAND_RE_B|K19|NVCC_3V3|I/OD|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.156(eMMC on board)118| rowspan="3" |NAND_RE_BCSI_P1_DN3| rowspan="3" |CPU.NAND_RE_BMIPI_CSI_D3_N| rowspan="3" |K19A18| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_RE_B
|-
|ALT1J1.120|CSI_P1_DP3|CPU.MIPI_CSI_D3_P|B18| -|D|||QSPI_B_DQS
|-
|ALT5J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO3_IO15
|-
|J1.158124
(NAND on board)
|NAND_READY_BNAND_DQS|CPU.NAND_READY_BNAND_DQS|K20R22
|NVCC_3V3
|I/O
|
|-
| rowspan="23" |J1.158124
(eMMC on board)
| rowspan="23" |NAND_READY_BNAND_DQS| rowspan="23" |CPU.NAND_READY_BNAND_DQS| rowspan="23" |K20R22| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |
|ALT0
|RAWNAND_READY_BRAWNAND_DQS|-|ALT1|QSPI_A_DQS
|-
|ALT5
|GPIO3_IO16GPIO3_IO14
|-
|J1.160126
(NAND on board)
|NAND_WE_BNAND_ALE|CPU.NAND_WE_BNAND_ALE|K22N22
|NVCC_3V3
|I/O
|
|-
| rowspan="23" |J1.160126
(eMMC on board)
| rowspan="23" |NAND_WE_BNAND_ALE| rowspan="23" |CPU.NAND_WE_BNAND_ALE| rowspan="23" |K22N22| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |
|ALT0
|RAWNAND_WE_BRAWNAND_ALE|-|ALT1|QSPI_A_SCLK
|-
|ALT5
|GPIO3_IO17GPIO3_IO00
|-
| rowspan="2" |J1.162128
(NAND on board)
|NAND_WP_B|CPU.NAND_WP_B|K21|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="2" |J1.162(eMMC on board)| rowspan="2" |NAND_WP_BSD1_CLK| rowspan="2" |CPU.NAND_WP_BSD1_CLK| rowspan="2" |K21V26
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WP_BUSDHC1_CLK
|-
|ALT5
|GPIO3_IO18GPIO2_IO00
|-
| rowspan="3" |J1.164128(eMMC on board)| rowspan="3" |DGNDNAND_CE0_B|DGNDrowspan="3" |CPU.NAND_CE0_B| -rowspan="3" |N24|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_CE0_B
|-
|J1.166|CLK1_N|CPU.CLK1_N|T23||D||ALT1|QSPI_A_SS0_B
|-
|J1.168|CLK1_P|CPU.CLK1_P|R23||D||ALT5|GPIO3_IO01
|-
| rowspan="2" |J1.170130(NAND on board)|USB2_RXNrowspan="2" |SD1_CMD| rowspan="2" |CPU.USB2_RX_NSD1_CMD|B8rowspan="2" |V27|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_CMD
|-
|J1.172|USB2_RXP|CPU.USB2_RX_P|A8||D||ALT5|GPIO2_IO01
|-
| rowspan="4" |J1.174130(eMMC on board)|USB2_TXNrowspan="4" |NAND_CE1_B| rowspan="4" |CPU.USB2_TX_NNAND_CE1_B|B9rowspan="4" |P27|rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_CE1_B
|-
|J1.176|USB2_TXP|CPU.USB2_TX_P|A9||D||ALT1|QSPI_A_SS1_B
|-
|J1.178|USB1_RXN|CPU.USB1_RX_N|B12||D||ALT2|USDHC3_STROBE
|-
|J1.180|USB1_RXP|CPU.USB1_RX_P|A12||D||ALT5|GPIO3_IO02
|-
| rowspan="2" |J1.182132(NAND on board)|USB1_TXNrowspan="2" |SD1_RST_B| rowspan="2" |CPU.USB1_TX_NSD1_RST_B|B13rowspan="2" |R23|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_RESET_B
|-
|J1.184|USB1_TXP|CPU.USB1_TX_P|A13||D||ALT5|GPIO2_IO10
|-
| rowspan="4" |J1.132(eMMC on board)| rowspan="4" |NAND_CE2_B| rowspan="4" |CPU.NAND_CE2_B| rowspan="4" |M27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_CE2_B|-|ALT1|QSPI_B_SS0_B|-|ALT2|USDHC3_DATA5|-|ALT5|GPIO3_IO03|-| rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_STROBE| rowspan="2" |R24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_STROBE|-|ALT5|GPIO2_IO11|-| rowspan="4" |J1.134(eMMC on board)| rowspan="4" |NAND_CE3_B| rowspan="4" |CPU.NAND_CE3_B| rowspan="4" |L27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_CE3_B|-|ALT1|QSPI_B_SS1_B|-|ALT2|USDHC3_DATA6|-|ALT5|GPIO3_IO034|-|J1.136(NAND on board)|NAND_CLE|CPU.NAND_CLE|K27|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="4" |J1.136(eMMC on board)| rowspan="4" |NAND_CLE| rowspan="4" |CPU.NAND_CLE| rowspan="4" |K27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_CLE|-|ALT1|QSPI_B_SCLK|-|ALT2|USDHC3_DATA7|-|ALT5|GPIO3_IO05|-| rowspan="2" |J1.138(NAND on board)| rowspan="2" |SD1_DATA0| rowspan="2" |CPU.SD1_DATA0| rowspan="2" |Y27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA0|-|ALT5|GPIO2_IO02|-| rowspan="3" |J1.138(eMMC on board)| rowspan="3" |NAND_DATA00| rowspan="3" |CPU.NAND_DATA00| rowspan="3" |P23| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA00|-|ALT1|QSPI_A_DATA0|-|ALT5|GPIO3_IO06|-| rowspan="2" |J1.140(NAND on board)| rowspan="2" |SD1_DATA1| rowspan="2" |CPU.SD1_DATA1| rowspan="2" |Y26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA1|-|ALT5|GPIO2_IO0|-| rowspan="3" |J1.140(eMMC on board)| rowspan="3" |NAND_DATA01| rowspan="3" |CPU.NAND_DATA01| rowspan="3" |K24| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA01|-|ALT1|QSPI_A_DATA1|-|ALT5|GPIO3_IO07|-| rowspan="2" |J1.142(NAND on board)| rowspan="2" |SD1_DATA2| rowspan="2" |CPU.SD1_DATA2| rowspan="2" |T27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA2|-|ALT5|GPIO2_IO04|-| rowspan="4" |J1.142(eMMC on board)| rowspan="4" |NAND_DATA02| rowspan="4" |CPU.NAND_DATA02| rowspan="4" |K23| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA02|-|ALT1|QSPI_A_DATA2|-|ALT2|USDHC3_CD_B(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO3_IO08|-| rowspan="2" |J1.144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |T26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="4" |J1.144(eMMC on board)| rowspan="4" |NAND_DATA03| rowspan="4" |CPU.NAND_DATA03| rowspan="4" |N23| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT2|USDHC3_WP(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO3_IO09|-|J1.146|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="2" |J1.148(NAND on board)| rowspan="2" |SD1_DATA4| rowspan="2" |CPU.SD1_DATA4| rowspan="2" |U27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4|-|ALT5|GPIO2_IO06|-| rowspan="4" |J1.148(eMMC on board)| rowspan="4" |NAND_DATA04| rowspan="4" |CPU.NAND_DATA04| rowspan="4" |M26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA04|-|ALT1|QSPI_B_DATA0|-|ALT2|USDHC3_DATA0|-|ALT5|GPIO3_IO10|-| rowspan="2" |J1.150(NAND on board)| rowspan="2" |SD1_DATA5| rowspan="2" |CPU.SD1_DATA5| rowspan="2" |U26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA5|-|ALT5|GPIO2_IO07|-| rowspan="4" |J1.150(eMMC on board)| rowspan="4" |NAND_DATA05| rowspan="4" |CPU.NAND_DATA05| rowspan="4" |L26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA05|-|ALT1|QSPI_B_DATA1|-|ALT2|USDHC3_DATA1|-|ALT5|GPIO3_IO11|-| rowspan="2" |J1.152(NAND on board)| rowspan="2" |SD1_DATA6| rowspan="2" |CPU.SD1_DATA6| rowspan="2" |W27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA6|-|ALT5|GPIO2_IO08|-| rowspan="4" |J1.152(eMMC on board)| rowspan="4" |NAND_DATA06| rowspan="4" |CPU.NAND_DATA06| rowspan="4" |K26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA06|-|ALT1|QSPI_B_DATA2|-|ALT2|USDHC3_DATA2|-|ALT5|GPIO3_IO12|-| rowspan="2" |J1.154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |W26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09|-| rowspan="4" |J1.154(eMMC on board)| rowspan="4" |NAND_DATA07| rowspan="4" |CPU.NAND_DATA07| rowspan="4" |N26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT2|USDHC3_DATA3|-|ALT5|GPIO3_IO13|-|J1.156(NAND on board)|NAND_RE_B|CPU.NAND_RE_B|N27|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="4" |J1.156(eMMC on board)| rowspan="4" |NAND_RE_B| rowspan="4" |CPU.NAND_RE_B| rowspan="4" |N27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_RE_B|-|ALT1|QSPI_B_DQS|-|ALT2|USDHC3_DATA4|-|ALT5|GPIO3_IO15|-|J1.158(NAND on board)|NAND_READY_B|CPU.NAND_READY_B|P26|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.158(eMMC on board)| rowspan="3" |NAND_READY_B| rowspan="3" |CPU.NAND_READY_B| rowspan="3" |P26| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_READY_B|-|ALT2|USDHC3_RESET_B|-|ALT5|GPIO3_IO16|-|J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|R26|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.160(eMMC on board)| rowspan="3" |NAND_WE_B| rowspan="3" |CPU.NAND_WE_B| rowspan="3" |R26| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_WE_B|-|ALT2|USDHC3_CLK|-|ALT5|GPIO3_IO17|-|J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|R27|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.162(eMMC on board)| rowspan="3" |NAND_WP_B| rowspan="3" |CPU.NAND_WP_B| rowspan="3" |R27| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_WP_B|-|ALT2|USDHC3_CMD|-|ALT5|GPIO3_IO18|-|J1.164|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="5" |J1.166| rowspan="5" |GPIO1_IO15| rowspan="5" |CPU.GPIO1_IO15| rowspan="5" |AB9| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|GPIO1_IO15|-|ALT1|USB2_OTG_OC|-|ALT4|USDHC3_WP(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT4)|-|ALT5|PWM4_OUT|-|ALT6|CCM_CLKO2|-| rowspan="4" |J1.168| rowspan="4" |GPIO1_IO07| rowspan="4" |CPU.GPIO1_IO07| rowspan="4" |AF11| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO07|-|ALT1|ENET1_MDIO(Configure register IOMUXC_ENET1_MDIO_SELECT_INPUT for mode ALT1)|-|ALT5|USDHC1_WP|-|ALT6|CCM_EXT_CLK4|-| rowspan="6" |J1.170| rowspan="6" |SAI1_TXD4| rowspan="6" |CPU.SAI1_TXD4| rowspan="6" |AG22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA4|-|ALT1|SAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_BCLK(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE12|-|ALT5|GPIO4_IO16|-|ALT6|SRC_BOOT_CFG12|-| rowspan="6" |J1.172| rowspan="6" |SAI1_TXD5| rowspan="6" |CPU.SAI1_TXD5| rowspan="6" |AF22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA5|-|ALT1|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT1)|-|ALT2|SAI6_TX_DATA0|-|ALT4|CORESIGHT_TRACE13|-|ALT5|GPIO4_IO17|-|ALT6|SRC_BOOT_CFG13|-| rowspan="6" |J1.174| rowspan="6" |SAI1_TXD6| rowspan="6" |CPU.SAI1_TXD6| rowspan="6" |AG23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA6|-|ALT1|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE14|-|ALT5|GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14|-| rowspan="6" |J1.176| rowspan="6" |SAI1_TXD7| rowspan="6" |CPU.SAI1_TXD7| rowspan="6" |AF23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT3|PDM_CLK|-|ALT4|CORESIGHT_TRACE15|-|ALT5|GPIO4_IO19|-|ALT6|SRC_BOOT_CFG15|-| rowspan="7" |J1.178| rowspan="7" |SAI1_RXD7| rowspan="7" |CPU.SAI1_RXD7| rowspan="7" |AF19| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI1_TX_DATA4|-|ALT4|CORESIGHT_TRACE7|-|ALT5|GPIO4_IO09|-|ALT6|SRC_BOOT_CFG7|-| rowspan="6" |J1.180| rowspan="6" |SAI1_RXD6| rowspan="6" |CPU.SAI1_RXD6| rowspan="6" |AG19| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA6|-|ALT1|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE6|-|ALT5|GPIO4_IO08|-|ALT6|SRC_BOOT_CFG6|-| rowspan="7" |J1.182| rowspan="7" |SAI1_RXD5| rowspan="7" |CPU.SAI1_RXD5| rowspan="7" |AF18| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA5|-|ALT1|SAI6_TX_DATA0|-|ALT2|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT2)|-|ALT3|SAI1_RX_SYNC(Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT3)|-|ALT4|CORESIGHT_TRACE5|-|ALT5|GPIO4_IO07|-|ALT6|SRC_BOOT_CFG|-| rowspan="6" |J1.184| rowspan="6" |SAI1_RXD4| rowspan="6" |CPU.SAI1_RXD4| rowspan="6" |AG18| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA4|-|ALT1|SAI1_RX_DATA4(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE4|-|ALT5|GPIO4_IO06|-|ALT6|SRC_BOOT_CFG4|-|J1.186|USB1_VBUS|CPU.USB1_VBUS|D14F22| -|S|Connected with 30K resistor on SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.188|USB2_VBUS|CPU.USB2_VBUS|D9F23| -|S|Connected with 30K resistor on SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.190|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J1.192|USB1_ID|CPU.USB1_ID|C14D22|VDD_PHY_3V3VDDA_1V8|I||||-|J1.194|USB2_ID
|CPU.USB2_ID
|C9D23|VDD_PHY_3V3VDDA_1V8
|I
|
|USB1_DN
|CPU.USB1_DN
|B14A22
| -
|D
|USB1_DP
|CPU.USB1_DP
|A14B22
| -
|D
|USB2_DP
|CPU.USB2_DP
|A10B23
| -
|D
|USB2_DN
|CPU.USB2_DN
|B10A23
| -
|D
|-
|}
'''(*)''' PMIC_PWRON can be used in two configuration: ''Embedded-like'' (default mounting option) or ''Tablet-like''. In the first case, the system reboots in case of PMIC_PWR_ON signal activity.
 
In the second case, the system will shut down waiting for a CPU_ONOFF signal raising (like a button-mode in a tablet) and the PMIC_PWRON Voltage domain is NVCC_SNVS_1V8
Please contact [mailto:sales@dave.eu sales dept.] for more information
----
[[Category:MITO 8M Mini]]
[[Category:MITO 8M Nano]]
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