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MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table

16,711 bytes added, 18:06, 27 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 14768|Dec 20202021/10/11}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2023/10/26
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Update pin information
|-
|}
<section end="History" /><section begin="Body" />
==Connectors and Pinout Table description==
=== Connectors description ===
In the following table are described all available connectors integrated on MITO 8M Mini/Nano SOM:
{| class="wikitable"
|-
|-
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini/Nano pinout specifications. See the images below for reference:
[[File:MITO_8M_Mini_MITO8M_Mini-_TOPconn-top.jpegpng|500px|thumb|MITO 8M Mini/Nano TOP view|none]][[File:MITO_8M_Mini_MITO8M_Mini-conn-_BOTTOMbottom.jpegpng|500px|thumb|MITO 8M Mini/Nano BOTTOM view|none]]
Below a detailed description of the pinout, grouped in the following tables:
|-
|'''Pin Name'''
| Pin (signal) name on the MITO 8M Mini connectors
|-
|'''Internal<br>connections'''
| Connections to the components
* CPU.<x> : pin connected to CPU pad named <x>(NXP iMX8MM)* PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210PF8121)
* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
| rowspan="4" |GPIO1_IO00
| rowspan="4" |CPU.GPIO1_IO00
| rowspan="4" |T6AG14
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
|-
|ALT5
|ANAMIX_REF_CLK_32KCCM_REF_CLK_32K
|-
|ALT6
| rowspan="4" |GPIO1_IO01
| rowspan="4" |CPU.GPIO1_IO01
| rowspan="4" |T7AF14
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
|-
|ALT5
|ANAMIX_REF_CLK_25MCCM_REF_CLK_24M
|-
|ALT6
| rowspan="3" |SPDIF_EXT_CLK
| rowspan="3" |CPU.SPDIF_EXT_CLK
| rowspan="3" |E6AF8
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |GPIO1_IO13
| rowspan="3" |CPU.GPIO1_IO13
| rowspan="3" |K6AD9
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|GPIO1_IO13
|PWM2_OUT
|-
| rowspan="2" |J1.45|VDD_PHY_1V8rowspan="2" |GPIO1_IO11| rowspan="2" |CPU.GPIO1_IO11| rowspan="2" |AC10|rowspan="2" |NVCC_3V3|rowspan="2" |I/O| rowspan="2" |Internally used for ETH CLK enable, do not connect|ALT0|GPIO1_IO11|-|ALT1|USB1_OTG_ID
|-
| rowspan="3" |J1.47
| rowspan="3" |ECSPI2_SCLK
| rowspan="3" |CPU.ECSPI2_SCLK
| rowspan="3" |C5E6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |ECSPI2_MOSI
| rowspan="3" |CPU.ECSPI2_MOSI
| rowspan="3" |E5B8
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |GPIO1_IO08
| rowspan="3" |CPU.GPIO1_IO08
| rowspan="3" |N7AG10
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|USDHC2_RESET_B
|-
| rowspan="34" |J1.53| rowspan="34" |GPIO1_IO09| rowspan="34" |CPU.GPIO1_IO09| rowspan="34" |M7AF10| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|GPIO1_IO09
|ALT1
|ENET1_1588_EVENT0_OUT
|-
|ALT4
|USDHC3_RESET_B
|-
|ALT5
| rowspan="3" |ECSPI2_MISO
| rowspan="3" |CPU.ECSPI2_MISO
| rowspan="3" |B5A8
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |ECSPI2_SS0
| rowspan="3" |CPU.ECSPI2_SS0
| rowspan="3" |A5A6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|ALT1
|UART4_RTS_B
(Configure register IOMUXC_UART4_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
| rowspan="3" |GPIO1_IO05
| rowspan="3" |CPU.GPIO1_IO05
| rowspan="3" |P7AF12
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|CCM_PMIC_READY
|-
| rowspan="34" |J1.63| rowspan="34" |I2C2_SCLSAI5_RXD0| rowspan="34" |CPU.I2C2_SCLSAI5_RXD0| rowspan="34" |G7AD18| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|I2C2_SCLSAI5_RX_DATA0( Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT0)
|-
|ALT1
|ENET1_1588_EVENT1_INSAI1_TX_DATA2|-|ALT4|PDM_BIT_STREAM0(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT4)
|-
|ALT5
|GPIO5_IO16GPIO3_IO21
|-
| rowspan="36" |J1.65| rowspan="36" |I2C2_SDASAI5_RXD1| rowspan="36" |CPU.I2C2_SDASAI5_RXD1| rowspan="36" |F7AC14| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|I2C2_SDASAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT0)
|-
|ALT1
|ENET1_1588_EVENT1_OUTSAI1_TX_DATA3|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI5_TX_SYNC(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT3)|-|ALT4|PDM_BIT_STREAM1(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT4)
|-
|ALT5
|GPIO5_IO17GPIO3_IO22
|-
| rowspan="4" |J1.67
| rowspan="4" |GPIO1_IO06
| rowspan="4" |CPU.GPIO1_IO06
| rowspan="4" |N5AG11
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
|CCM_EXT_CLK3
|-
| rowspan="34" |J1.69| rowspan="34" |SAI2_RXC| rowspan="34" |CPU.SAI2_RXC| rowspan="34" |H3AB22| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|SAI2_RX_BCLK
|ALT1
|SAI5_TX_BCLK
(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|ALT4
|UART1_RX
|-
|ALT5
|GPIO4_IO22
|-
| rowspan="36" |J1.71| rowspan="36" |SAI2_RXFS| rowspan="36" |CPU.SAI2_RXFS| rowspan="36" |J4AC19| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|SAI2_RX_SYNC
|ALT1
|SAI5_TX_SYNC
(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
|-
|ALT2
|SAI5_TX_DATA1
|-
|ALT3
|SAI2_RX_DATA1
|-
|ALT4
|UART1_TX
|-
|ALT5
| rowspan="2" |SD2_DATA0
| rowspan="2" |CPU.SD2_DATA0
| rowspan="2" |N22AB23
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_DATA1
| rowspan="2" |CPU.SD2_DATA1
| rowspan="2" |N21AB24
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_DATA2
| rowspan="2" |CPU.SD2_DATA2
| rowspan="2" |P22V24
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_DATA3
| rowspan="2" |CPU.SD2_DATA03
| rowspan="2" |P21V23
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_CMD
| rowspan="2" |CPU.SD2_CMD
| rowspan="2" |M22W24
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_CLK
| rowspan="2" |CPU.SD2_CLK
| rowspan="2" |L22W23
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
|
|-
| rowspan="34" |J1.89| rowspan="34" |UART3_TXD| rowspan="34" |CPU.UART3_TXD| rowspan="34" |B7D18| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |Internally pulled-up to NVCC_3V3
|ALT0
|UART3_TX
|ALT1
|UART1_RTS_B
(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT2
|USDHC3_VSELECT
|-
|ALT5
|GPIO5_IO27
|-
| rowspan="34" |J1.91| rowspan="34" |UART3_RXD| rowspan="34" |CPU.UART3_RXD| rowspan="34" |A6E18| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|UART3_RX
|ALT1
|UART1_CTS_B
|-
|ALT2
|USDHC3_RESET_B
|-
|ALT5
|GPIO5_IO26
|-
| rowspan="43" |J1.93| rowspan="43" |UART4_TXDUART1_TXD| rowspan="43" |CPU.UART4_TXDUART1_TXD| rowspan="43" |D7F13| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|UART4_TXUART1_TX
|-
|ALT1
|UART2_RTS_B|-|ALT2|PCIE2_CLKREQ_BECSPI3_MOSI
|-
|ALT5
|GPIO5_IO29GPIO5_IO23
|-
| rowspan="43" |J1.95| rowspan="43" |UART4_RXDUART1_RXD| rowspan="43" |CPU.UART4_RXDUART1_RXD| rowspan="43" |C6E14| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|UART4_RXUART1_RX
|-
|ALT1
|UART2_CTS_B|-|ALT2|PCIE1_CLKREQ_BECSPI3_SCLK
|-
|ALT5
|GPIO5_IO28GPIO5_IO22
|-
| rowspan="2" |J1.97
| rowspan="2" |SD2_WP
| rowspan="2" |CPU.SD2_WP
| rowspan="2" |M21AA27
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_RST_B
| rowspan="2" |CPU.SD2_RESET_B
| rowspan="2" |R22AB26
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
|GPIO2_IO19
|-
| rowspan="4" |J1.101|HDMI_DDC_SCLrowspan="4" |I2C2_SCL| rowspan="4" |CPU.HDMI_DDC_SCLI2C2_SCL|R3rowspan="4" |D10|VDD_PHY_1V8rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|I2C2_SCL
|-
|J1.103|HDMI_DDC_SDA|CPU.HDMI_DDC_SDA|P3|VDD_PHY_1V8|I/O||ALT1|ENET1_1588_EVENT1_IN
|-
|J1.105ALT2|HDMI_AUX_NUSDHC3_CD_B|CPU.HDMI_AUX_N|V2| -|D|connected with capacitor in series||(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)
|-
|J1.107|HDMI_AUX_P|CPU.HDMI_AUX_P|V1| -|D|connected with capacitor in series|ALT5|GPIO5_IO16
|-
| rowspan="4" |J1.109103|DGND rowspan="4" |I2C2_SDA|DGNDrowspan="4" |CPU.I2C2_SDA| -rowspan="4" |D9| -rowspan="4" |NVCC_3V3|Growspan="4" |I/O| rowspan="4" ||ALT0|I2C2_SDA
|-
|J1.111|HDMI_TX_M_LN_3|CPU.HDMI_TX_M_LN_3|M2| -|D|connected with capacitor in series|ALT1|ENET1_1588_EVENT1_OUT
|-
|J1.113ALT2|HDMI_TX_P_LN_3USDHC3_WP|CPU.HDMI_TX_P_LN_3|M1| -|D|connected with capacitor in series||(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)
|-
|J1.115|HDMI_TX_M_LN_0|CPU.HDMI_TX_M_LN_0|T2| -|D|connected with capacitor in series|ALT5|GPIO5_IO17
|-
| rowspan="6" |J1.117105|HDMI_TX_P_LN_0rowspan="6" |SAI1_RXD3| rowspan="6" |CPU.HDMI_TX_P_LN_0SAI1_RXD3| rowspan="6" |AF17| rowspan="6" | NVCC_3V3|T1rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on|D[[MITO 8M Mini SOM/Part number composition|connected with capacitor in seriesMITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA3
|-
|J1.119ALT1|HDMI_TX_M_LN_1SAI5_RX_DATA3|CPU.HDMI_TX_M_LN_1|U1| -|D|connected with capacitor in series||(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT1)
|-
|J1.121ALT3|HDMI_TX_P_LN_1PDM_BIT_STREAM3|CPU.HDMI_TX_P_LN_1|U2| -|D|connected with capacitor in series||(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT3)
|-
|J1.123|HDMI_TX_M_LN_2|CPU.HDMI_TX_M_LN_2|N1| -|D|connected with capacitor in series|ALT4|CORESIGHT_TRACE3
|-
|J1.125|HDMI_TX_P_LN_2|CPU.HDMI_TX_P_LN_2|N2| -|D|connected with capacitor in series|ALT5|GPIO4_IO05
|-
|J1.127|HDMI_CEC|CPU.HDMI_CEC|W3|VDD_PHY_1V8|I/O||ALT6|SRC_BOOT_CFG3
|-
| rowspan="5" |J1.129107|HDMI_HPDrowspan="5" |SAI1_TXD3| rowspan="5" |CPU.HDMI_HPDSAI1_TXD3|W2rowspan="5" |AF21|VDD_PHY_1V8rowspan="5" | NVCC_3V3| rowspan="5" |I/O|rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA3|-|ALT1|SAI5_TX_DATA3|-|ALT4|CORESIGHT_TRACE11|-|ALT5|GPIO4_IO15|-|ALT6|SRC_BOOT_CFG11
|-
|J1.131109
|DGND
|DGND
|
|-
| rowspan="4" |J1.133111|LVDS0_CLK_Nrowspan="4" |SAI1_TXFS|BRIDGErowspan="4" |CPU.A_CLKNSAI1_TXFS|F9rowspan="4" |AB19| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_TX_SYNC (Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT0)
|-
|J1.135ALT1|LVDS0_CLK_PSAI5_TX_SYNC|BRIDGE.A_CLKP|F8| -|D|||(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
|-
|J1.137|LVDS0_TX0_N|BRIDGE.A_Y0N|C9| -|D||ALT4|CORESIGHT_EVENTO
|-
|J1.139|LVDS0_TX0_P|BRIDGE.A_Y0P|C8| -|D||ALT5|GPIO4_IO10
|-
| rowspan="4" |J1.141113|LVDS0_TX1_Nrowspan="4" |SAI1_TXC|BRIDGErowspan="4" |CPU.A_Y1NSAI1_TXC| rowspan="4" |AC18| rowspan="4" |NVCC_3V3|D9rowspan="4" |I/O| -rowspan="4" ||DALT0|SAI1_TX_BCLK (Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|J1.143|LVDS0_TX1_P|BRIDGE.A_Y1P|D8| -|D||ALT4|CORESIGHT_EVENTI
|-
|J1.145|LVDS0_TX2_N|BRIDGE.A_Y2N|E9| -|D||ALT5|GPIO4_IO11
|-
| rowspan="5" |J1.147115|LVDS0_TX2_Prowspan="5" |SAI1_TXD0|BRIDGErowspan="5" |CPU.A_Y2PSAI1_TXD0| rowspan="5" |AG20|E8rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|DMITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA0|-|ALT1|SAI5_TX_DATA0
|-
|J1.149|LVDS0_TX3_N|BRIDGE.A_Y3N|G9| -|D||ALT4|CORESIGHT_TRACE8
|-
|J1.151|LVDS0_TX3_P|BRIDGE.A_Y3P|G8| -|D||ALT5|GPIO4_IO12
|-
|ALT6|SRC_BOOT_CFG8|-| rowspan="5" |J1.153117|DGND rowspan="5" |SAI1_TXD1|DGNDrowspan="5" |CPU.SAI1_TXD1| -rowspan="5" |AF20| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on|G[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA1
|-
|J1.155|LVDS1_CLK_N|BRIDGE.B_CLKN|A6| -|D||ALT1|SAI5_TX_DATA1
|-
|J1.157|LVDS1_CLK_P|BRIDGE.B_CLKP|B6| -|D||ALT4|CORESIGHT_TRACE9
|-
|J1.159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D||ALT5|GPIO4_IO13
|-
|J1.161|LVDS1_TX0_P|BRIDGE.B_Y0P|B3| -|D||ALT6|SRC_BOOT_CFG9
|-
| rowspan="5" |J1.163119|LVDS1_TX1_Nrowspan="5" |SAI1_TXD2|BRIDGErowspan="5" |CPU.B_Y1NSAI1_TXD2| rowspan="5" |AG21| rowspan="5" |NVCC_3V3|A4rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration: can be pulled-up or down depending on|D[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA2
|-
|J1.165ALT1|LVDS1_TX1_P|BRIDGE.B_Y1P|B4SAI5_TX_DATA2| -|D||ALT4|CORESIGHT_TRACE10
|-
|J1.167|LVDS1_TX2_N|BRIDGE.B_Y2N|A5| -|D||ALT5|GPIO4_IO14
|-
|J1.169|LVDS1_TX2_P|BRIDGE.B_Y2P|B5| -|D||ALT6|SRC_BOOT_CFG10
|-
| rowspan="4" |J1.171121|LVDS1_TX3_Nrowspan="4" |SAI1_RXFS|BRIDGErowspan="4" |CPU.B_Y3NSAI1_RXFS| rowspan="4" |AG16| rowspan="4" |NVCC_3V3|A7rowspan="4" |I/O| -rowspan="4" ||DALT0|SAI1_RX_SYNC (Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT1)
|-
|J1.173|LVDS1_TX3_P|BRIDGE.B_Y3P|B7| -|D||ALT4|CORESIGHT_TRACE_CLK
|-
|J1.175|DGND |DGND| -| -|G||ALT5|GPIO4_IO00
|-
| rowspan="24" |J1.177123| rowspan="24" |SD2_CD_BSAI1_RXC| rowspan="24" |CPU.SD2_CD_BSAI1_RXC| rowspan="24" |L21AF16| rowspan="24" |NVCC_3V3| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC2_CD_BSAI1_RX_BCLK|-|ALT1|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT4|CORESIGHT_TRACE_CTL
|-
|ALT5
|GPIO2_IO12GPIO4_IO01
|-
| rowspan="37" |J1.179125| rowspan="37" |ECSPI1_SS0SAI1_RXD0| rowspan="37" |CPU.ECSPI1_SS0SAI1_RXD0| rowspan="37" |D4AG15| rowspan="37" |NVCC_3V3| rowspan="37" |I/O| rowspan="37" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|ECSPI1_SS0SAI1_RX_DATA0
|-
|ALT1
|UART3_RTS_BSAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT1)|-|ALT2|SAI1_TX_DATA1|-|ALT3|PDM_BIT_STREAM0(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT3)|-|ALT4|CORESIGHT_TRACE0
|-
|ALT5
|GPIO5_IO09GPIO4_IO02|-|ALT6|SRC_BOOT_CFG0
|-
| rowspan="36" |J1.181127| rowspan="36" |ECSPI1_SCLKSAI1_RXD1| rowspan="36" |CPU.ECSPI1_SCLKSAI1_RXD1| rowspan="36" |D5AF15| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|ECSPI1_SCLKSAI1_RX_DATA1
|-
|ALT1
|UART3_RXSAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT1)|-|ALT3|PDM_BIT_STREAM1(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT3)|-|ALT4|CORESIGHT_TRACE1
|-
|ALT5
|GPIO5_IO06GPIO4_IO03|-|ALT6|SRC_BOOT_CFG1
|-
| rowspan="36" |J1.183129| rowspan="36" |ECSPI1_MISOSAI1_RXD2| rowspan="36" |CPU.ECSPI1_MISOSAI1_RXD2| rowspan="36" |B4AG17| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|ECSPI1_MISOSAI1_RX_DATA2
|-
|ALT1
|UART3_CTS_BSAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT1)|-|ALT3|PDM_BIT_STREAM2(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT3)|-|ALT4|CORESIGHT_TRACE2
|-
|ALT5
|GPIO5_IO08GPIO4_IO04|-|ALT6|SRC_BOOT_CFG2
|-
| rowspan="3" |J1.185131| rowspan="3" |GPIO1_IO03DGND | rowspan="3" |CPU.GPIO1_IO03DGND| rowspan="3" |P4-| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OG| rowspan="3" ||ALT0|GPIO1_IO03
|-
|ALT1J1.133|LVDS0_CLK_N|BRIDGE.A_CLKN|F9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||USDHC1_VSELECT
|-
|ALT5J1.133|DSI_CLK_N|CPU.MIPI_DSI_CLK_N|A11| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||SDMA1_EXT_EVENT0
|-
| rowspan="3" |J1.187135| rowspan="3" |UART2_TXDLVDS0_CLK_P| rowspan="3" |CPUBRIDGE.UART2_TXDA_CLKP| rowspan="3" F8|D6-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |used as default Linux consoleN composition]]|ALT0|UART2_TX
|-
|ALT1J1.135|DSI_CLK_P|CPU.MIPI_|B11| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_SS0
|-
|ALT5J1.137|LVDS0_TX0_N|BRIDGE.A_Y0N|C9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO25
|-
| rowspan="3" |J1.189137| rowspan="3" |UART2_RXDDSI_D0_N| rowspan="3" |CPU.UART2_RXDMIPI_DSI_D0_N| rowspan="3" A9|B6-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |used as default Linux consoleN composition]]|ALT0|UART2_RXD
|-
|ALT1J1.139|LVDS0_TX0_P|BRIDGE.A_Y0P|C8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_MISO
|-
|ALT5J1.139|DSI_D0_P|CPU.MIPI_DSI_D0_P|B9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO24
|-
| rowspan="3" |J1.191141| rowspan="3" |UART1_TXDLVDS0_TX1_N| rowspan="3" |CPUBRIDGE.UART1_TXDA_Y1N| rowspan="3" D9|A7-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|UART1_TX
|-
|ALT1J1.141|DSI_D1_N|CPU.MIPI_DSI_D1_N|A10| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_MOSI
|-
|ALT5J1.143|LVDS0_TX1_P|BRIDGE.A_Y1P|D8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO23
|-
| rowspan="3" |J1.193143| rowspan="3" |UART1_RXDDSI_D1_P| rowspan="3" |CPU.UART1_RXDMIPI_DSI_D1_P| rowspan="3" B10|C7-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|UART1_RXD
|-
|ALT1J1.145|LVDS0_TX2_N|BRIDGE.A_Y2N|E9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||ECSPI3_SCLK
|-
|ALT5J1.145|DSI_D2_N|CPU.MIPI_DSI_D2_N|A12| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO22
|-
| rowspan="3" |J1.195147| rowspan="3" |ECSPI1_MOSILVDS0_TX2_P| rowspan="3" |CPUBRIDGE.ECSPI1_MOSIA_Y2P| rowspan="3" E8|A4-| rowspan="3" |NVCC_3V3D| rowspan="3" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="3" |N composition]]|ALT0|ECSPI1_MOSI
|-
|ALT1J1.147|DSI_D2_P|CPU.MIPI_DSI_D2_P|B12| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||UART3_TX
|-
|ALT5J1.149|LVDS0_TX3_N|BRIDGE.A_Y3N|G9| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||GPIO5_IO07
|-
| rowspan="4" |J1.197149| rowspan="4" |GPIO1_IO14DSI_D3_N| rowspan="4" |CPU.GPIO1_IO14MIPI_DSI_D3_N| rowspan="4" A13|K7-| rowspan="4" |NVCC_3V3D| rowspan="4" Depending on [[MITO 8M Mini SOM/Part number composition|IMITO 8M Mini SOM P/O| rowspan="4" |N composition]]|ALT0|GPIO1_IO14
|-
|ALT1J1.151|LVDS0_TX3_P|BRIDGE.A_Y3P|G8| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||USB2_OTG_PWR
|-
|ALT5J1.151|DSI_D3_P|CPU.MIPI_DSI_D3_P|B13| -|D|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]||PWM3_OUT
|-
|ALT6J1.153|DGND |DGND| -| -|G|||CCM_CLKO1
|-
| rowspan="3" |J1.199| rowspan="3" |GPIO1_IO04| rowspan="3" |CPU.GPIO1_IO04| rowspan="3" |P5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO04|-|ALT1|USDHC2_VSELECT|-|ALT5|SDMA1_EXT_EVENT1|-| rowspan="3" |J1.201155| rowspan="3" |GPIO1_IO12LVDS1_CLK_N| rowspan="3" |CPUBRIDGE.GPIO1_IO12| rowspan="3" |L7| rowspan="3" |NVCC_3V3B_CLKN| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO12|-|ALT1|USB1_OTG_PWR|-|ALT5|SDMA2_EXT_EVENT1|-|J1.203|DGND |DGND| -A6| -|GD
|
|
|
|-
|} ==SODIMM J1 EVEN pins declaration ==.157 {| class="wikitable" LVDS1_CLK_P! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" | Alternative Functions|-|J1BRIDGE.2|DGNDB_CLKP|DGNDB6
| -
|<nowiki>-</nowiki>|GD
|
|
|
|-
|J1.4159|3LVDS1_TX0_N|BRIDGE.3VIN B_Y0N|INPUT VOLTAGEA3
| -
|3.3VIN|SD
|
|
|
|-
|J1.6161|3LVDS1_TX0_P|BRIDGE.3VIN B_Y0P|INPUT VOLTAGEB3
| -
|3.3VIN|SD
|
|
|
|-
|J1.8163|3LVDS1_TX1_N|BRIDGE.3VIN B_Y1N|INPUT VOLTAGEA4
| -
|3.3VIN|SD
|
|
|
|-
|J1.10165|3LVDS1_TX1_P|BRIDGE.3VIN B_Y1P|INPUT VOLTAGEB4
| -
|3.3VIN|SD
|
|
|
|-
|J1.12167|DGNDLVDS1_TX2_N|DGNDBRIDGE.B_Y2N|A5
| -
|<nowiki>-</nowiki>|GD
|
|
|
|-
|J1.14169|PMIC_LICELL LVDS1_TX2_P|PMICBRIDGE.LICELLB_Y2P|30B5
| -
|SD
|
|
|
|-
|J1.16171|CPU_ONOFFLVDS1_TX3_N|CPUBRIDGE.ONOFFB_Y3N|W21A7|NVCC_SNVS-|ID|internal pull-up 100k to NVCC_SNVS
|
|
|-
|J1.18173|BOARD_PGOODLVDS1_TX3_P|BRIDGE.B_Y3P|B7
| -
| -|NVCC_3V3|OD
|
|
|
|-
|J1.20175|BOOT_MODE_SELDGND |BOOT MODE SELECTIONDGND| -
| -
|NVCC_3V3|I|internal pull-up to NVCC_3V3|G
|
|-
|J1.22
|CPU_PORn
|CPU.POR_B
PMIC.RESETMCU
|W20
3
|NVCC_SNVS
|I/O
|internal pull-up 100k to NVCC_SNVS
|
|
|-
|J1.24|EXT_RESET|MASTER RESET| -| -|I|internal pull-up to NVCC_SNVS|||-| rowspan="42" |J1.26177| rowspan="42" |SAI3_RXCSD2_CD_B| rowspan="42" |CPU.SAI3_RXCSD2_CD_B| rowspan="42" |F4AA26| rowspan="42" |NVCC_3V3| rowspan="42" |I/O| rowspan="42" |
|ALT0
|SAI3_RX_BCLKUSDHC2_CD_B
|-
|ALT1ALT5|GPT1_CAPTURE2GPIO2_IO12|-| rowspan="3" |J1.179| rowspan="3" |ECSPI1_SS0| rowspan="3" |CPU.ECSPI1_SS0| rowspan="3" |B6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_SS0
|-
|ALT2ALT1|SAI5_RX_BCLKUART3_RTS_B(Configure register IOMUXC_UART3_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO4_IO29GPIO5_IO09
|-
| rowspan="43" |J1.28181| rowspan="43" |GPIO1_IO02ECSPI1_SCLK| rowspan="43" |CPU.GPIO1_IO02ECSPI1_SCLK| rowspan="43" |R4D6| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02ECSPI1_SCLK
|-
|ALT1
|WDOG1_WDOG_BUART3_RX
|-
|ALT5
|WDOG1_WDOG_ANYGPIO5_IO06
|-
|ALT7|SJC_DE_B|-|J1.30|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="43" |J1.32183| rowspan="43" |SAI3_RXDECSPI1_MISO| rowspan="43" |CPU.SAI3_RXDECSPI1_MISO| rowspan="43" |F3A7| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_RX_DATA0ECSPI1_MISO
|-
|ALT1
|GPT1_COMPARE1|-|ALT2|SAI5_RX_DATA0UART3_CTS_B
|-
|ALT5
|GPIO4_IO30GPIO5_IO08
|-
| rowspan="3" |J1.34185| rowspan="3" |SAI2_MCLKGPIO1_IO03| rowspan="3" |CPU.SAI2_MCLKGPIO1_IO03| rowspan="3" |H5AF13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for PMIC interrupt, do not connect Pulled-up to NVCC_3V3
|ALT0
|SAI2_MCLKGPIO1_IO03
|-
|ALT1
|SAI5_MCLKUSDHC1_VSELECT
|-
|ALT5
|GPIO4_IO27SDMA1_EXT_EVENT0
|-
| rowspan="43" |J1.36187| rowspan="43" |SAI3_RXFSUART2_TXD| rowspan="43" |CPU.SAI3_RXFSUART2_TXD| rowspan="43" |G4E15| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |used as default Linux console
|ALT0
|SAI3_RX_SYNCUART2_TX
|-
|ALT1
|GPT1_CAPTURE1|-|ALT2|SAI5_RX_SYNCECSPI3_SS0
|-
|ALT5
|GPIO4_IO28GPIO5_IO25
|-
| rowspan="43" |J1.38189| rowspan="43" |I2C3_SCLUART2_RXD| rowspan="43" |CPU.I2C3_SCLUART2_RXD| rowspan="43" |G8F15| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |used as default Linux console
|ALT0
|I2C3_SCLUART2_RXD
|-
|ALT1
|PWM4_OUTECSPI3_MISO|-|ALT5|GPIO5_IO24|-| rowspan="3" |J1.191| rowspan="3" |UART4_TXD| rowspan="3" |CPU.UART4_TXD| rowspan="3" |F18| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART4_TX
|-
|ALT2ALT1|GPT2_CLKUART2_RTS_B(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO5_IO18GPIO5_IO29
|-
| rowspan="4" |J1.40193| rowspan="4" |SAI3_TXFSUART4_RXD| rowspan="4" |CPU.SAI3_TXFSUART4_RXD| rowspan="4" |G3F19
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI3_TX_SYNCUART4_RX
|-
|ALT1
|GPT1_CLKUART2_CTS_B
|-
|ALT2
|SAI5_RX_DATA1PCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO4_IO31GPIO5_IO28
|-
| rowspan="3" |J1.42195| rowspan="3" |SPDIF_RXECSPI1_MOSI| rowspan="3" |CPU.SPDIF_RXECSPI1_MOSI| rowspan="3" |G6B7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_INECSPI1_MOSI
|-
|ALT1
|PWM2_OUTUART3_TX
|-
|ALT5
|GPIO5_IO04GPIO5_IO07
|-
| rowspan="35" |J1.44197| rowspan="35" |SPDIF_TXGPIO1_IO14| rowspan="35" |CPU.SPDIF_TXGPIO1_IO14| rowspan="35" |F6AC9| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|SPDIF1_OUTGPIO1_IO14
|-
|ALT1
|PWM3_OUTUSB2_OTG_PWR|-|ALT4|USDHC3_CD_B(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|GPIO5_IO03PWM3_OUT
|-
|ALT6|CCM_CLKO1|-| rowspan="43" |J1.46199| rowspan="43" |SAI3_MCLKGPIO1_IO04| rowspan="43" |CPU.SAI3_MCLKGPIO1_IO04| rowspan="43" |D3AG12| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI3_MCLKGPIO1_IO04
|-
|ALT1
|PWM4_OUT|-|ALT2|SAI5_MCLKUSDHC2_VSELECT
|-
|ALT5
|GPIO5_IO02SDMA1_EXT_EVENT1
|-
| rowspan="43" |J1.48201| rowspan="43" |I2C3_SDAGPIO1_IO12| rowspan="43" |CPU.I2C3_SDAGPIO1_IO12| rowspan="43" |E9AB10| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|I2C3_SDAGPIO1_IO12
|-
|ALT1
|PWM3_OUT|-|ALT2|GPT3_CLKUSB1_OTG_PWR
|-
|ALT5
|GPIO5_IO19SDMA2_EXT_EVENT1
|-
| rowspan="4" |J1.50203| rowspan="4" |SAI3_TXCDGND | rowspan="4" |CPU.SAI3_TXCDGND| rowspan="4" |C4-| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OG| rowspan="4" ||ALT0|SAI3_TX_BCLK
|-
|ALT1} ==SODIMM J1 EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" |GPT1_COMPARE2Alternative Functions
|-
|ALT2J1.2|DGND|DGND| -|<nowiki>-</nowiki>|G|||SAI5_RX_DATA2
|-
|ALT5J1.4|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S|||GPIO5_IO00
|-
| rowspan="4" |J1.526| rowspan="4" |SAI3_TXD3.3VIN | rowspan="4" |CPU.SAI3_TXDINPUT VOLTAGE| rowspan="4" |C3-| rowspan="4" |NVCC_3V33.3VIN| rowspan="4" |I/OS| rowspan="4" ||ALT0|SAI3_TX_DATA0
|-
|ALT1|GPT1_COMPARE3|-|ALT2|SAI5_RX_DATA3|-|ALT5|GPIO5_IO01|-| rowspan="2" |J1.548| rowspan="2" |GPIO1_IO10| rowspan="2" |CPU3.GPIO1_IO10| rowspan="2" |M7| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0|GPIO1_IO10|-|ALT1|USB1_OTG_ID|-|J1.56|DGND3VIN |DGNDINPUT VOLTAGE
| -
|<nowiki>-</nowiki>3.3VIN|GS
|
|
|
|-
| rowspan="4" |J1.5810| rowspan="4" |SAI5_MCLK3.3VIN | rowspan="4" |CPU.SAI5_MCLKINPUT VOLTAGE| rowspan="4" |K4-| rowspan="4" |NVCC_3V33.3VIN| rowspan="4" |I/OS| rowspan="4" ||ALT0|SAI5_MCLK
|-
|ALT1J1.12|DGND|DGND| -|<nowiki>-</nowiki>|G|||SAI1_TX_BCLK
|-
|ALT2J1.14|PMIC_LICELL |PMIC.LICELL|46| -|S|||SAI4_MCLK
|-
|ALT5J1.16|CPU_ONOFF|CPU.ONOFF|A25|NVCC_SNVS_1V8|I|internal pull-up 100k to NVCC_SNVS_1V8||GPIO3_IO25
|-
| rowspan="4" |J1.6018| rowspan="4" |GPIO1_IO15BOARD_PGOOD| rowspan="4" |CPU.GPIO1_IO15-| rowspan="4" |J6-| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO15
|-
|ALT1J1.20|BOOT_MODE_SEL|BOOT MODE SELECTION| -|NVCC_3V3|I|internal pull-up to NVCC_3V3||USB2_OTG_OC
|-
|ALT5J1.22|CPU_PORn|CPU.POR_BPMIC.RESET_MCU|B2421|NVCC_SNVS_1V8|I/O|internal pull-up 100k to NVCC_SNVS_1V8||PWM4_OUT
|-
|ALT6J1.24|PMIC_PWRON|PMIC.PWRON| 22| '''(*)''' 3.3VIN|I|internal pull-up 100k to VIN'''(*)''' default as ''Embedded'' power mode||CCM_CLKO2
|-
| rowspan="35" |J1.6226| rowspan="35" |SAI5_RXFSSAI3_RXC| rowspan="35" |CPU.SAI5_RXFSSAI3_RXC| rowspan="35" |N4AG7| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|SAI5_RX_SYNCSAI3_RX_BCLK
|-
|ALT1
|SAI1_TX_DATA0GPT1_CLK
|-
|ALT5|GPIO3_IO19|-| rowspan="3" |J1.64| rowspan="3" |SAI5_RXC| rowspan="3" |CPU.SAI5_RXC| rowspan="3" |L5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0ALT2
|SAI5_RX_BCLK
(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2)
|-
|ALT1ALT4|SAI1_TX_DATA1UART2_CTS_B
|-
|ALT5
|GPIO3_IO20GPIO4_IO29
|-
| rowspan="34" |J1.6628| rowspan="34" |SAI2_TXCGPIO1_IO02| rowspan="34" |CPU.SAI2_TXCGPIO1_IO02| rowspan="34" |J5AG13| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |Internally used for PMIC WDI, do not connect
|ALT0
|SAI2_TX_BCLKGPIO1_IO02
|-
|ALT1
|SAI5_TX_DATA2WDOG1_WDOG_B
|-
|ALT5
|GPIO4_IO25WDOG1_WDOG_ANY
|-
| rowspan="3" |J1.68| rowspan="3" |SAI2_TXD0| rowspan="3" |CPU.SAI2_TXD0| rowspan="3" |G5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0ALT7|SAI2_TX_DATA0SJC_DE_B
|-
|ALT1J1.30|SAI5_TX_DATA3DGND|DGND|-|ALT5<nowiki>-</nowiki>|G|||GPIO4_IO26
|-
| rowspan="35" |J1.7032| rowspan="35" |SAI2_TXFSSAI3_RXD| rowspan="35" |CPU.SAI2_TXFSSAI3_RXD| rowspan="35" |H4AF7| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|SAI2_TX_SYNCSAI3_RX_DATA0
|-
|ALT1
|SAI5_TX_DATA1GPT1_COMPARE1|-|ALT2|SAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT2)|-|ALT4|UART2_RTS_B(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|GPIO4_IO24GPIO4_IO30
|-
| rowspan="3" |J1.7234| rowspan="3" |SAI2_RXD0SAI2_MCLK| rowspan="3" |CPU.SAI2_RXD0SAI2_MCLK| rowspan="3" |H6AD19
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI2_RX_DATA0SAI2_MCLK
|-
|ALT1
|SAI5_TX_DATA0SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO4_IO23GPIO4_IO27
|-
| rowspan="3" |J1.74| rowspan="3" |SAI5_RXD0| rowspan="3" |CPU.SAI5_RXD0| rowspan="3" |M5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_DATA0 |-|ALT1|SAI1_TX_DATA2|-|ALT5|GPIO3_IO21|-| rowspan="5" |J1.7636| rowspan="5" |SAI5_RXD1SAI3_RXFS| rowspan="5" |CPU.SAI5_RXD1SAI3_RXFS| rowspan="5" |L4AG8| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
|ALT0
|SAI5_RX_DATA1SAI3_RX_SYNC
|-
|ALT1
|SAI1_TX_DATA3GPT1_CAPTURE1
|-
|ALT2
|SAI1_TX_SYNCSAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT2)
|-
|ALT3
|SAI5_TX_SYNCSAI3_RX_DATA1
|-
|ALT5
|GPIO3_IO212GPIO4_IO28
|-
| rowspan="54" |J1.7838| rowspan="54" |SAI5_RXD2I2C3_SCL| rowspan="54" |CPU.SAI5_RXD2I2C3_SCL| rowspan="54" |M4E10| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |
|ALT0
|SAI5_RX_DATA2I2C3_SCL
|-
|ALT1
|SAI1_TX_DATA4PWM4_OUT
|-
|ALT2
|SAI1_TX_SYNC|-|ALT3|SAI5_TX_BCLKGPT2_CLK
|-
|ALT5
|GPIO3_IO23GPIO5_IO18
|-
| rowspan="56" |J1.8040| rowspan="56" |SAI5_RXD3SAI3_TXFS| rowspan="56" |CPU.SAI5_RXD3SAI3_TXFS| rowspan="56" |K5AC6| rowspan="56" |NVCC_3V3| rowspan="56" |I/O| rowspan="56" |
|ALT0
|SAI5_RX_DATA3SAI3_TX_SYNC
|-
|ALT1
|SAI1_TX_DATA5GPT1_CAPTURE2
|-
|ALT2
|SAI1_TX_SYNCSAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT2)
|-
|ALT3
|SAI5_TX_DATA0SAI3_TX_DATA1|-|ALT4|UART2_RX
|-
|ALT5
|GPIO3_IO24GPIO4_IO31
|-
| rowspan="3" |J1.8242|DGNDrowspan="3" |SPDIF_RX|DGNDrowspan="3" |CPU.SPDIF_RX| -rowspan="3" |AG9| rowspan="3" |NVCC_3V3|<nowiki>-<rowspan="3" |I/nowiki>O| rowspan="3" ||ALT0|GSPDIF1_IN|-|ALT1|PWM2_OUT
|-
|J1.84|CLK2_N|CPU.CLK2_N|T22|VDDA_1V8|D|Internally used for PCIe CLK, do not connect|ALT5|GPIO5_IO04
|-
| rowspan="3" |J1.8644|CLK2_Prowspan="3" |SPDIF_TX| rowspan="3" |CPU.CLK2_PSPDIF_TX|U22rowspan="3" |AF9|VDDA_1V8rowspan="3" |NVCC_3V3|Drowspan="3" |I/O|Internally used for PCIe CLK, do not connectrowspan="3" ||ALT0|SPDIF1_OUT
|-
|J1.88|PCIE1_REF_CLKN|CPU.PCIE1_REF_PAD_CLK_N|K24|VDD_PHY_3V3|D||ALT1|PWM3_OUT
|-
|J1.90|PCIE1_REF_CLKP|CPU.PCIE1_REF_PAD_CLK_P|K25|VDD_PHY_3V3|D||ALT5|GPIO5_IO03
|-
| rowspan="4" |J1.9246|PCIE1_RXNrowspan="4" |SAI3_MCLK| rowspan="4" |CPU.PCIE1_RXN_NSAI3_MCLK|H24rowspan="4" |AD6|VDD_PHY_3V3rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_MCLK
|-
|J1.94|PCIE1_RXP|CPU.PCIE1_RXN_P|H25|VDD_PHY_3V3|D||ALT1|PWM4_OUT
|-
|J1.96ALT2|PCIE1_TXNSAI5_MCLK|CPU.PCIE1_TXN_N|J24|VDD_PHY_3V3|D|||(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT2)
|-
|J1.98|PCIE1_TXP|CPU.PCIE1_TXN_P|J25|VDD_PHY_3V3|D||ALT5|GPIO5_IO02
|-
| rowspan="4" |J1.10048|DGNDrowspan="4" |I2C3_SDA| rowspan="4" |CPU.I2C3_SDA|DGNDrowspan="4" |F10| -rowspan="4" |NVCC_3V3|<nowiki>-<rowspan="4" |I/nowiki>O|Growspan="4" ||ALT0|I2C3_SDA
|-
|J1.102|CSI1_CLK_N|CPU.MIPI_CSI1_CLK_N|A22| -|D||ALT1|PWM3_OUT
|-
|J1.104ALT2|CSI1_CLK_P|CPU.MIPI_CSI1_CLK_P|B22GPT3_CLK| -|D||ALT5|GPIO5_IO19
|-
| rowspan="5" |J1.10650|CSI1_D0_Nrowspan="5" |SAI3_TXC| rowspan="5" |CPU.MIPI_CSI1_D0_NSAI3_TXC|A23rowspan="5" |AG6| -rowspan="5" |NVCC_3V3|Drowspan="5" |I/O| rowspan="5" ||ALT0|SAI3_TX_BCLK
|-
|J1.108|CSI1_D0_P|CPU.MIPI_CSI1_D0_P|B23| -|D||ALT1|GPT1_COMPARE2
|-
|J1.110ALT2|CSI1_D1_NSAI5_RX_DATA2|CPU.MIPI_CSI1_D1_N|C22| -|D|||(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT2)
|-
|J1.112|CSI1_D1_P|CPU.MIPI_CSI1_D1_P|D22| -|D||ALT4|UART2_TX
|-
|J1.114|CSI1_D2_N|CPU.MIPI_CSI1_D2_N|B24| -|D||ALT5|GPIO5_IO00
|-
| rowspan="4" |J1.11652|CSI1_D2_Prowspan="4" |SAI3_TXD| rowspan="4" |CPU.MIPI_CSI1_D2_PSAI3_TXD| rowspan="4" |AF6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_DATA0|-|ALT1|C23GPT1_COMPARE3| -|DALT2|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT2)|-|ALT5|GPIO5_IO01
|-
| rowspan="5" |J1.11854|CSI1_D3_Nrowspan="5" |SAI1_MCLK| rowspan="5" |CPU.MIPI_CSI1_D3_NSAI1_MCLK| rowspan="5" |AB18| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI1_MCLK|-|ALT1|SAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI1_TX_BCLK(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT3|PDM_CLK|-|ALT5|GPIO4_IO20|-|J1.56|DGND|C21DGND
| -
|D<nowiki>-</nowiki>|G
|
|
|
|-
|J1.120|CSI1_D3_P|CPU.MIPI_CSI1_D3_P|D21| -|D||||-|J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J1.124(NAND on board)|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.124(eMMC on board)58| rowspan="3" |NAND_DQSSAI5_MCLK| rowspan="3" |CPU.NAND_DQSSAI5_MCLK| rowspan="3" |M20AD15| rowspan="3" |NVCC_3V3| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DQSSAI5_MCLK(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT0)
|-
|ALT1
|QSPI_A_DQSSAI1_TX_BCLK(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO3_IO14GPIO3_IO25|-| rowspan="2" |J1.60| rowspan="2" |GPIO1_IO10| rowspan="2" |CPU.GPIO1_IO10| rowspan="2" |AD10| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0|GPIO1_IO10
|-
|J1.126(NAND on board)|NAND_ALE|CPU.NAND_ALE|G19|NVCC_3V3|I/O|Internally used for NAND, do not connect|ALT1|USB1_OTG_ID
|-
| rowspan="3" |J1.126(eMMC on board)62| rowspan="3" |NAND_ALESAI5_RXFS| rowspan="3" |CPU.NAND_ALESAI5_RXFS| rowspan="3" |G19AB15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_ALESAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT0)
|-
|ALT1
|QSPI_A_SCLKSAI1_TX_DATA0
|-
|ALT5
|GPIO3_IO00GPIO3_IO19
|-
| rowspan="24" |J1.128(NAND on board)64| rowspan="24" |SD1_CLKSAI5_RXC| rowspan="24" |CPU.SD1_CLKSAI5_RXC| rowspan="24" |L25AC15| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_CLKSAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT0)|-|ALT1|SAI1_TX_DATA1|-|ALT4|PDM_CLK
|-
|ALT5
|GPIO2_IO00GPIO3_IO20
|-
| rowspan="3" |J1.128(eMMC on board)66| rowspan="3" |NAND_CE0_BSAI2_TXC| rowspan="3" |CPU.NAND_CE0_BSAI2_TXC| rowspan="3" |H19AD22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE0_BSAI2_TX_BCLK
|-
|ALT1
|QSPI_A_SS0_BSAI5_TX_DATA2
|-
|ALT5
|GPIO3_IO01GPIO4_IO25
|-
| rowspan="2" |J1.130(NAND on board)| rowspan="2" |SD1_CMD| rowspan="2" |CPU.SD1_CMD| rowspan="2" |L24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_CMD|-|ALT5|GPIO2_IO01|-| rowspan="3" |J1.130(eMMC on board)68| rowspan="3" |NAND_CE1_BSAI2_TXD0| rowspan="3" |CPU.NAND_CE1_BSAI2_TXD0| rowspan="3" |G21AC22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE1_BSAI2_TX_DATA0
|-
|ALT1
|QSPI_A_SS1_BSAI5_TX_DATA3
|-
|ALT5
|GPIO3_IO02GPIO4_IO26
|-
| rowspan="25" |J1.132(NAND on board)70| rowspan="25" |SD1_RST_BSAI2_TXFS| rowspan="25" |CPU.SD1_RST_BSAI2_TXFS| rowspan="25" |R24AD23| rowspan="25" |NVCC_3V3(NVCC_1V8 on request)| rowspan="25" |I/O| rowspan="25" |
|ALT0
|USDHC1_RESET_BSAI2_TX_SYNC|-|ALT1|SAI5_TX_DATA1|-|ALT3|SAI2_TX_DATA1|-|ALT4|UART1_CTS_B
|-
|ALT5
|GPIO2_IO10GPIO4_IO24|-| rowspan="4" |J1.72| rowspan="4" |SAI2_RXD0| rowspan="4" |CPU.SAI2_RXD0| rowspan="4" |AC24| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI2_RX_DATA0|-|ALT1|SAI5_TX_DATA0|-|ALT4|UART1_RTS_B(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT4)|-|ALT5|GPIO4_IO23
|-
| rowspan="3" |J1.132(eMMC on board)74| rowspan="3" |NAND_CE2_BI2C4_SDA| rowspan="3" |CPU.NAND_CE2_BI2C4_SDA| rowspan="3" |F21E13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_CE2_BI2C4_SDA
|-
|ALT1
|QSPI_B_SS0_BPWM1_OUT
|-
|ALT5
|GPIO3_IO03GPIO5_IO21
|-
| rowspan="24" |J1.134(NAND on board)76| rowspan="24" |SD1_STROBEI2C4_SCL| rowspan="24" |CPU.SD1_STROBEI2C4_SCL| rowspan="24" |T24D13| rowspan="24" |NVCC_3V3(NVCC_1V8 on request)| rowspan="24" |I/O| rowspan="24" |
|ALT0
|USDHC1_STROBEI2C4_SCL|-|ALT1|PWM2_OUT|-|ALT2|PCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO2_IO11GPIO5_IO20
|-
| rowspan="36" |J1.134(eMMC on board)78| rowspan="36" |NAND_CE3_BSAI5_RXD2| rowspan="36" |CPU.NAND_CE3_BSAI5_RXD2| rowspan="36" |H20AD13| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|RAWNAND_CE3_BSAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT0)
|-
|ALT1
|QSPI_B_SS1_BSAI1_TX_DATA4|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT3)|-|ALT4|PDM_BIT_STREAM2(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT4)
|-
|ALT5
|GPIO3_IO034GPIO3_IO23|-| rowspan="6" |J1.80| rowspan="6" |SAI5_RXD3| rowspan="6" |CPU.SAI5_RXD3| rowspan="6" |AC13| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" ||ALT0|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT0)
|-
|J1.136(NAND on board)ALT1|NAND_CLESAI1_TX_DATA5|CPU.NAND_CLE-|H21ALT2|NVCC_3V3SAI1_TX_SYNC|I/O|Internally used (Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for NAND, do not connect||mode ALT2)
|-
| rowspan="3" |J1.136(eMMC on board)| rowspan="3" |NAND_CLE| rowspan="3" |CPU.NAND_CLE| rowspan="3" |H21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0ALT3|RAWNAND_CLESAI5_TX_DATA0
|-
|ALT1ALT4|QSPI_B_SCLKPDM_BIT_STREAM3(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT4)
|-
|ALT5
|GPIO3_IO05GPIO3_IO24
|-
| rowspan="2" |J1.138(NAND on board)| rowspan="2" |SD1_DATA082| rowspan="2" |CPU.SD1_DATA0DGND| rowspan="2" |M25DGND| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I<nowiki>-</Onowiki>| rowspan="2" G||ALT0|USDHC1_DATA0
|-
|ALT5J1.84|PCIE1_REF_CLKN|CPU.PCIE_REF_CLK_N|A21|VDDA_1V8|D|||GPIO2_IO02
|-
| rowspan="3" |J1.138(eMMC on board)86| rowspan="3" |NAND_DATA00PCIE1_REF_CLKP| rowspan="3" |CPU.NAND_DATA00PCIE_REF_CLK_P| rowspan="3" |G20B21| rowspan="3" |NVCC_3V3VDDA_1V8| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA00
|-
|ALT1J1.88|CLKIN1|CPU.CLKIN1|H27|NVCC_3V3|I|||QSPI_A_DATA0
|-
|ALT5J1.90|CLKIN2|CPU.CLKIN2|J27|NVCC_3V3|I|||GPIO3_IO06
|-
| rowspan="2" |J1.140(NAND on board)92| rowspan="2" |SD1_DATA1PCIE1_RXN| rowspan="2" |CPU.SD1_DATA1PCIE_RXN_N| rowspan="2" |M24A19| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)VDDA_1V8| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA1
|-
|ALT5J1.94|PCIE1_RXP|CPU.PCIE_RXN_P|B19|VDDA_1V8|D|||GPIO2_IO0
|-
| rowspan="3" |J1.140(eMMC on board)96| rowspan="3" |NAND_DATA01PCIE1_TXN| rowspan="3" |CPU.NAND_DATA01PCIE_TXN_N| rowspan="3" |J20A20| rowspan="3" |NVCC_3V3VDDA_1V8| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA01
|-
|ALT1J1.98|PCIE1_TXP|CPU.PCIE_TXN_P|B20|VDDA_1V8|D|||QSPI_A_DATA1
|-
|ALT5J1.100|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO3_IO07
|-
| rowspan="2" |J1.142(NAND on board)102| rowspan="2" |SD1_DATA2CSI_P1_CKN| rowspan="2" |CPU.SD1_DATA2MIPI_CSI_CLK_N| rowspan="2" |N25A16| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA2
|-
|ALT5J1.104|CSI_P1_CKP|CPU.MIPI_CSI_CLK_P|B16| -|D|||GPIO2_IO04
|-
| rowspan="3" |J1.142(eMMC on board)106| rowspan="3" |NAND_DATA02CSI_P1_DN0| rowspan="3" |CPU.NAND_DATA02MIPI_CSI_D0_N| rowspan="3" |H22A14| rowspan="3" |NVCC_3V3-| rowspan="3" |I/OD| rowspan="3" ||ALT0|RAWNAND_DATA02
|-
|ALT1J1.108|CSI_P1_DP0|CPU.MIPI_CSI_D0_P|B14| -|D|||QSPI_A_DATA2
|-
|ALT5J1.110|CSI_P1_DN1|CPU.MIPI_CSI_D1_N|A15| -|D|||GPIO3_IO08
|-
| rowspan="2" |J1.144(NAND on board)112| rowspan="2" |SD1_DATA3CSI_P1_DP1| rowspan="2" |CPU.SD1_DATA3MIPI_CSI_D1_P| rowspan="2" |P25B15| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA3
|-
|ALT5J1.114|CSI_P1_DN2|CPU.MIPI_CSI_D2_N|A17| -|D|||GPIO2_IO05
|-
| rowspan="3" |J1.144(eMMC on board)116| rowspan="3" |NAND_DATA03CSI_P1_DP2| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.146|DGNDMIPI_CSI_D2_P|DGNDB17
| -
|<nowiki>-</nowiki>|GD
|
|
|
|-
| rowspan="2" |J1.148(NAND on board)118| rowspan="2" |SD1_DATA4CSI_P1_DN3| rowspan="2" |CPU.SD1_DATA4MIPI_CSI_D3_N| rowspan="2" |N24A18| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)-| rowspan="2" |I/OD| rowspan="2" ||ALT0|USDHC1_DATA4
|-
|ALT5J1.120|CSI_P1_DP3|CPU.MIPI_CSI_D3_P|B18| -|D|||GPIO2_IO06
|-
| rowspan="3" |J1.148122(eMMC on board)| rowspan="3" |NAND_DATA04DGND| rowspan="3" |CPU.NAND_DATA04DGND| rowspan="3" |L20-| rowspan="3" |NVCC_3V3<nowiki>-</nowiki>| rowspan="3" |I/OG| rowspan="3" ||ALT0|RAWNAND_DATA04
|-
|ALT1|QSPI_B_DATA0|-|ALT5|GPIO3_IO10|-| rowspan="2" |J1.150124
(NAND on board)
| rowspan="2" |SD1_DATA5NAND_DQS| rowspan="2" |CPU.SD1_DATA5NAND_DQS| rowspan="2" |P24R22| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" |Internally used for NAND, do not connect|ALT0|USDHC1_DATA5
|-
|ALT5|GPIO2_IO07|-| rowspan="3" |J1.150124
(eMMC on board)
| rowspan="3" |NAND_DATA05NAND_DQS| rowspan="3" |CPU.NAND_DATA05NAND_DQS| rowspan="3" |J22R22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA05RAWNAND_DQS
|-
|ALT1
|QSPI_B_DATA1QSPI_A_DQS
|-
|ALT5
|GPIO3_IO11GPIO3_IO14
|-
| rowspan="2" |J1.152126
(NAND on board)
| rowspan="2" |SD1_DATA6NAND_ALE| rowspan="2" |CPU.SD1_DATA6NAND_ALE| rowspan="2" |R25N22| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" |Internally used for NAND, do not connect|ALT0|USDHC1_DATA6
|-
|ALT5|GPIO2_IO08|-| rowspan="3" |J1.152126
(eMMC on board)
| rowspan="3" |NAND_DATA06NAND_ALE| rowspan="3" |CPU.NAND_DATA06NAND_ALE| rowspan="3" |L19N22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA06RAWNAND_ALE
|-
|ALT1
|QSPI_B_DATA2QSPI_A_SCLK
|-
|ALT5
|GPIO3_IO12GPIO3_IO00
|-
| rowspan="2" |J1.154128
(NAND on board)
| rowspan="2" |SD1_DATA7SD1_CLK| rowspan="2" |CPU.SD1_DATA7SD1_CLK| rowspan="2" |T25V26
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |
|ALT0
|USDHC1_DATA7USDHC1_CLK
|-
|ALT5
|GPIO2_IO09GPIO2_IO00
|-
| rowspan="3" |J1.154128
(eMMC on board)
| rowspan="3" |NAND_DATA07NAND_CE0_B| rowspan="3" |CPU.NAND_DATA07NAND_CE0_B| rowspan="3" |M19N24
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DATA07RAWNAND_CE0_B
|-
|ALT1
|QSPI_B_DATA3QSPI_A_SS0_B
|-
|ALT5
|GPIO3_IO13GPIO3_IO01
|-
| rowspan="2" |J1.156130
(NAND on board)
|NAND_RE_Browspan="2" |SD1_CMD| rowspan="2" |CPU.NAND_RE_BSD1_CMD|K19rowspan="2" |V27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|Internally used for NAND, do not connectrowspan="2" ||ALT0|USDHC1_CMD
|-
|ALT5|GPIO2_IO01|-| rowspan="34" |J1.156130(eMMC on board)| rowspan="34" |NAND_RE_BNAND_CE1_B| rowspan="34" |CPU.NAND_RE_BNAND_CE1_B| rowspan="34" |K19P27| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|RAWNAND_RE_BRAWNAND_CE1_B
|-
|ALT1
|QSPI_B_DQSQSPI_A_SS1_B|-|ALT2|USDHC3_STROBE
|-
|ALT5
|GPIO3_IO15GPIO3_IO02
|-
| rowspan="2" |J1.158132
(NAND on board)
|NAND_READY_B|CPU.NAND_READY_B|K20|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="2" |J1.158(eMMC on board)| rowspan="2" |NAND_READY_BSD1_RST_B| rowspan="2" |CPU.NAND_READY_BSD1_RST_B| rowspan="2" |K20R23
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_READY_BUSDHC1_RESET_B
|-
|ALT5
|GPIO3_IO16GPIO2_IO10
|-
| rowspan="4" |J1.160132(eMMC on board)| rowspan="4" |NAND_CE2_B| rowspan="4" |CPU.NAND_CE2_B| rowspan="4" |M27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_CE2_B|-|ALT1|QSPI_B_SS0_B|-|ALT2|USDHC3_DATA5|-|ALT5|GPIO3_IO03|-| rowspan="2" |J1.134
(NAND on board)
|NAND_WE_B|CPU.NAND_WE_B|K22|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="2" |J1.160(eMMC on board)| rowspan="2" |NAND_WE_BSD1_STROBE| rowspan="2" |CPU.NAND_WE_BSD1_STROBE| rowspan="2" |K22R24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WE_BUSDHC1_STROBE
|-
|ALT5
|GPIO3_IO17GPIO2_IO11
|-
| rowspan="4" |J1.162134(eMMC on board)| rowspan="4" |NAND_CE3_B| rowspan="4" |CPU.NAND_CE3_B| rowspan="4" |L27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_CE3_B|-|ALT1|QSPI_B_SS1_B|-|ALT2|USDHC3_DATA6|-|ALT5|GPIO3_IO034|-|J1.136
(NAND on board)
|NAND_WP_BNAND_CLE|CPU.NAND_WP_BNAND_CLE|K21K27
|NVCC_3V3
|I/O
|
|-
| rowspan="24" |J1.162136
(eMMC on board)
| rowspan="24" |NAND_WP_BNAND_CLE| rowspan="24" |CPU.NAND_WP_BNAND_CLE| rowspan="24" |K21K27| rowspan="24" |NVCC_3V3| rowspan="24" |I/O| rowspan="24" |
|ALT0
|RAWNAND_WP_BRAWNAND_CLE|-|ALT1|QSPI_B_SCLK|-|ALT2|USDHC3_DATA7
|-
|ALT5
|GPIO3_IO18GPIO3_IO05
|-
| rowspan="2" |J1.164138(NAND on board)| rowspan="2" |SD1_DATA0|DGNDrowspan="2" |CPU.SD1_DATA0|DGNDrowspan="2" |Y27| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|<nowiki>-<rowspan="2" |I/nowiki>O|Growspan="2" ||ALT0|USDHC1_DATA0
|-
|J1.166|CLK1_N|CPU.CLK1_N|T23||D||ALT5|GPIO2_IO02
|-
| rowspan="3" |J1.168138(eMMC on board)|CLK1_Prowspan="3" |NAND_DATA00| rowspan="3" |CPU.CLK1_PNAND_DATA00|R23rowspan="3" |P23|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA00
|-
|J1.170|USB2_RXN|CPU.USB2_RX_N|B8||D||ALT1|QSPI_A_DATA0
|-
|J1.172|USB2_RXP|CPU.USB2_RX_P|A8||D||ALT5|GPIO3_IO06
|-
| rowspan="2" |J1.174140(NAND on board)|USB2_TXNrowspan="2" |SD1_DATA1| rowspan="2" |CPU.USB2_TX_NSD1_DATA1|B9rowspan="2" |Y26|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA1
|-
|J1.176|USB2_TXP|CPU.USB2_TX_P|A9||D||ALT5|GPIO2_IO0
|-
| rowspan="3" |J1.178140(eMMC on board)|USB1_RXNrowspan="3" |NAND_DATA01| rowspan="3" |CPU.USB1_RX_NNAND_DATA01|B12rowspan="3" |K24|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA01
|-
|J1.180|USB1_RXP|CPU.USB1_RX_P|A12||D||ALT1|QSPI_A_DATA1
|-
|ALT5|GPIO3_IO07|-| rowspan="2" |J1.142(NAND on board)| rowspan="2" |SD1_DATA2| rowspan="2" |CPU.SD1_DATA2| rowspan="2" |T27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA2|-|ALT5|GPIO2_IO04|-| rowspan="4" |J1.142(eMMC on board)| rowspan="4" |NAND_DATA02| rowspan="4" |CPU.NAND_DATA02| rowspan="4" |K23| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA02|-|ALT1|QSPI_A_DATA2|-|ALT2|USDHC3_CD_B(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO3_IO08|-| rowspan="2" |J1.144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |T26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="4" |J1.144(eMMC on board)| rowspan="4" |NAND_DATA03| rowspan="4" |CPU.NAND_DATA03| rowspan="4" |N23| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT2|USDHC3_WP(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO3_IO09|-|J1.146|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="2" |J1.148(NAND on board)| rowspan="2" |SD1_DATA4| rowspan="2" |CPU.SD1_DATA4| rowspan="2" |U27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4|-|ALT5|GPIO2_IO06|-| rowspan="4" |J1.148(eMMC on board)| rowspan="4" |NAND_DATA04| rowspan="4" |CPU.NAND_DATA04| rowspan="4" |M26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA04|-|ALT1|QSPI_B_DATA0|-|ALT2|USDHC3_DATA0|-|ALT5|GPIO3_IO10|-| rowspan="2" |J1.150(NAND on board)| rowspan="2" |SD1_DATA5| rowspan="2" |CPU.SD1_DATA5| rowspan="2" |U26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA5|-|ALT5|GPIO2_IO07|-| rowspan="4" |J1.150(eMMC on board)| rowspan="4" |NAND_DATA05| rowspan="4" |CPU.NAND_DATA05| rowspan="4" |L26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA05|-|ALT1|QSPI_B_DATA1|-|ALT2|USDHC3_DATA1|-|ALT5|GPIO3_IO11|-| rowspan="2" |J1.152(NAND on board)| rowspan="2" |SD1_DATA6| rowspan="2" |CPU.SD1_DATA6| rowspan="2" |W27| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA6|-|ALT5|GPIO2_IO08|-| rowspan="4" |J1.152(eMMC on board)| rowspan="4" |NAND_DATA06| rowspan="4" |CPU.NAND_DATA06| rowspan="4" |K26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA06|-|ALT1|QSPI_B_DATA2|-|ALT2|USDHC3_DATA2|-|ALT5|GPIO3_IO12|-| rowspan="2" |J1.154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |W26| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09|-| rowspan="4" |J1.154(eMMC on board)| rowspan="4" |NAND_DATA07| rowspan="4" |CPU.NAND_DATA07| rowspan="4" |N26| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT2|USDHC3_DATA3|-|ALT5|GPIO3_IO13|-|J1.156(NAND on board)|NAND_RE_B|CPU.NAND_RE_B|N27|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="4" |J1.156(eMMC on board)| rowspan="4" |NAND_RE_B| rowspan="4" |CPU.NAND_RE_B| rowspan="4" |N27| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|RAWNAND_RE_B|-|ALT1|QSPI_B_DQS|-|ALT2|USDHC3_DATA4|-|ALT5|GPIO3_IO15|-|J1.158(NAND on board)|NAND_READY_B|CPU.NAND_READY_B|P26|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.158(eMMC on board)| rowspan="3" |NAND_READY_B| rowspan="3" |CPU.NAND_READY_B| rowspan="3" |P26| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_READY_B|-|ALT2|USDHC3_RESET_B|-|ALT5|GPIO3_IO16|-|J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|R26|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.160(eMMC on board)| rowspan="3" |NAND_WE_B| rowspan="3" |CPU.NAND_WE_B| rowspan="3" |R26| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_WE_B|-|ALT2|USDHC3_CLK|-|ALT5|GPIO3_IO17|-|J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|R27|NVCC_3V3|I/O|Internally used for NAND, do not connect|||-| rowspan="3" |J1.162(eMMC on board)| rowspan="3" |NAND_WP_B| rowspan="3" |CPU.NAND_WP_B| rowspan="3" |R27| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_WP_B|-|ALT2|USDHC3_CMD|-|ALT5|GPIO3_IO18|-|J1.164|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="5" |J1.166| rowspan="5" |GPIO1_IO15| rowspan="5" |CPU.GPIO1_IO15| rowspan="5" |AB9| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|GPIO1_IO15|-|ALT1|USB2_OTG_OC|-|ALT4|USDHC3_WP(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT4)|-|ALT5|PWM4_OUT|-|ALT6|CCM_CLKO2|-| rowspan="4" |J1.168| rowspan="4" |GPIO1_IO07| rowspan="4" |CPU.GPIO1_IO07| rowspan="4" |AF11| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO07|-|ALT1|ENET1_MDIO(Configure register IOMUXC_ENET1_MDIO_SELECT_INPUT for mode ALT1)|-|ALT5|USDHC1_WP|-|ALT6|CCM_EXT_CLK4|-| rowspan="6" |J1.170| rowspan="6" |SAI1_TXD4| rowspan="6" |CPU.SAI1_TXD4| rowspan="6" |AG22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA4|-|ALT1|SAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_BCLK(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE12|-|ALT5|GPIO4_IO16|-|ALT6|SRC_BOOT_CFG12|-| rowspan="6" |J1.172| rowspan="6" |SAI1_TXD5| rowspan="6" |CPU.SAI1_TXD5| rowspan="6" |AF22| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA5|-|ALT1|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT1)|-|ALT2|SAI6_TX_DATA0|-|ALT4|CORESIGHT_TRACE13|-|ALT5|GPIO4_IO17|-|ALT6|SRC_BOOT_CFG13|-| rowspan="6" |J1.174| rowspan="6" |SAI1_TXD6| rowspan="6" |CPU.SAI1_TXD6| rowspan="6" |AG23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA6|-|ALT1|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE14|-|ALT5|GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14|-| rowspan="6" |J1.176| rowspan="6" |SAI1_TXD7| rowspan="6" |CPU.SAI1_TXD7| rowspan="6" |AF23| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_TX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT3|PDM_CLK|-|ALT4|CORESIGHT_TRACE15|-|ALT5|GPIO4_IO19|-|ALT6|SRC_BOOT_CFG15|-| rowspan="7" |J1.178| rowspan="7" |SAI1_RXD7| rowspan="7" |CPU.SAI1_RXD7| rowspan="7" |AF19| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA7|-|ALT1|SAI6_MCLK(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI1_TX_DATA4|-|ALT4|CORESIGHT_TRACE7|-|ALT5|GPIO4_IO09|-|ALT6|SRC_BOOT_CFG7|-| rowspan="6" |J1.180| rowspan="6" |SAI1_RXD6| rowspan="6" |CPU.SAI1_RXD6| rowspan="6" |AG19| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA6|-|ALT1|SAI6_TX_SYNC(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT2|SAI6_RX_SYNC(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE6|-|ALT5|GPIO4_IO08|-|ALT6|SRC_BOOT_CFG6|-| rowspan="7" |J1.182|USB1_TXNrowspan="7" |SAI1_RXD5| rowspan="7" |CPU.USB1_TX_NSAI1_RXD5|B13rowspan="7" |AF18| rowspan="7" |NVCC_3V3|rowspan="7" |I/O|Drowspan="7" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA5|-|ALT1|SAI6_TX_DATA0|-|ALT2|SAI6_RX_DATA0(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT2)|-|ALT3|SAI1_RX_SYNC(Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT3)|-|ALT4|CORESIGHT_TRACE5|-|ALT5|GPIO4_IO07|-|ALT6|SRC_BOOT_CFG|-| rowspan="6" |J1.184|USB1_TXProwspan="6" |SAI1_RXD4| rowspan="6" |CPU.USB1_TX_PSAI1_RXD4| rowspan="6" |AG18| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]|ALT0|SAI1_RX_DATA4|-|ALT1|SAI1_RX_DATA4(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT1)|A13-|ALT2|DSAI6_RX_BCLK(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT2)|-|ALT4|CORESIGHT_TRACE4|-|ALT5|GPIO4_IO06|-|ALT6|SRC_BOOT_CFG4|-|J1.186|USB1_VBUS|CPU.USB1_VBUS|D14F22| -|S|Connected with 30K resistor on SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.188|USB2_VBUS|CPU.USB2_VBUS|D9F23| -|S|Connected with 30K resistor on SOM.See IMX8MM datasheet for 5V tolerance info.|||-|J1.190|DGND|DGND| -|<nowiki>-</nowiki>|G|
|
|
|USB1_ID
|CPU.USB1_ID
|C14D22|VDD_PHY_3V3VDDA_1V8
|I
|
|USB2_ID
|CPU.USB2_ID
|C9D23|VDD_PHY_3V3VDDA_1V8
|I
|
|USB1_DN
|CPU.USB1_DN
|B14A22
| -
|D
|USB1_DP
|CPU.USB1_DP
|A14B22
| -
|D
|USB2_DP
|CPU.USB2_DP
|A10B23
| -
|D
|USB2_DN
|CPU.USB2_DN
|B10A23
| -
|D
|-
|}
'''(*)''' PMIC_PWRON can be used in two configuration: ''Embedded-like'' (default mounting option) or ''Tablet-like''. In the first case, the system reboots in case of PMIC_PWR_ON signal activity.
 
In the second case, the system will shut down waiting for a CPU_ONOFF signal raising (like a button-mode in a tablet) and the PMIC_PWRON Voltage domain is NVCC_SNVS_1V8
Please contact [mailto:sales@dave.eu sales dept.] for more information
----
[[Category:MITO 8M Mini]]
[[Category:MITO 8M Nano]]
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