Difference between revisions of "MITO 8M Mini SOM/MITO 8M Mini Hardware/Peripherals/PCI Express"

From DAVE Developer's Wiki
Jump to: navigation, search
Line 8: Line 8:
 
|-
 
|-
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Gen 2021
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Dec 2020
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
 
|-
 
|-

Revision as of 10:01, 29 January 2021

History
Version Issue Date Notes
1.0.0 Dec 2020 First release



Peripheral PCI Express[edit | edit source]

PCI Express (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards.

The PCI Express interface on MITO 8M Mini/Nano SOM is avaiable on SODIMM connector pinout.

Description[edit | edit source]

The PCI Express interfaces available on MITO 8M Mini/Nano is based on iMX8M Mini/Nano SoC.

The PCI Express interfaces supports the following standards and features:

  • PCIe PHY ports (1-lines) with L1 low power substates
  • up to 6.0 Gbps data rate
  • complies to PCI Express base specification 2.1.
  • 8B/10B Encoding / Decoding
  • Supports Spread Spectrum Clocking in Transmitter and Receiver

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section