Difference between revisions of "MITO 8M Mini SOM/MITO 8M Mini Hardware/Peripherals/LVDS"
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* Arranging the data as required by the external display receiver and by LVDS display standards | * Arranging the data as required by the external display receiver and by LVDS display standards | ||
* Synchronization and control capabilities | * Synchronization and control capabilities | ||
| + | This interface is available when the MIPI-to-LVDS bridge is present. See on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]] | ||
=== Description === | === Description === | ||
Revision as of 09:55, 29 January 2021
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Peripheral LVDS[edit | edit source]
The LVDS interface available on MITO 8M Mini/Nano is based on a MIPI® DSI To FLATLINK™ LVDS bridge IC.
It is directly connected to the MIPI® DSI output port of iMX8M Mini/Nano SOC.
This support covers all aspects of these activities:
- Connectivity to relevant devices - Displays with LVDS receivers
- Arranging the data as required by the external display receiver and by LVDS display standards
- Synchronization and control capabilities
This interface is available when the MIPI-to-LVDS bridge is present. See on MITO 8M Mini SOM P/N composition
Description[edit | edit source]
The LVDS port supports the following standards and features:
- Suitable for 60-fps WUXGA 1920 × 1200 Resolution at 18-bpp and 24-bpp Color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
- Output Configurable for Single-Link or Dual-Link LVDS
- LVDS Output Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Modes
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
