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→SoC and SDRAM bank organization
This section illustrates the configuration settings common to all the tests performed. Basically, the testbed that was used is the same described in [[MISC-TN-008:_Running_Debian_Buster_(armbian)_on_Mito8M|this TN]].
===SoC and SDRAM bank organization===The SoC model is i.MX8M Quad:<pre class="board-terminal">
armbian@Mito8M:~/devel/lmbench/tmp$ lscpu
Architecture: aarch64
NUMA node0 CPU(s): 0-3
Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
</pre>
This processor is capable of running either at 800 MHz or 1.3 GHz. All the tests were conducted at 800 MHz.
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