MISC-TN-009: Characterizing the RAM bandwidth of Mito8M SoM

Info Box Applies to MITO 8M

This technical note was validated against specific versions of hardware and software. What is described here may not work with other versions.

History

Version	Date	Notes
1.0.0	January 2020	First public release

Introduction

Mito8M is the first DAVE Embedded Systems' system-on-module (SoM) based on a core implementing the ARMv8-A architecture. Traditionally, ARM cores that are based on 32-bit ARMv7-A architecture exhibit a limited RAM bandwidth even if they are coupled with 64-bit width SDRAM banks. When dealing with computationally heavy tasks, this factor may turn out to be a severe bottleneck limiting the overall performance.

Besides an intrinsic increased computational power over their predecessors, ARMv8-A-based SoC's are also expected to improve RAM bandwidth significantly. This technical note (TN for short) illustrates several benchmarking tests that were run on Mito8M SoM. It is worth to remember that this product is built upon the i.MX8M processor by NXP.

Testbed general configuration

This section illustrates the configuration settings common to all the tests performed. Basically, the testbed that was used is the same described in this TN.

SoC and SDRAM bank

The SoC model is i.MX8M Quad:

armbian@Mito8M:~/devel/lmbench/tmp$ lscpu
Architecture:        aarch64
Byte Order:          Little Endian
CPU(s):              4
On-line CPU(s) list: 0-3
Thread(s) per core:  1
Core(s) per socket:  4
Socket(s):           1
NUMA node(s):        1
Vendor ID:           ARM
Model:               4
Model name:          Cortex-A53
Stepping:            r0p4
CPU max MHz:         1300.0000
CPU min MHz:         800.0000
BogoMIPS:            16.66
L1d cache:           unknown size
L1i cache:           unknown size
L2 cache:            unknown size
NUMA node0 CPU(s):   0-3
Flags:               fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid

This processor is capable of running either at 800 MHz or 1.3 GHz. All the tests were conducted at 800 MHz.

The following table details the characteristics of the SDRAM bank connected to the SoC.

		Mito8M
SoC	SoC	NXP i.MX8M Quad
	ARM frequency [MHz]	800
SDRAM	Type	LPDDR4
	Frequency [MHz]	1600
	Bus witdth [bit]	32
	Theoretical bandiwidth [Gb/s]	102.4
	Size [MB]	3072

Software configuration

• Linux kernel: 4.14.98
• Architecture: aarch64
• Governor: userspace @ 800 MHz

root@Mito8M:~# echo userspace > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
root@Mito8M:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
userspace
root@Mito8M:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq
800000

GCC

armbian@Mito8M:~/devel/lmbench$ gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/aarch64-linux-gnu/8/lto-wrapper
Target: aarch64-linux-gnu
Configured with: ../src/configure -v --with-pkgversion='Debian 8.3.0-6' --with-bugurl=file:///usr/share/doc/gcc-8/README.Bugs --enable-languages=c,ada,c++,go,d,fortran,objc,obj-c++ --prefix=/usr --with-gcc-major-version-only --program-suffix=-8 --program-prefix=aarch64-linux-gnu- --enable-shared --enable-linker-build-id --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --libdir=/usr/lib --enable-nls --enable-bootstrap --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --with-default-libstdcxx-abi=new --enable-gnu-unique-object --disable-libquadmath --disable-libquadmath-support --enable-plugin --enable-default-pie --with-system-zlib --disable-libphobos --enable-multiarch --enable-fix-cortex-a53-843419 --disable-werror --enable-checking=release --build=aarch64-linux-gnu --host=aarch64-linux-gnu --target=aarch64-linux-gnu
Thread model: posix
gcc version 8.3.0 (Debian 8.3.0-6)

Results

This section details the results that were achieved by the different benchmarks

Testbed #1

		Mito8M
	ARM frequency [MHz]	792
	Frequency [MHz]	1600
	Bus witdth [bit]	32

Useful links

• STREAM benchmark
• LM Bench benchmark
• pmbw benchmark
• Joshua Wyatt Smith and Andrew Hamilton, Parallel benchmarks for ARM processors in the highenergy context
• T Wrigley, G Harmsen and B Mellado, Memory performance of ARM processors and itsrelevance to High Energy Physics
• G. T. Wrigley, R. G. Reed, B. Mellado, Memory benchmarking characterisation of ARM-based SoCs