|November 2016January 2017

Other system-on-chips (SOC) implements proprietary solution to handle the access to the shared resources. [http://www.nxp.com/pages/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX NXP i.MX6SoloX] is an example of such components, as it integrates a so called ''Resource Domain Controller'' (RDC), that " provides robust support for the isolation of destination memory mapped locations such as peripherals and memory to a single core, a bus master, or set of cores and bus masters" as stated by the manufacturer [2].

[2] See ''NXP i.MX 6SoloX Applications Processor Reference Manual (IMX6SXRM)''. 

[[File:TBDSoloX-AMP.png|thumb|center|600px400px|captionSimplified block diagram of the AMP configuration]]

For this specific application, it is required that the M4 core has exclusive access of to the following resources:

It is also required that :*M4 firmware is booted before the Linux kernel and that the [2]*The Linux kernel has exclusive control of some other GPIOSGPIOs.  Satisfying the first requirement has been the trickiest challenge because, by default, U-Boot and Linux kernel make use of GPT timer, as per official BSP released by NXP. This is not a big deal for U-Boot, because it just uses this timer to handle timeouts and to measure time intervals. The things are more complicated with regard to the Linux, because GPT is used as kernel's clock source. As such, it is involved in the scheduling process and it is dynamically reconfigured over the time, depending on power saving policies.

Satisfying the first requirement has been the trickiest challenge because, by defaultTo solve this issue, both U-Boot and Linux kernel make have been modified, in order to use of GPT EPIT timer, as per official BSP released by NXPinstead. This is not a big deal for U-BootIn spite of this modification, because it just uses this timer to handle timeouts and to measure time intervals. The things are more complicated with regard we have been able to the preserve Linux kernel, because GPT is used as clock source. As such, it is involved in the scheduling process and it is dynamically reconfigured over the time, depending on 's power saving policiesmechanisms.

To solve In order to protect the peripherals that have to be under the exclusive control of the M4 core, RDC has been configured accordingly. For example, the memory area in which GPT registers are mapped, is accessible by the M4 core only. RDC initialization is performed by M4 itself. It is worth remembering that the its granularity is an important factor that has to be taken in consideration. In this issueapplication, for example, both U-Boot it has had to choose different GPIO banks for M4 and Linux kernel A9. In case the same bank was chosen, it would have been modifiedimpossible to partition GPIOs across the two cores, in order because some resources are shared among all of the GPIOs belonging to use EPIT timer insteadthe same bank (for example the clocks feeding the GPIO module). In spite of For this modificationreason, we two different banks have been able to preserve power saving strategieschosen.

About boot requirements, U [1] For more details please refer to the [http://www.nxp.com/pages/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX?tab=Design_Tools_Tab FreeRTOS™ BSP for the i.MX 6SoloX ARM® Cortex®-Boot has been configured in order to get M4 core]. [2] Following is the following complete bootstrap sequence:

#*perform performs basic hardware initializations

#in In turn, U-Boot

#once Once Linux kernel has completed the bootstrap process, a user space application establishes a communication channel with M4 core, through [https://www.kernel.org/doc/Documentation/remoteproc.txt RPMsg].      [1] For more details please refer to the [http://www.nxp.com/pages/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX?tab=Design_Tools_Tab FreeRTOS™ BSP for the i.MX 6SoloX ARM® Cortex®-M4 core].