Changes

{{ImportantMessage|text=This document refers to the tools used to '''build the software for the Processing Subsystem (PS) only'''.

*'''FSBL is no longer used as the first-stage bootloader'''. '''It is replaced by U-Boot SPL'''.*'''Yocto build system is fully integrated into the kit and it is used to build all the software running on the target'''. Consequently, the Vivado SDK tool chain is no longer used.*To simplify the installation of host-side tools, '''a [[Managed Virtual Machine (MVM)]] is provided''', containing all the required tools.==Structure of BELK/BXELK reference designs== 

==Basic structure The role of Vivado Design Suite and integration into BELK/BXELK==Vivado/SDK [1] can be viewed as a collection of programs required to deal with all of the development aspects related to Xilinx components U-Boot SPL is based on one file (software running on ARM cores, FPGA fabric verification and programming, power estimation etc<code>ps7_init.c</code>). These include strictly FPGA-related tools such as Floorplanner and pure-software development tools such as SDK.The ambitious objective that is to provide a complete, user-friendly, integrated environment that allows software developers to deal with FPGA development even if they are not familiar with this technology, generated by hiding a lot of its complexities [2]Vivado. As usualIn turn, this ease of use comes at the expense of control and flexibility. This could not be acceptable in many cases where engineers need to control and customize many aspects of the project to implement what is required by system specifications. For this reason, BELK and BXELK have been built around Vivado but file contains some deviations from the default development approach suggested by Xilinx have been introduced, in order to '''push the modularization and the maintainability of the projects initialization parameters that are set according to the maximum possible extent'''Zynq configuration.

The following pictures show respectively U-Boot sources provided by the BELK/BXELK include such file. Unless you need to modify the initial Zynq configuration, you don't need to generate a new <code>ps7_init.c</code> file. Therefore, from the standpoint of the software running on PS, the role of Vivado/SDK default development flow and how this has been integrated is limited to the generation of such file.==The role of Yocto==From the point of view of PS software, the role of Yocto build system is crucial. As shown in the BELK/BXELK infrastructurefollowing image, in fact, it is used to build:* U-Boot SPL (first-stage bootloader)* U-Boot (second-stage bootloader)* Linux kernel* Device tree* root file system* user applications.

[[File:BELKBelk-4.0.0 belk-vivado-sdk-development-flowyocto.png|thumbnailthumb|center|300px600px|Vivado/SDK development Simplified flow (BELK 4.0.0 or newer and BXELK 2.0.0 or newer)of Yocto-based building process]]

The image shows the simplified flow of the Yocto-based building process. The modules within the dashed line are included in the [[File:Belk-vivado-sdk-integration.png|thumbnail|center|300px|Vivado/SDK integration into BELK/BXELKManaged Virtual Machine (MVM)]]delivered along with the kit.

 The [[1BELK/BXELK_software_components#Downloadable_binary_images|binary images]] The Software Development Kit (SDK) is distributed with the Xilinx Integrated Design Environment for creating embedded applications on Zynq™-7000 All Programmable SoCskit are generated by this process. SDK is {{ImportantMessage|text=Please note that the first application IDE to deliver true homogenous whole build process requires a lot of hardware resources in terms of disk storage, RAM, and heterogenous multi-processor design and debugprocessing power. For this reason, it is optionally included with discouraged to use the Vivado Design Suite or ISE Design Suite, or available as a separate free download for application developersMVM to perform such build. [2] Nevertheless FPGA developers will find all the traditional tools that allow complete control of FPGA fabric.}}