Logical structure of Bora and BoraX Embedded Linux Kits (BELK/BXELK)

Info Box Applies to Bora Applies to BORA Xpress

Introduction

To understand the structure of Bora Embedded Linux Kit (BELK) and BoraX Embedded Linux Kit (BXELK), it is necessary to describe the basic organization of Xilinx Vivado Design Suite/Xilinx SDK and to recall briefly the recent history of development tools provided by Xilinx.

A little bit of history

At the time of this writing (October 2013) Xilinx is migrating from mature ISE 14.x Design Suite - that should be the last series of this suite - to the new Vivado environment. Both are composed by several programs and some of these are in common. From the general standpoint, the main difference between ISE and Vivado - even if ISE does support Zynq - is that the latter has been expressively conceived to support newer SoC architectures such as Zynq, besides traditional FPGAs. Thus, adopting Vivado as the default environment for BELK/BXELK would seem the natural choice. However, the migration process mentioned above has just begun and the majority of application notes and reference designs released by Xilinx still refers to ISE suite. Plus Vivado is still a little bit "green" and several bug fixes and improvements are introduced by every new release.

Since Bora was presented in 2013 and because this product addresses long longevity markets such as industrial and biomedical, DAVE Embedded Systems chose to build BELK/BXELK upon Vivado that undoubtedly represents today the future of Xilinx development environments.

Structure of BELK/BXELK reference designs

The typical linux-based Zynq design is composed by the following parts:

• FSBL
• U-Boot
• device tree file
• Linux kernel
• Root file system
• Executable image of core #1 (in case of AMP systems)
• FPGA bitstream.

Generally speaking, these parts - in the binary/sinthesized form - are combined together in one monolithic file that is stored in a non-volatile memory such as SPI NOR flash. Generating this file is quite easy as described by Vivado documentation. However in real world products, this may be too rigid because developers may want to handle these parts separately and independently.

Basic structure of Vivado Design Suite and integration into BELK/BXELK

Vivado/SDK [1] can be viewed as a collection of programs required to deal with all of the development aspects related to Xilinx components (software running on ARM cores, FPGA fabric verification and programming, power estimation etc.). These include strictly FPGA-related tools such as Floorplanner and pure-software development tools such as SDK. The ambitious objective is to provide a complete, user friendly, integrated environment that allows software developers to deal with FPGA development even if they are not familiar with this technology, by hiding a lot of its complexities [2]. As usual this ease of use comes at the expence of control and flexibility. This could not be acceptable in many cases where engineers need to control and customize many aspects of the project to implement what is required by system specifications. For this reason, BELK and BXELK have been built around Vivado but some deviations from the default development approach suggested by Xilinx have been introduced, in order to push the modularization and the maintainability of the projects to the maximum possible extent.

The following pictures show respectively the Vivado/SDK default development flow and how this has been integrated in the BELK/BXELK infrastructure.

Vivado/SDK development flow

Vivado/SDK integration into BELK/BXELK

[1] The Software Development Kit (SDK) is the Xilinx Integrated Design Environment for creating embedded applications on Zynq™-7000 All Programmable SoCs. SDK is the first application IDE to deliver true homogenous and heterogenous multi-processor design and debug, it is optionally included with the Vivado Design Suite or ISE Design Suite, or available as a separate free download for application developers.

[2] Nevertheless FPGA developers will find all the traditional tools that allow complete control of FPGA fabric.