Changes

The following figure shows pictures show a simplified scheme of the the developing development environment for an Embedded Linux system based on BORA or BORAX: it is composed of . The tmw main blocks are a host machine and a target machine. [[File:Belk-development-flow.png|thumb|center|600px|BORA/BORAX development environment (BELK <= version up to 3.0.2 and , BXELK <= version up to 1.0.1)]] [[File:BELK-4.0.0 belk-development-flow.png|thumb|center|600px|BORA/BORAX development environment (BELK 4.0.0 or newer and , BXELK 2.0.0 or newer)]] In a typical environment, the host is used by the developer to (cross-)compile the code that is to run on the target. In our case , the target is a SOM, while the host is assumed to be a PC running the Linux operating system, either in a physical installation or as a virtual machine(for recent kits, this is the [[Logical_structure_of_Bora_and_BoraX_Embedded_Linux_Kits_(BELK/BXELK)#BELK_starting_from_version_4.0.0_.2F_BXELK_starting_from_version_2.0.0|MVM]]).  The bootloader running on the target can download the Linux kernel image through the network (TFTP), as well as the u-boot bootloader binary images (useful when an update of the bootloader is required).  Moreover, the Linux kernel running on the target is able to mount the root file system from different physical media, for example from a directory exported via Network File System (NFS) by the host. This strategy (kernel image and RFS retrieved from the network) saves time during the development phase, since no flash reprogramming or removable storage (SD, usb USB pen drives, external disks) is required to test new versions or updates of the software components.  In contrast with a typical embedded system, BORA/BORAX adds some complexity, due to the nature of the Zynq processor, which provides both a CPU core (aka PS, processing systemProcessing System) and a an integrated FPGA (aka PL, programmable logicProgrammable Logic). This means that additional tools are required to manage this complexity.  In particular, the *The Vivado® Design Suite and is required for the generation of the PL bitstream*The Xilinx Software Development Kit are (SDK) is required for the hardware level configuration and for building the first stage boot loader (FSBL)(BELK version up to 3. 0.2, BXELK version up to 1.0.1) Starting from BELK-4.0.0 and BXELK-2.0.0 U-boot SPL bootloader is used instead of FSBL allowing SW only development flow avoiding the use of Vivado® Design Suite, therefore Xilinx SDK is no longer required.