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→Carrier board specific design guidelines
In this section hardware guidelines valid for NAON are analized. The information provided here complete the [[Carrier board design guidelines (SOM)|Carrier board design guidelines]] for some specific interfaces.
==== Interfaces Guidelines ====
For interfaces not mentioned in this section, refer to the generic guidelines.
===== USB =====
====== PCB ======
Table listeb below integrated integrates the general basic guidelines table
{| {{table border=1}}
| align="center" style="background:#f0f0f0;"|'''Parameter for USB Differential Pairs'''
===== SATA =====
====== PCB ======
Table listeb below integrated integrates the general basic guidelines table
{| {{table border=1}}
| align="center" style="background:#f0f0f0;"|'''Parameter for USB Differential Pairs'''
|-
| Intra pair matching(mils||-||-||10
|-
| Inter pair matching(mils||-||-||-
|-
| Max traces length ||-||-||6"
|}
=== LCD Interface ======= PCB ====* Matching depends from Pixel Clock. As general rule, match lines at 500-800 mils* Place series terminator near Naon Connector=== VIN Interface ======= PCB ====* No Matching required between TX and RXdepends from Pixel Clock. As general rule, but keep same route for every differential pairmatch lines at 500-800 mils* Place series terminator near VIN source=== RMII Interface ===This interface is a subset of the RGMII port.==== Schematic ====* use a standard RMII PHY device that support 50MHz Clock input mode* Set PHY address different from integrated PHY
==Software==
