3,260
edits
Changes
m
===Carrier board specific design guidelines==={{InfoBoxTop}}<br/>{{Applies To Maya}}'''Please refer first to [[Carrier board design guidelines (SOM)|Carrier board design guidelines]].'''<br/>In this section hardware guidelines valid for MAYA are analized. The information provided here complete the [[Carrier board design guidelines (SOM)|Carrier board design guidelines]] for some specific interfaces.{{InfoBoxBottom}}
no edit summary
==Introduction==
This page provides useful information and resources to system designers in order to integrate Naon module in his/her application quickly.
==Hardware==
===Evaluation boards and reference designs===
Several schematics are available in order to accelerate the design of carrier board hosting Maya SOM. Please note that, even if these schematics are derived from tested real-world applications, they are provided "as is" and they might be modified in order to adapt to your specific application.
Available schematics:
* MayaEVB-Lite: [[MayaEVB-Lite#Schematics]]
===Carrier board design guidelines===
[[Carrier board design guidelines (SOM)|This page]] provides general guidelines about how to implement carrier boards hosting SOM.
In the following sections further hardware guidelines valid for Maya are illustrated. The information provided here complete the [[Carrier board design guidelines (SOM)|Carrier board design guidelines]] for some specific interfaces.
==== Interfaces Guidelines ====
For interfaces not mentioned in this section, refer to the generic guidelines.
| Max traces length ||-||-||17"
|}
=== LCD Interface ===
==== PCB ====
* Matching depends from Pixel Clock. As general rule, match lines at 500-800 mils
* Place Consider placing series terminator terminations near Maya Connector
=== VIN Interface ===
==== PCB ====
* Matching depends from Pixel Clock. As general rule, match lines at 500-800 mils
* Place Consider placing series terminator terminations near VIN source
=== RMII Interface ===
==== Schematic ====
* use a standard RMII PHY device that support 50MHz Clock input mode
* Set PHY address different from integrated PHY