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→How to implement workaround suggested by Xilinx on BoraEVB
The BANK35 MUST be powered at 1.8V
===== Test on BoraEVB =====
To test the solution, please make these connections on BORAevb rev.A:
* 1.8V supply for BANK35 : (J11.2 to J11.7)
* I2C SCL : JP10.14 to JP21.5
* I2C SDA : JP10.16 to JP21.3
===== Test on BoraXEVB =====
To test the solution, please make these connections on BoraXEVB:
* 1.8V supply for BANK35 : please refer to VDDIO_BANK35 possibility on BoraXEVB schematics
* populate RPACK RP87
* I2C SCL : JP30.9 to JP29.5
* I2C SDA : JP30.11 to JP29.3
===Programmable logic (PL)===
