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Power consumptions related to some real world use cases can be found here. [TBD insert link]
U0007 moved page Integration guide (Bora/BoraX) to Integration guide (Bora/BoraX/BoraLite)
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=== Main SD/MMC interface ===
=== Connecting the PUDC_B pin ===
On Bora SOM, PUDC_B pin is (J2 connector, pin 15) connected to VDDIO_BANK34 (3.3V) via 10K resistor (, thus [http://www.xilinx.com/support/answers/50802.html internal pull-up resistors are disabled on each SelectIO pin, until FPGA configuration completes].
Default behavior can be changed by connecting PUDC_B pin (J2 - Pin 15) to ground with 1K pull-down resistor appropriate circuitry at carrier board levelto set it to logical 0.
=== PS' I²C buses ===
[[File:Bora-i2c-glitch-filter.png|thumb|center|600px]]
[[File:BoraLite-i2c-glitch-filter.jpg|thumb|center|600px]]
The BANK35 MUST be powered at 1.8V
===== Test on BoraEVB =====
To test the solution, please make these connections on BORAevb rev.A:
* 1.8V supply for BANK35 : (J11.2 to J11.7)
* I2C SCL : JP10.14 to JP21.5
* I2C SDA : JP10.16 to JP21.3
===== Test on BoraXEVB =====
To test the solution, please make these connections on BoraXEVB:
* 1.8V supply for BANK35 : please refer to VDDIO_BANK35 possibility on BoraXEVB schematics
* populate RPACK RP87
* I2C SCL : JP30.9 to JP29.5
* I2C SDA : JP30.11 to JP29.3
===Programmable logic (PL)===
For BoraX SOM please refer to the [[Programmable_logic_(BORAXpress)|page]].
For BoraLite SOM please refer to the [[Programmable_logic_(BoraLite)|page]].
===Traces length matching===
A spreadsheet is available for download here, containing detailed information about signals routing. These information can be used to check nets matching of the overall system (carrier board + SOM).
For Bora/BoraEVB systems: [[File:Bora-routing.zip]].
For BoraX/BoraXEVB systems: [[File:BoraX-BoraXEVB-combined-routing.zip]].
For BoraLite/BoraXEVB systems: the presence of the Bora Lite adapter does not make sense to provide the routing information. Please refer to the [[Programmable_logic_(BoraLite)| Programmable_logic_(BoraLite) page]] about information on internal BORA Lite routing. Please take carefully into account the design of the Carrier board considering every information related to the SO-DIMM socket and the tracenet on the Carrier
