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Integration guide (Bora/BoraX/BoraLite)

24,738 bytes removed, 10:11, 18 October 2019
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Power consumptions related to some real world use cases can be found here. [TBD insert link]
=== Main SD/MMC interface ===
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=== Connecting the PUDC_B pin ===
 
On Bora SOM, PUDC_B pin is (J2 connector, pin 15) connected to VDDIO_BANK34 (3.3V) via 10K resistor, thus [http://www.xilinx.com/support/answers/50802.html internal pull-up resistors are disabled on each SelectIO pin, until FPGA configuration completes].
 
Default behavior can be changed by appropriate circuitry at carrier board level to set it to logical 0.
 
=== PS' I²C buses ===
[[File:Bora-i2c-glitch-filter.png|thumb|center|600px]][[File:BoraLite-i2c-glitch-filter.jpg|thumb|center|600px]] 
(1) What here described refers to I2C0 controller that by default is routed on pins MIO46 and MIO47.
=== PL bank 34 = How to implement workaround suggested by Xilinx on BoraEVB====Routing implemented on Bora SoM allows the use of bank 34's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent. Pairs are highlighted with different colors. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohm.
{| class="wikitable" border="1"| align="center" style="background:#f0f0f0;"|'''Bora pin name'''| align="center" style="background:#f0f0f0;"|'''Individual trace length<br>[mils]'''| align="center" style="background:#f0f0f0;"|'''Intra-pair match<br>[mils]'''| align="center" style="background:#f0f0f0;"|'''Inter-pair match<br>[mils]'''| align="center" style="background:#f0f0f0;"|'''Group name'''|-| IO_L1N_T0_34||align="center"|1751,37||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L1P_T0_34||align="center"|1749,02||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L2N_T0_34||align="center"|1625,68||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L2P_T0_34||align="center"|1624,91||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L4N_T0_34||align="center"|1581,72||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L4P_T0_34||align="center"|1582,11||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L5N_T0_34||align="center"|1769,81||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L5P_T0_34||align="center"|1776,23||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L7N_T1_34||align="center"|1566,52||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L7P_T1_34||align="center"|1569,36||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L9N_T1_DQS_34||align="center"|1490,25||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L9P_T1_DQS_34||align="center"|1498,04||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L10N_T1_34||align="center"|1516,97||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L10P_T1_34||align="center"|1517,37||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L15N_T2_DQS_34||align="center"|1610,74||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L15P_T2_DQS_34||align="center"|1602,81||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L16N_T2_34||align="center"|1601,55||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L16P_T2_34||align="center"|1616,03||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L17N_T2_34||align="center"|1574,33||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L17P_T2_34||align="center"|1593,38||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L18N_T2_34||align="center"|1740,11||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L18P_T2_34||align="center"|1750,54||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L20N_T3_34||align="center"|1588,01||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L20P_T3_34||align="center"|1585,53||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L21N_T3_DQS_34||align="center"|1567,1||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L21P_T3_DQS_34||align="center"|1570,96||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L22N_T3_34||align="center"|1619,26||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L22P_T3_34||align="center"|1622,13||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L23N_T3_34||align="center"|1769,71||align="center"|25||align="center"|300||BANK34 Diff group 1|-| IO_L23P_T3_34||align="center"|1775,52||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L24N_T3_34||align="center"|1772,07||align="center"|25||align="center"|300||BANK34 Diff group 1|- style="background: gray"| IO_L24P_T3_34||align="center"|1774,49||align="center"|25||align="center"|300||BANK34 Diff group 1|-style="background: black"| ''' '''|||||||||-| IO_L11N_T1_SRCC_34||align="center"|1817,43||align="center"|10||align="center"|50||BANK34 xRCC group|-| IO_L11P_T1_SRCC_34||align="center"|1823,9||align="center"|10||align="center"|50||BANK34 xRCC group|- style="background: gray"| IO_L12N_T1_MRCC_34||align="center"|1844,2||align="center"|10||align="center"|50||BANK34 xRCC group|- style="background: gray"| IO_L12P_T1_MRCC_34||align="center"|1841,36||align="center"|10||align="center"|50||BANK34 xRCC group|-| IO_L13N_T1_MRCC_34||align="center"|1811,51||align="center"|10||align="center"|50||BANK34 xRCC group|-| IO_L13P_T1_MRCC_34||align="center"|1818,58||align="center"|10||align="center"|50||BANK34 xRCC group|- style="background: gray"| IO_L14N_T2_SRCC_34||align="center"|1818,78||align="center"|10||align="center"|50||BANK34 xRCC group|- style="background: gray"| IO_L14P_T2_SRCC_34||align="center"|1822,02||align="center"|10||align="center"|50||BANK34 xRCC group|-|} About power voltage, take into consideration Plase note that Bank 35 is fixed at 3.3V. === PL bank 35 ===On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz.Signals have been grouped in the following classes:* FDDR_ADDR* FDDR_CK* FDDR_BYTE0* FDDR_BYTE1Some of them are differential pairs. These kind of signals are highlighted in dark grey in the following sections where, for each signal, detailed information are provided, related to routing rules reference project with I2C glitch filter implemented on Bora SoM and carrier board guidelines. Following tables indicates general recommended rules for single-ended and differantial pairs on carrier board in terms of impedence and isolation. Differential pairs:{| class="wikitable" border="1"| align="center" style="background:#f0f0f0;"|''' '''| align="center" style="background:#f0f0f0;"|''' Value '''| align="center" style="background:#f0f0f0;"|''' UOM '''|-| Common Mode impedance typ||align="center"|55||align="center"|Ohm|-| Differential Mode impedance typ||align="center"|100||align="center"|Ohm|-| Isolation||align="center"|4x||align="center"|gap|-|} Single-ended signals:{| class="wikitable" border="1"| align="center" style="background:#f0f0f0;"|''' '''| align="center" style="background:#f0f0f0;"|''' Value '''| align="center" style="background:#f0f0f0;"|''' UOM '''|-| Common Mode impedance typ||align="center"|55||align="center"|Ohm|-| Isolation||align="center"|2x||align="center"|width|-|} About power voltage, Bank 35 FPGA is configurable and must be powered by carrier board. Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs.===== FDDR_ADDR class =====Following table details routing rules implemented available on Bora SoM and suggested carrier board guidelines for FDDR_ADDR class signals. The picture shows connection scheme and the nomenclature used in the tablerequest. [Plase contact [Filemailto:FDDR_ADDRsupport-bora@dave.png]]  {| class="wikitable" border="1"! align="center" style="background:#f0f0f0;" rowspan="2" | '''Bora pin name''' ! align="center" style="background:#f0f0f0;" rowspan="2" | '''Group name'''! align="center" style="background:#f0f0f0;" rowspan="2" | '''Carrier board net name'''! align="center" style="background:#f0f0f0;" colspan="3" | '''SoM routing rules and specifications'''! align="center" style="background:#f0f0f0;" colspan="6" | '''Carrier board guidelines'''|eu support-! align="center" style="background:#f0f0f0;" | '''Actual length<br>[mils]'''! align="center" style="background:#f0f0f0;" | '''Max length match<br>[milsbora@dave.eu]'''! align="center" style="background:#f0f0f0;" | '''Nominal max length<br>[mils]'''! align="center" style="background:#f0f0f0;" | '''AD_A2 length match<br>[mils]'''! align="center" style="background:#f0f0f0;" | '''AD_AT length match<br>[mils]'''! align="center" style="background:#f0f0f0;" | '''AD_AS1 length match<br>[mils]'''! align="center" style="background:#f0f0f0;" | '''AD_AS1 max length<br>[mils]'''! align="center" style="background:#f0f0f0;" | '''AD_AT max length<br>[mils]'''! align="center" style="background:#f0f0f0;" | '''AD_A2+AD_AS1 max length<br>[mils]'''|-|IO_L17N_T2_AD5N_35||FDDR_ADDR||FDDR_ADDR_3||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L20P_T3_AD6P_35||FDDR_ADDR||FDDR_BA_2||align="center"|1853,4||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L16N_T2_35||FDDR_ADDR||FDDR_ADDR_5||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L18N_T2_AD13N_35||FDDR_ADDR||FDDR_ADDR_1||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L24N_T3_AD15N_35||FDDR_ADDR||FDDR_CKE_0||align="center"|1834,3||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L23P_T3_35||FDDR_ADDR||FDDR_CAS_N||align="center"|1857,01||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L14N_T2_AD4N_SRCC_35||FDDR_ADDR||FDDR_ADDR_9||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L24P_T3_AD15P_35||FDDR_ADDR||FDDR_CS0_N||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L14P_T2_AD4P_SRCC_35||FDDR_ADDR||FDDR_ADDR_10||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L15P_T2_DQS_AD12P_35||FDDR_ADDR||FDDR_ADDR_8||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L15N_T2_DQS_AD12N_35||FDDR_ADDR||FDDR_ADDR_7||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L12N_T1_MRCC_35||FDDR_ADDR||FDDR_RESET_N||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L13P_T2_MRCC_35||FDDR_ADDR||FDDR_ADDR_12||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L13N_T2_MRCC_35||FDDR_ADDR||FDDR_ADDR_11||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_25_35||FDDR_ADDR||FDDR_ODT_0||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L23N_T3_35||FDDR_ADDR||FDDR_WE_N||align="center"|1869,66||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L17P_T2_AD5P_35||FDDR_ADDR||FDDR_ADDR_4||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L22N_T3_AD7N_35||FDDR_ADDR||FDDR_RAS_N||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L20N_T3_AD6N_35||FDDR_ADDR||FDDR_BA_1||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L18P_T2_AD13P_35||FDDR_ADDR||FDDR_ADDR_2||align="center"|1853,7||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L16P_T2_35||FDDR_ADDR||FDDR_ADDR_6||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L22P_T3_AD7P_35||FDDR_ADDR||FDDR_BA_0||align="center"|1850,82||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-| IO_L19P_T3_35||FDDR_ADDR||FDDR_ADDR_0||align="center"|1836,73||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100|-|}
===== FDDR_CK class =====Following table details routing rules implemented This project, built with Vivado 2014.4, is based on Bora SoM and suggested carrier board guidelines the default project for FDDR_CK class signalsBELK (BORA rev. The picture shows connection scheme B and the nomenclature used in the tableBORAevb rev.A).
[[File:FDDR_CKHere we have changed I2C0 signals routing to EMIO pins through FPGA, implementing the I2C glitch filter with VHDL example code provided in Xilinx AR# 61861.The MIO46-MIO47 is then configured as input GPIO. This is accomplished from the FSBL generated within the provided project.png]]
{| class="wikitable" border="1"! align="center" style="background:#f0f0f0;" rowspan="2" |'''Bora pin name'''! align="center" style="background:#f0f0f0;" rowspan="2" |'''Group name'''! align="center" style="background:#f0f0f0;" rowspan="2" |'''Carrier board net name'''! align="center" style="background:#f0f0f0;" colspan="4" |'''SoM routing rules and specifications'''! align="center" style="background:#f0f0f0;" colspan="8" |'''Carrier board guidelines'''|-! align="center" style="background:#f0f0f0;"|'''Actual length<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''Intra-pair match<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''Max length match (with respect to FDDR_ADDR group)<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''Nominal max length<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''Intra-pair match<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''CK_A2 pair match (with respect to FDDR_ADDR)<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''CK_AT intra-pair match<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''CK_AS1 match (with respect I2C interface is routed through FPGA to FDDR_ADDR)<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''CK_AS1 max length<br>[mils]'''! align="center" style="backgroundpins on BANK35:#f0f0f0;"|'''CK_AT maximum length<br>[mils]'''! align="center" style* I2C SCL ="background:#f0f0f0;"|'''CK_AT pair match (with respect to FDDR_ADDR)<br>[mils]'''IO_L9P_T1_DQS_AD3P_35! align* I2C SDA ="center" style="background:#f0f0f0;"|'''CK_A2+CK_AS1 max length<br>[mils]'''|- style="background: gray"| IO_L21P_T3_DQS_AD14P_35||FDDR_CK||FDDR_CK_P0||align="center"|1900,39||align="center"|5||align="center"|80||align="center"|1912||align="center"|10||align="center"|40||align="center"|5||align="center"|50||align="center"|60||align="center"|400||align="center"|100||align="center"|2100|- style="background: gray"| IO_L21N_T3_DQS_AD14N_35||FDDR_CK||FDDR_CK_N0||align="center"|1898,17||align="center"|5||align="center"|80||align="center"|1912||align="center"|10||align="center"|40||align="center"|5||align="center"|50||align="center"|60||align="center"|400||align="center"|100||align="center"|2100|-|}IO_L9N_T1_DQS_AD3N_35
===== FDDR_BYTE0 class =====Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE0 class signalsThe BANK35 MUST be powered at 1.8V
{| class="wikitable" border="1"! align="center" style="background:#f0f0f0;" rowspan="2" |'''Pin Name'''! align="center" style="background:#f0f0f0;" rowspan="2" |'''Group name'''! align="center" styleTest on BoraEVB ="background:#f0f0f0;" rowspan="2" |'''Carrier board net name'''! align="center" style="background:#f0f0f0;" colspan="4" |'''SoM routing rules and specifications'''! align="center" style="background:#f0f0f0;" colspan="3" |'''Carrier board guidelines'''|-! align="center" style="background:#f0f0f0;"|'''Actual length<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''Max length match<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''Max inter-pair match length To test the solution, please make these connections on SOM<br>[mils]'''! align="center" style="backgroundBORAevb rev.A:#f0f0f0;"|'''Nominal max length<br>[mils]'''! align="center" style="background* 1.8V supply for BANK35 :#f0f0f0;"|'''Group match (mandatory)<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''Intra-pair match (mandatoryJ11.2 to J11.7)<br>[mils]'''! align="center" style="background* I2C SCL :#f0f0f0;"|'''Max length<br>[mils]'''|-| IO_L2N_T0_AD8N_35||FDDR_BYTE0||FDDR_DQ_2||align="center"|1222,66||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L6P_T0_35||FDDR_BYTE0||FDDR_DQ_7||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L5P_T0_AD9P_35||FDDR_BYTE0||FDDR_DQ_5||align="center"|1226,42||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L4P_T0_35||FDDR_BYTE0||FDDR_DQ_3||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L2P_T0_AD8P_35||FDDR_BYTE0||FDDR_DQ_1||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L1N_T0_AD0N_35||FDDR_BYTE0||FDDR_DQ_0||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L4N_T0_35||FDDR_BYTE0||FDDR_DQ_4||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L5N_T0_AD9N_35||FDDR_BYTE0||FDDR_DQ_6||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L1P_T0_AD0P_35||FDDR_BYTE0||FDDR_DM_0||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)|- style="background: gray"| IO_L3P_T0_DQS_AD1P_35||FDDR_BYTE0||FDDR_DQS_P0||align="center"|1221,04||align="center"|15||align="center"|JP10.14 to JP21.5||align="center"|1230||align="center"|25||align="center"|5||align="center"|CK_A2+CK_AS1(max)|- style="background* I2C SDA : gray"| IO_L3N_T0_DQS_AD1N_35||FDDR_BYTE0||FDDR_DQS_N0||align="center"|1219,42||align="center"|15||align="center"|5||align="center"|1230||align="center"|25||align="center"|5||align="center"|CK_A2+CK_AS1(max)|-|}JP10.16 to JP21.3
===== FDDR_BYTE1 class Test on BoraXEVB =====Following table details routing rules implemented To test the solution, please make these connections on Bora SoM and suggested carrier board guidelines BoraXEVB:* 1.8V supply for FDDR_BYTE1 class signalsBANK35 : please refer to VDDIO_BANK35 possibility on BoraXEVB schematics* populate RPACK RP87* I2C SCL : JP30.9 to JP29.5* I2C SDA : JP30.11 to JP29.3
{| class="wikitable" border="1"! align="center" styleProgrammable logic (PL)="background:#f0f0f0;" rowspan="2" |'''Pin Name'''! align="center" style="background:#f0f0f0;" rowspan="2" |'''Group name'''! align="center" style="backgroundFor Bora SOM please refer to the following links:#f0f0f0;" rowspan="2" |'''Carrier board net name'''! align="center" style="background:*[[Programmable_logic_(Bora)#f0f0f0;" colspan="4" Routing_information|'''SoM routing rules and specifications'''! align="center" style="background:#f0f0f0;" colspan="3" |'''Carrier board guidelines'''|-! align="center" style="background:#f0f0f0;"|'''Actual length<br>[milsbank 34]'''! align="center" style="background:#f0f0f0;"|'''Max length match<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''Max inter-pair match length on SOM<br>*[mils]'''! align="center" style="background:#f0f0f0;"|'''Nominal max length<br>[mils]'''! align="center" style="background:#f0f0f0;"|'''Group match Programmable_logic_(mandatoryBora)<br>[mils]'''! align="center" style="background:#f0f0f0;"Routing_information_2|'''Intra-pair match (mandatory)<br>[milsbank 35]]'''! align="center" style="background:#f0f0f0;"|'''Max length<br>*[[mils]'''|-| IO_L10N_T1_AD11N_35||FDDR_BYTE1||FDDR_DQ_12||align="center"|1345,93||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1Programmable_logic_(maxBora)#Routing_information_3|-| IO_L10P_T1_AD11P_35||FDDR_BYTE1||FDDR_DQ_11||align="center"|1345,93||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L11P_T1_SRCC_35||FDDR_BYTE1||FDDR_DQ_13||align="center"|1353,43||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L12P_T1_MRCC_35||FDDR_BYTE1||FDDR_DQ_15||align="center"|1341,3||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L11N_T1_SRCC_35||FDDR_BYTE1||FDDR_DQ_14||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L8P_T1_AD10P_35||FDDR_BYTE1||FDDR_DQ_9||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L7N_T1_AD2N_35||FDDR_BYTE1||FDDR_DQ_8||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L8N_T1_AD10N_35||FDDR_BYTE1||FDDR_DQ_10||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)|-| IO_L7P_T1_AD2P_35||FDDR_BYTE1||FDDR_DM_1||align="center"|1345,93||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)|- style="background: gray"| IO_L9P_T1_DQS_AD3P_35||FDDR_BYTE1||FDDR_DQS_P1||align="center"|1354,26||align="center"|15||align="center"|5||align="center"|1355||align="center"|20||align="center"|5||align="center"|CK_A2+CK_AS1(max)|- style="background: gray"| IO_L9N_T1_DQS_AD3N_35||FDDR_BYTE1||FDDR_DQS_N1||align="center"|1350,66||align="center"|15||align="center"|5||align="center"|1355||align="center"|20||align="center"|5||align="center"|CK_A2+CK_AS1(max)|-|}bank 13]]
===== VREF =====Recommendations:* use a "T" connection as shown by following picture* use 20+ mils trace* place bypass capacitors as close as possible For BoraX SOM please refer to power ballsthe [[Programmable_logic_(BORAXpress)|page]].
For BoraLite SOM please refer to the [[File:VREF.pngProgrammable_logic_(BoraLite)|page]].
===== Related Xilinx documentation ==Traces length matching===* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf Xilinx Memory Interface Solutions UG586]* [http://www.xilinxA spreadsheet is available for download here, containing detailed information about signals routing.com/support/documentation/ip_documentation/mig_7series/v2_0/ds176_7Series_MISThese information can be used to check nets matching of the overall system (carrier board + SOM).pdf Xilinx Memory Interface Solutions Data Sheet]
=== PL bank 13 (XC7Z020 only) ===Routing implemented on For Bora/BoraEVB systems: [[File:Bora SoM allows the use of bank 13's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependentzip]].
Pairs are highlighted with different colorsFor BoraX/BoraXEVB systems: [[File:BoraX-BoraXEVB-combined-routing. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohmzip]].
{| class="wikitable" border="1"| align="center" style="backgroundFor BoraLite/BoraXEVB systems:#f0f0f0;"|'''the presence of the Bora pin name'''| align="center" style="background:#f0f0f0;"|'''Individual net length<br>Lite adapter does not make sense to provide the routing information. Please refer to the [[mils]'''| align="center" style="background:#f0f0f0;"Programmable_logic_(BoraLite)|'''Intra-pair match<br>[milsProgrammable_logic_(BoraLite) page]'''| align="center" style="background:#f0f0f0;"|'''Inter-pair match<br>[mils]'''| align="center" style="background:#f0f0f0;"|'''Group Name'''|-| IO_L15N_T2_DQS_13||align="center"|1582,37||align="center"|25||align="center"|200||BANK13 Diff group 1|-| IO_L15P_T2_DQS_13||align="center"|1602,37||align="center"|25||align="center"|200||BANK13 Diff group 1|- style="background: gray"| IO_L16N_T2_13||align="center"|1589,32||align="center"|25||align="center"|200||BANK13 Diff group 1|- style="background: gray"| IO_L16P_T2_13||align="center"|1602,33||align="center"|25||align="center"|200||BANK13 Diff group 1|-| IO_L17N_T2_13||align="center"|1710,41||align="center"|25||align="center"|200||BANK13 Diff group 1|-| IO_L17P_T2_13||align="center"|1722,73||align="center"|25||align="center"|200||BANK13 Diff group 1|- style="background: gray"| IO_L18N_T2_13||align="center"|1720,53||align="center"|25||align="center"|200||BANK13 Diff group 1|- style="background: gray"| IO_L18P_T2_13||align="center"|1712,11||align="center"|25||align="center"|200||BANK13 Diff group 1|-| IO_L19N_T3_VREF_13||align="center"|1585,55||align="center"|25||align="center"|200||BANK13 Diff group 1|-| IO_L19P_T3_13||align="center"|1602,96||align="center"|25||align="center"|200||BANK13 Diff group 1|- style="background: gray"| IO_L20N_T3_13||align="center"|1623,95||align="center"|25||align="center"|200||BANK13 Diff group 1|- style="background: gray"| IO_L20P_T3_13||align="center"|1626,27||align="center"|25||align="center"|200||BANK13 Diff group 1|-| IO_L21N_T3_DQS_13||align="center"|1661,55||align="center"|25||align="center"|200||BANK13 Diff group 1|-| IO_L21P_T3_DQS_13||align="center"|1668,95||align="center"|25||align="center"|200||BANK13 Diff group 1|- style="background: gray"| IO_L22N_T3_13||align="center"|1592,18||align="center"|25||align="center"|200||BANK13 Diff group 1|- style="background: gray"| IO_L22P_T3_13||align="center"|1577,63||align="center"|25||align="center"|200||BANK13 Diff group 1|-style="background: black"| ''' '''|||||||||-| IO_L11N_T1_SRCC_13||align="center"|1702,04||align="center"|10||align="center"|50||BANK13 xRCC group|about information on internal BORA Lite routing. Please take carefully into account the design of the Carrier board considering every information related to the SO-| IO_L11P_T1_SRCC_13||align="center"|1705,07||align="center"|10||align="center"|50||BANK13 xRCC group|- style="background: gray"| IO_L12N_T1_MRCC_13||align="center"|1704,42||align="center"|10||align="center"|50||BANK13 xRCC group|- style="background: gray"| IO_L12P_T1_MRCC_13||align="center"|1703,11||align="center"|10||align="center"|50||BANK13 xRCC group|-| IO_L13N_T2_MRCC_13||align="center"|1731,33||align="center"|10||align="center"|50||BANK13 xRCC group|-| IO_L13P_T2_MRCC_13||align="center"|1732,15||align="center"|10||align="center"|50||BANK13 xRCC group|- style="background: gray"| IO_L14N_T2_SRCC_13||align="center"|1710,12||align="center"|10||align="center"|50||BANK13 xRCC group|- style="background: gray"| IO_L14P_T2_SRCC_13||align="center"|1716,36||align="center"|10||align="center"|50||BANK13 xRCC group|-|}DIMM socket and the tracenet on the Carrier
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