Bureaucrats, dave_user, Administrators
4,650
edits
Changes
→Connecting the PUDC_B pin
=== Connecting the PUDC_B pin ===
On Bora SOM, PUDC_B pin is (J2 connector, pin 15) connected to VDDIO_BANK34 (3.3V) via 10K resistor, thus [http://www.xilinx.com/support/answers/50802.html internal pull-up resistors are disabled on each SelectIO pin, until FPGA configuration completes].
Default behavior can be changed by setting PUDC_B pin (J2 - Pin 15) to logical 0 by appropriate circuitry at carrier board levelto set it to logical 0.
=== PS' I²C buses ===
