Changes

On Bora SOM, PUDC_B pin is connected to FPGA_VDDIO_BANK34 VDDIO_BANK34 (3.3V) via 10K resistor([http://www. This allows the external changes to the configuration of this xilinx.com/support/answers/50802.html internal pull-up resistors are disabled on each SelectIO pin, and the reusability of the same I/O pin after the until FPGA configurationcompletes]. In fact, PUDC_B pin  Default behavior can't be left floating before and during the configuration.So it is OK to connect changed by connecting PUDC_B pin (J2 - Pin 15) to '''P3V3_IOBANK''' via ground with 1K pull-up down resistor.There are no side effects on BORA SOM putting I/O into high Z stateat carrier board level.