Integration guide (Bora/BoraX/BoraLite)

Info Box Applies to Bora

Introduction

This page provides useful information and resources to system designers in order to integrate Bora SoMs in his/her application quickly. These information complement SoM-independent recommendations provided in the Carrier board design guidelines (SOM) page.

Several topics are covered, ranging from hardware issues to manufacturing aspects.

Advanced routing and carrier board design guidelines

Generally speaking, when designing a system-on-module (SoM) product it is impossible to know in advance the combination of interfaces and functionalities that will be implemented by the system integrator. This is even more true in case of Bora, due to the unprecedented flexibility and versatility of Zynq architecture. For this reason, Bora implements advanced routing schemes that, in combination with proper carrier board design, allow the implementation of high-speed complex interfaces that satisfy signal integrity requirements.

This chapter describes in detail such schemes and provides carrier board design guidelines accordingly.

In the following section the terms "Inter-pair matching" and "Intra-pair matching" are used. They indicate respectively:

• length matching among pairs belonging to the same class or group
• length matching between traces belonging to the same pair.

Suggested PCB specifications

	Min.	Typ.
Layers(number)	4	6
GND Plane Layers	1	2
Power Plane Layers	1	1
Vias hole (mechanical)* [mm]	0.3	-

*Smaller holes are deprecated because their limited current capacity and heat dissipation.

Power rails

Following power rails should be kept as short as possible and should be sized in order to minimize IR drop at maximum estimated current.

	Max estimated current	Required plane or copper areas
3.3V_SOM	application dependent	YES
VDDIO_BANK35	application dependent	NO
VDDIO_BANK13	application dependent	NO

Power consumptions related to some real world use cases can be found here. [TBD insert link]

Main SD/MMC interface

Signals: PS_MIO40_501, PS_MIO41_501, PS_MIO42_501, PS_MIO43_501, PS_MIO44_501, PS_MIO45_501.

Following table details routing rules implemented on Bora SoM.

	Value	UOM
Common Mode impedance	50	Ohm
Maximum Length Tolerance	200	mils

Main Gigabit Ethernet interface (ETH0)

Signals: ETH_TXRX0_P/ETH_TXRX0_M, ETH_TXRX1_P/ETH_TXRX1_M, ETH_TXRX2_P/ETH_TXRX2_M, ETH_TXRX3_P/ETH_TXRX3_M.

Following table details routing rules implemented on Bora SoM.

	Value	UOM
Common Mode impedance SOM	55	Ohm
Differential Mode impedance SOM	100	Ohm
Maximum Length Tolerance on SOM(intrapair)	10	mils
Maximum Length Tolerance on SOM(interpair)	400	mils

CAN interface

Signals: CAN_H/CAN_L.

Following table details routing rules implemented on Bora SoM.

	Value	UOM
Common Mode impedance SOM	-	Ohm
Differential Mode impedance SOM	110	Ohm
Maximum Length Tolerance on SOM(intrapair)	-	mils
Maximum Length Tolerance on SOM(interpair)	-	mils

XADC interface

Signals XADC_VP_R/XADC_VN_R (dedicated analog inputs).

Following table details routing rules implemented on Bora SoM.

	Value	UOM
Differential Mode impedance typ	100	Ohm
Maximum Length Tolerance on SOM(intrapair)	-	mils
Maximum Length Tolerance on SOM(interpair)	-	mils
Intrapair Matching required	10

PS' I²C buses

Xilinx released an important Answer Record related to Zynq PS I2C Controller on 19th September 2014 (http://www.xilinx.com/support/answers/61861.html), a long period after Bora public lunch.

A technical and functional assessment has been performed to find out the best solution to cope with this issue on Bora based systems (1). Bora SoM is conceived to address a wide range of different application environments that are by definition unknown at design stage. Therefore it is virtually impossible to find a one-size-fits-all solution that does not limit somehow Bora functionalities and is backward compatible. The followed approach has aimed to preserve:

• system reliability
• backward compatibility
• system designer's freedom to choose the appropriate solution for his/her specific application.

Thanks to the Bora's I2C0 topology, Bora has undergone no changes to satisfy these requirements. The SoM in fact allows for:

• implementing, at carrier board level, complex glitch filtering strategies such as the one suggested by Xilinx AR# 61861
• avoiding waste of resources of PL if not strictly necessary (for instance when I2C0 functionality is not required at all).

The configuration depicted by the following figure shows in principle a solution integrating the workaround suggested by Xilinx AR# 61861:

• PS I2C0 controller's signals are routed to PL via EMIO routing
• MIO46/47 are disabled
• glitch filter is digitally implemented in PL
• I2C0 SDA and SCL lines are physically connected to PL at carrier board level.

(1) What here described refers to I2C0 controller that by default is routed on pins MIO46 and MIO47.

How to implement workaround suggested by Xilinx on BoraEVB

Plase note that the reference project with I2C glitch filter implemented in FPGA is available on request. Plase contact support-bora@dave.eu

This project, built with Vivado 2014.4, is based on the default project for BELK (BORA rev.B and BORAevb rev.A).

Here we have changed I2C0 signals routing to EMIO pins through FPGA, implementing the I2C glitch filter with VHDL example code provided in Xilinx AR# 61861. The MIO46-MIO47 is then configured as input GPIO. This is accomplished from the FSBL generated within the provided project.

I2C interface is routed through FPGA to pins on BANK35:

• I2C SCL => IO_L9P_T1_DQS_AD3P_35
• I2C SDA => IO_L9N_T1_DQS_AD3N_35

The BANK35 MUST be powered at 1.8V

To test the solution, please make these connections on BORAevb rev.A:

• 1.8V supply for BANK35 : (J11.2 to J11.7)
• I2C SCL : JP10.14 to JP21.5
• I2C SDA : JP10.16 to JP21.3

PL bank 34

Routing implemented on Bora SoM allows the use of bank 34's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.

Pairs are highlighted with different colors. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohm.

Bora pin name	Individual trace length [mils]	Intra-pair match [mils]	Inter-pair match [mils]	Group name
IO_L1N_T0_34	1751,37	25	300	BANK34 Diff group 1
IO_L1P_T0_34	1749,02	25	300	BANK34 Diff group 1
IO_L2N_T0_34	1625,68	25	300	BANK34 Diff group 1
IO_L2P_T0_34	1624,91	25	300	BANK34 Diff group 1
IO_L4N_T0_34	1581,72	25	300	BANK34 Diff group 1
IO_L4P_T0_34	1582,11	25	300	BANK34 Diff group 1
IO_L5N_T0_34	1769,81	25	300	BANK34 Diff group 1
IO_L5P_T0_34	1776,23	25	300	BANK34 Diff group 1
IO_L7N_T1_34	1566,52	25	300	BANK34 Diff group 1
IO_L7P_T1_34	1569,36	25	300	BANK34 Diff group 1
IO_L9N_T1_DQS_34	1490,25	25	300	BANK34 Diff group 1
IO_L9P_T1_DQS_34	1498,04	25	300	BANK34 Diff group 1
IO_L10N_T1_34	1516,97	25	300	BANK34 Diff group 1
IO_L10P_T1_34	1517,37	25	300	BANK34 Diff group 1
IO_L15N_T2_DQS_34	1610,74	25	300	BANK34 Diff group 1
IO_L15P_T2_DQS_34	1602,81	25	300	BANK34 Diff group 1
IO_L16N_T2_34	1601,55	25	300	BANK34 Diff group 1
IO_L16P_T2_34	1616,03	25	300	BANK34 Diff group 1
IO_L17N_T2_34	1574,33	25	300	BANK34 Diff group 1
IO_L17P_T2_34	1593,38	25	300	BANK34 Diff group 1
IO_L18N_T2_34	1740,11	25	300	BANK34 Diff group 1
IO_L18P_T2_34	1750,54	25	300	BANK34 Diff group 1
IO_L20N_T3_34	1588,01	25	300	BANK34 Diff group 1
IO_L20P_T3_34	1585,53	25	300	BANK34 Diff group 1
IO_L21N_T3_DQS_34	1567,1	25	300	BANK34 Diff group 1
IO_L21P_T3_DQS_34	1570,96	25	300	BANK34 Diff group 1
IO_L22N_T3_34	1619,26	25	300	BANK34 Diff group 1
IO_L22P_T3_34	1622,13	25	300	BANK34 Diff group 1
IO_L23N_T3_34	1769,71	25	300	BANK34 Diff group 1
IO_L23P_T3_34	1775,52	25	300	BANK34 Diff group 1
IO_L24N_T3_34	1772,07	25	300	BANK34 Diff group 1
IO_L24P_T3_34	1774,49	25	300	BANK34 Diff group 1
IO_L11N_T1_SRCC_34	1817,43	10	50	BANK34 xRCC group
IO_L11P_T1_SRCC_34	1823,9	10	50	BANK34 xRCC group
IO_L12N_T1_MRCC_34	1844,2	10	50	BANK34 xRCC group
IO_L12P_T1_MRCC_34	1841,36	10	50	BANK34 xRCC group
IO_L13N_T1_MRCC_34	1811,51	10	50	BANK34 xRCC group
IO_L13P_T1_MRCC_34	1818,58	10	50	BANK34 xRCC group
IO_L14N_T2_SRCC_34	1818,78	10	50	BANK34 xRCC group
IO_L14P_T2_SRCC_34	1822,02	10	50	BANK34 xRCC group

About power voltage, take into consideration that Bank 35 is fixed at 3.3V.

PL bank 35

On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Signals have been grouped in the following classes:

• FDDR_ADDR
• FDDR_CK
• FDDR_BYTE0
• FDDR_BYTE1

Some of them are differential pairs. These kind of signals are highlighted in dark grey in the following sections where, for each signal, detailed information are provided, related to routing rules implemented on Bora SoM and carrier board guidelines.

Following tables indicates general recommended rules for single-ended and differantial pairs on carrier board in terms of impedence and isolation.

Differential pairs:

	Value	UOM
Common Mode impedance typ	55	Ohm
Differential Mode impedance typ	100	Ohm
Isolation	4x	gap

Single-ended signals:

	Value	UOM
Common Mode impedance typ	55	Ohm
Isolation	2x	width

About power voltage, Bank 35 is configurable and must be powered by carrier board.

Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs.

FDDR_ADDR class

Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_ADDR class signals. The picture shows connection scheme and the nomenclature used in the table.

Bora pin name	Group name	Carrier board net name	SoM routing rules and specifications			Carrier board guidelines
			Actual length [mils]	Max length match [mils]	Nominal max length [mils]	AD_A2 length match [mils]	AD_AT length match [mils]	AD_AS1 length match [mils]	AD_AS1 max length [mils]	AD_AT max length [mils]	AD_A2+AD_AS1 max length [mils]
IO_L17N_T2_AD5N_35	FDDR_ADDR	FDDR_ADDR_3	1832	80	1912	40	100	50	60	400	2100
IO_L20P_T3_AD6P_35	FDDR_ADDR	FDDR_BA_2	1853,4	80	1912	40	100	50	60	400	2100
IO_L16N_T2_35	FDDR_ADDR	FDDR_ADDR_5	1832	80	1912	40	100	50	60	400	2100
IO_L18N_T2_AD13N_35	FDDR_ADDR	FDDR_ADDR_1	1832	80	1912	40	100	50	60	400	2100
IO_L24N_T3_AD15N_35	FDDR_ADDR	FDDR_CKE_0	1834,3	80	1912	40	100	50	60	400	2100
IO_L23P_T3_35	FDDR_ADDR	FDDR_CAS_N	1857,01	80	1912	40	100	50	60	400	2100
IO_L14N_T2_AD4N_SRCC_35	FDDR_ADDR	FDDR_ADDR_9	1832	80	1912	40	100	50	60	400	2100
IO_L24P_T3_AD15P_35	FDDR_ADDR	FDDR_CS0_N	1832	80	1912	40	100	50	60	400	2100
IO_L14P_T2_AD4P_SRCC_35	FDDR_ADDR	FDDR_ADDR_10	1832	80	1912	40	100	50	60	400	2100
IO_L15P_T2_DQS_AD12P_35	FDDR_ADDR	FDDR_ADDR_8	1832	80	1912	40	100	50	60	400	2100
IO_L15N_T2_DQS_AD12N_35	FDDR_ADDR	FDDR_ADDR_7	1832	80	1912	40	100	50	60	400	2100
IO_L12N_T1_MRCC_35	FDDR_ADDR	FDDR_RESET_N	1832	80	1912	40	100	50	60	400	2100
IO_L13P_T2_MRCC_35	FDDR_ADDR	FDDR_ADDR_12	1832	80	1912	40	100	50	60	400	2100
IO_L13N_T2_MRCC_35	FDDR_ADDR	FDDR_ADDR_11	1832	80	1912	40	100	50	60	400	2100
IO_25_35	FDDR_ADDR	FDDR_ODT_0	1832	80	1912	40	100	50	60	400	2100
IO_L23N_T3_35	FDDR_ADDR	FDDR_WE_N	1869,66	80	1912	40	100	50	60	400	2100
IO_L17P_T2_AD5P_35	FDDR_ADDR	FDDR_ADDR_4	1832	80	1912	40	100	50	60	400	2100
IO_L22N_T3_AD7N_35	FDDR_ADDR	FDDR_RAS_N	1832	80	1912	40	100	50	60	400	2100
IO_L20N_T3_AD6N_35	FDDR_ADDR	FDDR_BA_1	1832	80	1912	40	100	50	60	400	2100
IO_L18P_T2_AD13P_35	FDDR_ADDR	FDDR_ADDR_2	1853,7	80	1912	40	100	50	60	400	2100
IO_L16P_T2_35	FDDR_ADDR	FDDR_ADDR_6	1832	80	1912	40	100	50	60	400	2100
IO_L22P_T3_AD7P_35	FDDR_ADDR	FDDR_BA_0	1850,82	80	1912	40	100	50	60	400	2100
IO_L19P_T3_35	FDDR_ADDR	FDDR_ADDR_0	1836,73	80	1912	40	100	50	60	400	2100

FDDR_CK class

Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_CK class signals. The picture shows connection scheme and the nomenclature used in the table.

Bora pin name	Group name	Carrier board net name	SoM routing rules and specifications				Carrier board guidelines
			Actual length [mils]	Intra-pair match [mils]	Max length match (with respect to FDDR_ADDR group) [mils]	Nominal max length [mils]	Intra-pair match [mils]	CK_A2 pair match (with respect to FDDR_ADDR) [mils]	CK_AT intra-pair match [mils]	CK_AS1 match (with respect to FDDR_ADDR) [mils]	CK_AS1 max length [mils]	CK_AT maximum length [mils]	CK_AT pair match (with respect to FDDR_ADDR) [mils]	CK_A2+CK_AS1 max length [mils]
IO_L21P_T3_DQS_AD14P_35	FDDR_CK	FDDR_CK_P0	1900,39	5	80	1912	10	40	5	50	60	400	100	2100
IO_L21N_T3_DQS_AD14N_35	FDDR_CK	FDDR_CK_N0	1898,17	5	80	1912	10	40	5	50	60	400	100	2100

FDDR_BYTE0 class

Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE0 class signals.

Pin Name	Group name	Carrier board net name	SoM routing rules and specifications				Carrier board guidelines
			Actual length [mils]	Max length match [mils]	Max inter-pair match length on SOM [mils]	Nominal max length [mils]	Group match (mandatory) [mils]	Intra-pair match (mandatory) [mils]	Max length [mils]
IO_L2N_T0_AD8N_35	FDDR_BYTE0	FDDR_DQ_2	1222,66	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L6P_T0_35	FDDR_BYTE0	FDDR_DQ_7	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L5P_T0_AD9P_35	FDDR_BYTE0	FDDR_DQ_5	1226,42	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L4P_T0_35	FDDR_BYTE0	FDDR_DQ_3	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L2P_T0_AD8P_35	FDDR_BYTE0	FDDR_DQ_1	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L1N_T0_AD0N_35	FDDR_BYTE0	FDDR_DQ_0	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L4N_T0_35	FDDR_BYTE0	FDDR_DQ_4	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L5N_T0_AD9N_35	FDDR_BYTE0	FDDR_DQ_6	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L1P_T0_AD0P_35	FDDR_BYTE0	FDDR_DM_0	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L3P_T0_DQS_AD1P_35	FDDR_BYTE0	FDDR_DQS_P0	1221,04	15	5	1230	25	5	CK_A2+CK_AS1(max)
IO_L3N_T0_DQS_AD1N_35	FDDR_BYTE0	FDDR_DQS_N0	1219,42	15	5	1230	25	5	CK_A2+CK_AS1(max)

FDDR_BYTE1 class

Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE1 class signals.

Pin Name	Group name	Carrier board net name	SoM routing rules and specifications				Carrier board guidelines
			Actual length [mils]	Max length match [mils]	Max inter-pair match length on SOM [mils]	Nominal max length [mils]	Group match (mandatory) [mils]	Intra-pair match (mandatory) [mils]	Max length [mils]
IO_L10N_T1_AD11N_35	FDDR_BYTE1	FDDR_DQ_12	1345,93	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L10P_T1_AD11P_35	FDDR_BYTE1	FDDR_DQ_11	1345,93	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L11P_T1_SRCC_35	FDDR_BYTE1	FDDR_DQ_13	1353,43	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L12P_T1_MRCC_35	FDDR_BYTE1	FDDR_DQ_15	1341,3	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L11N_T1_SRCC_35	FDDR_BYTE1	FDDR_DQ_14	1340	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L8P_T1_AD10P_35	FDDR_BYTE1	FDDR_DQ_9	1340	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L7N_T1_AD2N_35	FDDR_BYTE1	FDDR_DQ_8	1340	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L8N_T1_AD10N_35	FDDR_BYTE1	FDDR_DQ_10	1340	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L7P_T1_AD2P_35	FDDR_BYTE1	FDDR_DM_1	1345,93	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L9P_T1_DQS_AD3P_35	FDDR_BYTE1	FDDR_DQS_P1	1354,26	15	5	1355	20	5	CK_A2+CK_AS1(max)
IO_L9N_T1_DQS_AD3N_35	FDDR_BYTE1	FDDR_DQS_N1	1350,66	15	5	1355	20	5	CK_A2+CK_AS1(max)

VREF

Recommendations:

• use a "T" connection as shown by following picture
• use 20+ mils trace
• place bypass capacitors as close as possible to power balls.

Related Xilinx documentation

• Xilinx Memory Interface Solutions UG586
• Xilinx Memory Interface Solutions Data Sheet

PL bank 13 (XC7Z020 only)

Routing implemented on Bora SoM allows the use of bank 13's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.

Pairs are highlighted with different colors. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohm.

Bora pin name	Individual net length [mils]	Intra-pair match [mils]	Inter-pair match [mils]	Group Name
IO_L15N_T2_DQS_13	1582,37	25	200	BANK13 Diff group 1
IO_L15P_T2_DQS_13	1602,37	25	200	BANK13 Diff group 1
IO_L16N_T2_13	1589,32	25	200	BANK13 Diff group 1
IO_L16P_T2_13	1602,33	25	200	BANK13 Diff group 1
IO_L17N_T2_13	1710,41	25	200	BANK13 Diff group 1
IO_L17P_T2_13	1722,73	25	200	BANK13 Diff group 1
IO_L18N_T2_13	1720,53	25	200	BANK13 Diff group 1
IO_L18P_T2_13	1712,11	25	200	BANK13 Diff group 1
IO_L19N_T3_VREF_13	1585,55	25	200	BANK13 Diff group 1
IO_L19P_T3_13	1602,96	25	200	BANK13 Diff group 1
IO_L20N_T3_13	1623,95	25	200	BANK13 Diff group 1
IO_L20P_T3_13	1626,27	25	200	BANK13 Diff group 1
IO_L21N_T3_DQS_13	1661,55	25	200	BANK13 Diff group 1
IO_L21P_T3_DQS_13	1668,95	25	200	BANK13 Diff group 1
IO_L22N_T3_13	1592,18	25	200	BANK13 Diff group 1
IO_L22P_T3_13	1577,63	25	200	BANK13 Diff group 1
IO_L11N_T1_SRCC_13	1702,04	10	50	BANK13 xRCC group
IO_L11P_T1_SRCC_13	1705,07	10	50	BANK13 xRCC group
IO_L12N_T1_MRCC_13	1704,42	10	50	BANK13 xRCC group
IO_L12P_T1_MRCC_13	1703,11	10	50	BANK13 xRCC group
IO_L13N_T2_MRCC_13	1731,33	10	50	BANK13 xRCC group
IO_L13P_T2_MRCC_13	1732,15	10	50	BANK13 xRCC group
IO_L14N_T2_SRCC_13	1710,12	10	50	BANK13 xRCC group
IO_L14P_T2_SRCC_13	1716,36	10	50	BANK13 xRCC group