3,260
edits
Changes
m
→PS' I²C buses
(1) What here described refers to I2C0 controller that by default is routed on pins MIO46 and MIO47.
==== How to implement workaround suggested by Xilinx on BoraEVB====
''Reference project with I2C glitch filter implemented in FPGA is available on request.''
This project, built with Vivado 2014.4, is based on the default project for BELK (BORA rev.B and BORAevb rev.A).
Here we have changed I2C0 signals routing to EMIO pins through FPGA, implementing the I2C glitch filter with VHDL example code provided in Xilinx AR# 61861.
The MIO46-MIO47 is then configured as input GPIO. This is accomplished from the FSBL generated within the provided project.
I2C interface is routed through FPGA to pins on BANK35:
* I2C SCL => IO_L9P_T1_DQS_AD3P_35
* I2C SDA => IO_L9N_T1_DQS_AD3N_35
The BANK35 MUST be powered at 1.8V
To test the solution, please make these connections on BORAevb rev.A:
* 1.8V supply for BANK35 : (J11.2 to J11.7)
* I2C SCL : JP10.14 to JP21.5
* I2C SDA : JP10.16 to JP21.3
=== PL bank 34 ===
