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→PS' I²C buses
Xilinx released an important Answer Record related to Zynq PS I2C Controller on 19th September 2014 (http://www.xilinx.com/support/answers/61861.html), a long period after Bora public lunch.
A technical and functional assessment has been performed to find out the best solution to cope with this issue on Bora based systems (1). Bora SoM is conceived to address a wide range of different application environments that are by definition unknown at design stage. Therefore it is virtually impossible to find a one-size-fits-all solution that does not limit somehow Bora functionalities and is backward compatible. The followed approach has aimed to preserve :
* system reliability
* backward compatibility
* system designer's freedom to choose the appropriate solution for his/her specific application.
Thanks to the Bora's I2C0 topology, Bora has undergone no changes to satisfy these requirements. The SoM in fact allows tofor:* implementimplementing, at carrier board level, complex glitch filtering strategies such as the one suggested by Xilinx AR# 61861* avoid to avoiding waste of resources of PL if not strictly necessary (for instance when I2C0 functionality is not required at all).
The configuration depicted by the following figure shows in principle a solution integrating the workaround suggested by Xilinx AR# 61861:
[[File:Bora-i2c-glitch-filter.png]]
(1) What here described refers to I2C0 controller that by default is routed on pins MIO46 and MIO47.
