dave_user, Administrators
5,171
edits
Changes
no edit summary
{{Applies To Bora}}
{{Applies To BoraX}}
{{Applies To BoraLite}}
{{AppliesToBORA AN}}
{{AppliesToBORA Xpress AN}}
{{AppliesToBORA Lite AN}}
{{InfoBoxBottom}}
<section begin=Body/>=Introduction=Integration guide==
This page provides useful information and resources to system designers in order to integrate Bora SoMs in his/her application quickly. These information complement SoM-independent recommendations provided in the [[Carrier_board_design_guidelines_(SOM) | Carrier board design guidelines (SOM)]] page.
Several topics are covered, ranging from hardware issues to manufacturing aspects.
=== Advanced routing and carrier board design guidelines ===
Generally speaking, when designing a system-on-module (SoM) product it is impossible to know in advance the combination of interfaces and functionalities that will be implemented by the system integrator. This is even more true in case of Bora, due to the unprecedented flexibility and versatility of Zynq architecture. For this reason, Bora implements advanced routing schemes that, in combination with proper carrier board design, allow the implementation of high-speed complex interfaces that satisfy signal integrity requirements.
* length matching between traces belonging to the same pair.
==== Suggested PCB specifications ====
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|''' '''
<nowiki>*</nowiki>Smaller holes are deprecated because their limited current capacity and heat dissipation.
==== Power rails ====
Following power rails should be kept as short as possible and should be sized in order to minimize IR drop at maximum estimated current.
|}
==== Main SD/MMC interface ====
Signals: PS_MIO40_501, PS_MIO41_501, PS_MIO42_501, PS_MIO43_501, PS_MIO44_501, PS_MIO45_501.
|}
==== Main Gigabit Ethernet interface (ETH0) ====
Signals: ETH_TXRX0_P/ETH_TXRX0_M, ETH_TXRX1_P/ETH_TXRX1_M, ETH_TXRX2_P/ETH_TXRX2_M, ETH_TXRX3_P/ETH_TXRX3_M.
|}
==== CAN interface ====
Signals: CAN_H/CAN_L.
|}
==== XADC interface ====
Signals XADC_VP_R/XADC_VN_R (dedicated analog inputs).
|}
==== Connecting the PUDC_B pin ====
On Bora SOM, PUDC_B pin is (J2 connector, pin 15) connected to VDDIO_BANK34 (3.3V) via 10K resistor, thus [http://www.xilinx.com/support/answers/50802.html internal pull-up resistors are disabled on each SelectIO pin, until FPGA configuration completes].
Default behavior can be changed by appropriate circuitry at carrier board level to set it to logical 0.
==== PS' I²C buses ====
Xilinx released an important Answer Record related to Zynq PS I2C Controller on 19th September 2014 (http://www.xilinx.com/support/answers/61861.html), a long period after Bora public lunch.
[[File:Bora-i2c-glitch-filter.png|thumb|center|600px]]
[[File:BoraLite-i2c-glitch-filter.jpg|thumb|center|600px]]
(1) What here described refers to I2C0 controller that by default is routed on pins MIO46 and MIO47.
===== How to implement workaround suggested by Xilinx on BoraEVB=====
''Plase note that the reference project with I2C glitch filter implemented in FPGA is available on request. Plase contact [mailto:support-borahelpdesk@dave.eu support-borahelpdesk@dave.eu]''
This project, built with Vivado 2014.4, is based on the default project for BELK (BORA rev.B and BORAevb rev.A).
The BANK35 MUST be powered at 1.8V
====== Test on BoraEVB ======
To test the solution, please make these connections on BORAevb rev.A:
* 1.8V supply for BANK35 : (J11.2 to J11.7)
* I2C SDA : JP10.16 to JP21.3
====== Test on BoraXEVB ======To test the solution, please make these connections on BoraXEVB:* 1.8V supply for BANK35 : please refer to VDDIO_BANK35 possibility on BoraXEVB schematics* populate RPACK RP87* I2C SCL : JP30.9 to JP29.5* I2C SDA : JP30.11 to JP29.3 ====Programmable logic (PL)====
For Bora SOM please refer to the following links:
*[[BORA_SOM/BORA_Hardware/Peripherals/Programmable_logic_(BoraFPGA)#Routing_information|bank 34]]*[[BORA_SOM/BORA_Hardware/Peripherals/Programmable_logic_(BoraFPGA)#Routing_information_2|bank 35]]*[[BORA_SOM/BORA_Hardware/Peripherals/Programmable_logic_(BoraFPGA)#Routing_information_3|bank 13]] For BoraX SOM please refer to the [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Programmable_logic_(FPGA)|page]]. For BoraLite SOM please refer to the [[BORA_Lite_SOM/BORA_Lite_Hardware/Peripherals/Programmable_logic_(FPGA)|page]].
A spreadsheet is available for download here, containing detailed information about signals routing. These information can be used to check nets matching of the overall system (carrier board + SOM).
For BoraX/BoraXEVB systems: [[File:BoraX-BoraXEVB-combined-routing.zip]].
For BoraLite/BoraXEVB systems: the presence of the Bora Lite adapter does not make sense to provide the routing information. Please refer to the [[BORA_Lite_SOM/BORA_Lite_Hardware/Peripherals/Programmable_logic_(FPGA)| Programmable logic page]] about information on internal BORA Lite routing. Please take carefully into account the design of the Carrier board considering every information related to the SO-DIMM socket and the tracenet on the Carrier
<section end=Body/>
