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{{Applies To Bora}}
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{{Applies To BoraLite}}
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<section begin=Body/>=Introduction=Integration guide==
This page provides useful information and resources to system designers in order to integrate Bora SoMs in his/her application quickly. These information complement SoM-independent recommendations provided in the [[Carrier_board_design_guidelines_(SOM) | Carrier board design guidelines (SOM)]] page.
Several topics are covered, ranging from hardware issues to manufacturing aspects.
=== Advanced routing and carrier board design guidelines ===
Generally speaking, when designing a system-on-module (SoM) product it is impossible to know in advance the combination of interfaces and functionalities that will be implemented by the system integrator. This is even more true in case of Bora, due to the unprecedented flexibility and versatility of Zynq architecture. For this reason, Bora implements advanced routing schemes that, in combination with proper carrier board design, allow the implementation of high-speed complex interfaces that satisfy signal integrity requirements.
* length matching between traces belonging to the same pair.
==== Suggested PCB specifications ====
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|''' '''
<nowiki>*</nowiki>Smaller holes are deprecated because their limited current capacity and heat dissipation.
==== Power rails ====
Following power rails should be kept as short as possible and should be sized in order to minimize IR drop at maximum estimated current.
|}
Signals: PS_MIO40_501, PS_MIO41_501, PS_MIO42_501, PS_MIO43_501, PS_MIO44_501, PS_MIO45_501.
|}
==== Main Gigabit Ethernet interface (ETH0) ====
Signals: ETH_TXRX0_P/ETH_TXRX0_M, ETH_TXRX1_P/ETH_TXRX1_M, ETH_TXRX2_P/ETH_TXRX2_M, ETH_TXRX3_P/ETH_TXRX3_M.
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==== CAN interface ====
Signals: CAN_H/CAN_L.
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==== XADC interface ====
Signals XADC_VP_R/XADC_VN_R (dedicated analog inputs).
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==== Connecting the PUDC_B pin ==== On Bora SOM, PUDC_B pin is (J2 connector, pin 15) connected to VDDIO_BANK34 (3.3V) via 10K resistor, thus [http://www.xilinx.com/support/answers/50802.html internal pull-up resistors are disabled on each SelectIO pin, until FPGA configuration completes]. Default behavior can be changed by appropriate circuitry at carrier board level to set it to logical 0. ==== PS' I²C buses ====
Xilinx released an important Answer Record related to Zynq PS I2C Controller on 19th September 2014 (http://www.xilinx.com/support/answers/61861.html), a long period after Bora public lunch.
A technical and functional assessment has been performed to find out the best solution to cope with this issue on Bora based systems (1). Bora SoM is conceived to address a wide range of different application environments that are by definition unknown at design stage. Therefore it is virtually impossible to find a one-size-fits-all solution that does not limit somehow Bora functionalities and is backward compatible. The followed approach has aimed to preserve :
* system reliability
* backward compatibility
* system designer's freedom to choose the appropriate solution for his/her specific application.
Thanks to the Bora's I2C0 topology, Bora has undergone no changes to satisfy these requirements. The SoM in fact allows tofor:* implementimplementing, at carrier board level, complex glitch filtering strategies such as the one suggested by Xilinx AR# 61861* avoid to avoiding waste of resources of PL if not strictly necessary (for instance when I2C0 functionality is not required at all).
The configuration depicted by the following figure shows in principle a solution integrating the workaround suggested by Xilinx AR# 61861:
[[File:Bora-i2c-glitch-filter.png|thumb|center|600px]][[File:BoraLite-i2c-glitch-filter.jpg|thumb|center|600px]]
(1) What here described refers to I2C0 controller that by default is routed on pins MIO46 and MIO47.
=== PL bank 34 ===Routing implemented on Bora SoM allows the use of bank 34's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted How to implement workaround suggested by the following table that details routing rules Xilinx on Bora module. No carrier board guidelines can be provided, because these are application-dependent.BoraEVB=====
For BoraLite SOM please refer to the [[File:FDDR_ADDR.pngBORA_Lite_SOM/BORA_Lite_Hardware/Peripherals/Programmable_logic_(FPGA)|page]].
====Traces length matching====
A spreadsheet is available for download here, containing detailed information about signals routing. These information can be used to check nets matching of the overall system (carrier board + SOM).