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{{Applies To BoraX}}
{{Applies To BoraLite}}
{{AppliesToBORA AN}}
{{AppliesToBORA Xpress AN}}
{{AppliesToBORA Lite AN}}
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===== How to implement workaround suggested by Xilinx on BoraEVB=====
''Plase note that the reference project with I2C glitch filter implemented in FPGA is available on request. Plase contact [mailto:support-borahelpdesk@dave.eu support-borahelpdesk@dave.eu]''
This project, built with Vivado 2014.4, is based on the default project for BELK (BORA rev.B and BORAevb rev.A).
====Programmable logic (PL)====
For Bora SOM please refer to the following links:
*[[BORA_SOM/BORA_Hardware/Peripherals/Programmable_logic_(BoraFPGA)#Routing_information|bank 34]]*[[BORA_SOM/BORA_Hardware/Peripherals/Programmable_logic_(BoraFPGA)#Routing_information_2|bank 35]]*[[BORA_SOM/BORA_Hardware/Peripherals/Programmable_logic_(BoraFPGA)#Routing_information_3|bank 13]]
For BoraX SOM please refer to the [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Programmable_logic_(BORAXpressFPGA)|page]].
For BoraLite SOM please refer to the [[BORA_Lite_SOM/BORA_Lite_Hardware/Peripherals/Programmable_logic_(BoraLiteFPGA)|page]].
====Traces length matching====
For BoraX/BoraXEVB systems: [[File:BoraX-BoraXEVB-combined-routing.zip]].
For BoraLite/BoraXEVB systems: the presence of the Bora Lite adapter does not make sense to provide the routing information. Please refer to the [[BORA_Lite_SOM/BORA_Lite_Hardware/Peripherals/Programmable_logic_(BoraLiteFPGA)| Programmable_logic_(BoraLite) Programmable logic page]] about information on internal BORA Lite routing. Please take carefully into account the design of the Carrier board considering every information related to the SO-DIMM socket and the tracenet on the Carrier
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