View source for Integration guide (Bora/BoraX/BoraLite)

==Integration guide==

This page provides useful information and resources to system designers in order to integrate Bora SoMs in his/her application quickly. These information complement SoM-independent recommendations provided in the [[Carrier_board_design_guidelines_(SOM) | Carrier board design guidelines (SOM)]] page.

Several topics are covered, ranging from hardware issues to manufacturing aspects.

=== Advanced routing and carrier board design guidelines ===

Generally speaking, when designing a system-on-module (SoM) product it is impossible to know in advance the combination of interfaces and functionalities that will be implemented by the system integrator. This is even more true in case of Bora, due to the unprecedented flexibility and versatility of Zynq architecture. For this reason, Bora implements advanced routing schemes that, in combination with proper carrier board design, allow the implementation of high-speed complex interfaces that satisfy signal integrity requirements.

This chapter describes in detail such schemes and provides carrier board design guidelines accordingly. 

In the following section the terms "Inter-pair matching" and "Intra-pair matching" are used. They indicate respectively:
* length matching among pairs belonging to the same class or group
* length matching between traces belonging to the same pair.

==== Suggested PCB specifications ====
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''    '''
| align="center" style="background:#f0f0f0;"|'''Min.'''
| align="center" style="background:#f0f0f0;"|'''Typ.'''
|-
| Layers(number)||align="center"|4||align="center"|6
|-
| GND Plane Layers||align="center"|1||align="center"|2
|-
| Power Plane Layers||align="center"|1||align="center"|1
|-
| Vias hole (mechanical)* [mm]||align="center"|0.3||align="center"|-
|}

<nowiki>*</nowiki>Smaller holes are deprecated because their limited current capacity and heat dissipation.

==== Power rails ====
Following power rails should be kept as short as possible and should be sized in order to minimize IR drop at maximum estimated current.

{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''                     '''
| align="center" style="background:#f0f0f0;"|'''Max estimated current'''
| align="center" style="background:#f0f0f0;"|'''Required plane or copper areas'''
|-
| 3.3V_SOM||align="center"|application dependent||align="center"|YES
|-
| VDDIO_BANK35||align="center"|application dependent||align="center"|NO
|-
| VDDIO_BANK13||align="center"|application dependent||align="center"|NO
|-
|}

==== Main SD/MMC interface ====
Signals: PS_MIO40_501, PS_MIO41_501, PS_MIO42_501, PS_MIO43_501, PS_MIO44_501, PS_MIO45_501.

Following table details routing rules implemented on Bora SoM.
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''       '''
| align="center" style="background:#f0f0f0;"|''' Value '''
| align="center" style="background:#f0f0f0;"|'''  UOM '''
|- 
| Common Mode impedance||align="center"|50||align="center"|Ohm
|-
| Maximum Length Tolerance||align="center"|200||align="center"|mils
|-
|}

==== Main Gigabit Ethernet interface (ETH0) ====
Signals: ETH_TXRX0_P/ETH_TXRX0_M, ETH_TXRX1_P/ETH_TXRX1_M, ETH_TXRX2_P/ETH_TXRX2_M, ETH_TXRX3_P/ETH_TXRX3_M.

Following table details routing rules implemented on Bora SoM.
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''       '''
| align="center" style="background:#f0f0f0;"|''' Value '''
| align="center" style="background:#f0f0f0;"|'''  UOM '''
|-
| Common Mode impedance SOM||align="center"|55||align="center"|Ohm
|-
| Differential Mode impedance SOM||align="center"|100||align="center"|Ohm
|-
| Maximum Length Tolerance on SOM(intrapair)||align="center"|10||align="center"|mils
|-
| Maximum Length Tolerance on SOM(interpair)||align="center"|400||align="center"|mils
|-
|}

==== CAN interface ====
Signals: CAN_H/CAN_L.

Following table details routing rules implemented on Bora SoM.
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''       '''
| align="center" style="background:#f0f0f0;"|''' Value '''
| align="center" style="background:#f0f0f0;"|'''  UOM '''
|-
| Common Mode impedance SOM||align="center"|-||align="center"|Ohm
|-
| Differential Mode impedance SOM||align="center"|110||align="center"|Ohm
|-
| Maximum Length Tolerance on SOM(intrapair)||align="center"|-||align="center"|mils
|-
| Maximum Length Tolerance on SOM(interpair)||align="center"|-||align="center"|mils
|-
|}

==== XADC interface ====
Signals XADC_VP_R/XADC_VN_R (dedicated analog inputs).

Following table details routing rules implemented on Bora SoM.
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''       '''
| align="center" style="background:#f0f0f0;"|''' Value '''
| align="center" style="background:#f0f0f0;"|'''  UOM '''
|-
| Differential Mode impedance typ||align="center"|100||align="center"|Ohm
|-
| Maximum Length Tolerance on SOM(intrapair)||align="center"|-||align="center"|mils
|-
| Maximum Length Tolerance on SOM(interpair)||align="center"|-||align="center"|mils
|-
| Intrapair Matching required||align="center"|10||
|-
|}

==== Connecting the PUDC_B pin ====

On Bora SOM, PUDC_B pin is (J2 connector, pin 15) connected to VDDIO_BANK34 (3.3V) via 10K resistor, thus [http://www.xilinx.com/support/answers/50802.html internal pull-up resistors are disabled on each SelectIO pin, until FPGA configuration completes]. 

Default behavior can be changed by appropriate circuitry at carrier board level to set it to logical 0.

==== PS' I²C buses ====

Xilinx released an important Answer Record related to Zynq PS I2C Controller on 19th September 2014 (http://www.xilinx.com/support/answers/61861.html), a long period after Bora public lunch.

A technical and functional assessment has been performed to find out the best solution to cope with this issue on Bora based systems (1). Bora SoM is conceived to address a wide range of different application environments that are by definition unknown at design stage. Therefore it is virtually impossible to find a one-size-fits-all solution that does not limit somehow Bora functionalities and is backward compatible. The followed approach has aimed to preserve:
* system reliability
* backward compatibility 
* system designer's freedom to choose the appropriate solution for his/her specific application.

Thanks to the Bora's I2C0 topology, Bora has undergone no changes to satisfy these requirements. The SoM in fact allows for:
* implementing, at carrier board level, complex glitch filtering strategies such as the one suggested by Xilinx AR# 61861
* avoiding waste of resources of PL if not strictly necessary (for instance when I2C0 functionality is not required at all).

The configuration depicted by the following figure shows in principle a solution integrating the workaround suggested by Xilinx AR# 61861:
* PS I2C0 controller's signals are routed to PL via EMIO routing
* MIO46/47 are disabled 
* glitch filter is digitally implemented in PL
* I2C0 SDA and SCL lines are physically connected to PL at carrier board level.


[[File:Bora-i2c-glitch-filter.png|thumb|center|600px]]
[[File:BoraLite-i2c-glitch-filter.jpg|thumb|center|600px]]


(1) What here described refers to I2C0 controller that by default is routed on pins MIO46 and MIO47.

===== How to implement workaround suggested by Xilinx on BoraEVB=====

''Plase note that the reference project with I2C glitch filter implemented in FPGA is available on request. Plase contact [mailto:helpdesk@dave.eu helpdesk@dave.eu]''

This project, built with Vivado 2014.4, is based on the default project for BELK (BORA rev.B and BORAevb rev.A).

Here we have changed I2C0 signals routing to EMIO pins through FPGA, implementing the I2C glitch filter with VHDL example code provided in Xilinx AR# 61861.
The MIO46-MIO47 is then configured as input GPIO. This is accomplished from the FSBL generated within the provided project.

I2C interface is routed through FPGA to pins on BANK35:
* I2C SCL => IO_L9P_T1_DQS_AD3P_35
* I2C SDA => IO_L9N_T1_DQS_AD3N_35

The BANK35 MUST be powered at 1.8V

====== Test on BoraEVB ======
To test the solution, please make these connections on BORAevb rev.A:
* 1.8V supply for BANK35 : (J11.2 to J11.7)
* I2C SCL : JP10.14 to JP21.5
* I2C SDA : JP10.16 to JP21.3

====== Test on BoraXEVB ======
To test the solution, please make these connections on BoraXEVB:
* 1.8V supply for BANK35 : please refer to VDDIO_BANK35 possibility on BoraXEVB schematics
* populate RPACK RP87
* I2C SCL : JP30.9 to JP29.5
* I2C SDA : JP30.11 to JP29.3

====Programmable logic (PL)====
For Bora SOM please refer to the following links:
*[[BORA_SOM/BORA_Hardware/Peripherals/Programmable_logic_(FPGA)#Routing_information|bank 34]]
*[[BORA_SOM/BORA_Hardware/Peripherals/Programmable_logic_(FPGA)#Routing_information_2|bank 35]]
*[[BORA_SOM/BORA_Hardware/Peripherals/Programmable_logic_(FPGA)#Routing_information_3|bank 13]]

For BoraX SOM please refer to the [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Programmable_logic_(FPGA)|page]].

For BoraLite SOM please refer to the [[BORA_Lite_SOM/BORA_Lite_Hardware/Peripherals/Programmable_logic_(FPGA)|page]].

====Traces length matching====
A spreadsheet is available for download here, containing detailed information about signals routing. These information can be used to check nets matching of the overall system (carrier board + SOM).

For Bora/BoraEVB systems: [[File:Bora-routing.zip]].

For BoraX/BoraXEVB systems: [[File:BoraX-BoraXEVB-combined-routing.zip]].

For BoraLite/BoraXEVB systems: the presence of the Bora Lite adapter does not make sense to provide the routing information. Please refer to the [[BORA_Lite_SOM/BORA_Lite_Hardware/Peripherals/Programmable_logic_(FPGA)| Programmable logic page]] about information on internal BORA Lite routing. Please take carefully into account the design of the Carrier board considering every information related to the SO-DIMM socket and the tracenet on the Carrier
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