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Hardware Manual (Diva)

5,324 bytes added, 10:38, 20 January 2023
Hardware Manual in PDF format
== Standards ==
Dave SrL '''DAVE Embedded Systems''' is certified to ISO 9001 standards.
== Disclaimers ==
'''DAVE Embedded Systems''' does not assume any responsibility for availability, supply and support related to all products mentioned in this manual that are not strictly part of the Diva CPU module.Diva CPU Modules are not designed for use in life support appliances, devices, or systems where malfunctioning of these products can reasonably be expected to result in personal injury. Dave Srl '''DAVE Embedded Systems'''' customers who are using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Dave Srl '''DAVE Embedded Systems''' for any damage resulting from such improper use or sale.
== Warranty ==
Diva is guaranteed against defects in material and workmanship for the warranty period from the shipment date. During the warranty period, Dave SrL '''DAVE Embedded Systems''' will at its discretion decide to repair or replace defective products. Within the warranty period, the repair of products is free of charge provided that warranty conditions are observed.
The warranty does not apply to defects resulting from improper or inadequate maintenance or handling by the customer, unauthorized modification or misuse, operation outside of the product’s specifications or improper installation or maintenance.
Dave SrL '''DAVE Embedded Systems''' will not be responsible for any defects or damages to other products not supplied by Dave SrL '''DAVE Embedded Systems''' that are caused by a faulty Diva module.
== Technical Support ==
We are committed to making our products easy to use and will help customers use our CPU modules in their systems. Technical support is delivered through email for registered kits owners. Support requests can be sent to support-diva'''helpdesk@dave.eu'''. Software upgrades are available for download in the restricted download area of '''DAVE web siteEmbedded Systems''' git server: http://www<code>git@git.dave.eu</reserved-areacode> . An account is required to access this area. Please refer to our Web site at httphttps://www.dave.eu/dave-cpu-module-am335x-diva.html for the latest product documents, utilities, drivers, Product Change Notices, Board Support Packages, Application Notes, mechanical drawings and additional tools and software.
== Related Documents ==
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" align="center"|'''Document'''| align="center" style="background:#f0f0f0;" align="center"|'''Location'''
|-
| Dave '''DAVE Embedded Systems''' Developers' Wiki||http://wiki.dave.eu/index.php/Main_Page
|-
| <br>||
|-
|+ align="bottom" style="caption-side: bottom" align="bottom" | Table: related documents
|}
== Hardware Manual in PDF format ==
== '''N.B. The latest Hardware Manual in PDF format ==version is 1.0.6.'''
Please download the [http://wwwmirror.dave.eu/sitesManuals/default/files/filesDIVA/diva-hm.pdf Diva Hardware Manual in pdf format].
== Conventions, Abbreviations, Acronyms ==
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" align="center"|'''Abbreviation'''| align="center" style="background:#f0f0f0;" align="center"|'''Definition'''
|-
| BTN||Button
| GPO||General Purpose Output
|-
| DELKDIVELK||Diva Embedded Linux Kit
|-
| PCB||Printed Circuit Board
| <br>||
|-
|+ align="bottom" style="caption-side: bottom" align="bottom" | Table: Abbreviations and acronyms used in this manual
|}
= Introduction =
Diva is a family of system-on-modules (SOM) that belongs to [httphttps://www.dave.eu/files/roadmap.pdf '''DAVEEmbedded Systems'''s ''Lite'' Line product class].
[[File:Diva-400.png|400px]]
== Product Highlights ==
* ARM Cortex-A8 architecture @ 275300/500600/600800/720 1000 MHz
* Lite Line
** "No-frills" CPU module
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" align="center"|'''Feature'''| align="center" style="background:#f0f0f0;" align="center"|'''Specifications'''| align="center" style="background:#f0f0f0;" align="center"|'''Options'''
|-
| CPU||"Sitara" AM335x<br>ARMv7 architecture<br>Cortex A8 @ 275300/500600/600800/720 1000 ||
|-
| RAM||16-bit DDR3 @ 303 333 MHz<br>Up to 512 MB ||
|-
| Storage||Flash NOR SPI<br>Flash NAND on Local bus<br>I²C 32 kbit EEPROM||
|-
|+ align="bottom" style="caption-side: bottom" align="bottom" | Table: CPU and Memories
|}
 
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" align="center"|'''Feature'''| align="center" style="background:#f0f0f0;" align="center"|'''Specifications'''| align="center" style="background:#f0f0f0;" align="center"|'''Options'''
|-
| Graphics Controller||Up to 24-Bits Data Output<br>Resolution Up to 2048x2048 (With Maximum 126-MHz Pixel Clock)<br>TFT/RGB support ||
| Miscellaneous||Up to 8x 12-bit ADC channels||
|-
|+ align="bottom" style="caption-side: bottom" align="bottom" | Table: Peripherals
|}
 
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" align="center"|'''Feature'''| align="center" style="background:#f0f0f0;" align="center"|'''Specifications'''| align="center" style="background:#f0f0f0;" align="center"|'''Options'''
|-
| Supply Voltage||[3.6 - 5.5] V, voltage regulation on board||
| Connectors||204-pin SO-DIMM||
|-
|+ align="bottom" style="caption-side: bottom" align="bottom" | Table: Electrical, Mechanical and Environmental Specifications
|}
== RAM memory bank ==
Main RAM memory consists of 16-bit wide DDR3 SDRAM running at 303 333 MHz. Maximum size is 512 MByte.
== NOR flash bank ==
This chapter describes the mechanical characteristics of the Diva module.
Mechanical drawings are available in DXF format from the Diva page on Dave's ''DAVE Embedded Systems''' website: http://httphttps://www.dave.eu/dave-cpu-module-am335x-diva.html
== Board Layout ==
[[File:So-dimm.png|600px|frameless|border]]
 
== CAD Drawings ==
 
* 2D (DXF format): https://mirror.dave.eu/diva/mechanicals/diva.dxf.zip
* 3D (STEP format): https://mirror.dave.eu/diva/mechanicals/diva_stp.zip
= Power, reset and control =
# this step is composed of two events
#* main PSU enables several voltage rails to complete CPU, memories and peripheral power up sequence
#* VAUX33 signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board circuitry that interfaces CPU I/O directlyor vice versa)
# PORSTn_OUT signal is raised to indicate that all power rails of SOM are stable
(1) This step is not mandatory and VIN and CB_PWR_GOOD can be connected together. CB_PWR_GOOD is provided to prevent, if necessary, Diva's PSU to turn on during ramp of carrier board VIN rail. Depending on carrier board's PSU design, this may lead to undesired glitches.
=== PMIC ===
* PWRHOLD (input): This signal is connected to processor's PMIC_PWR_EN and is used to initiate power up sequence.
* PMIC_PWRON (input): A rising edge of this pin (automatically done at startup) the PMIC performs an OFF-to-ACTIVE state transition. On a falling edge of this pin, the PMIC performs an ACTIVE-to-OFF state transition. This signal is pulled-up to VIN through 10kOhm resistor.
===Power consumptiontree and voltage domains===Even though Diva is powered by one supply rail, several voltage domains exist according to circuitry and components' specifications. From the system integrator's perspective, it is crucial to know how interface signals are related to these domains in order to design the carrier board properly. The following image depicts Diva's simplified power tree and voltage domains organization.  [[File:DIVA-power-block-diagram.png|thumb|center|600px|Simplified power tree/voltage domains diagram]]
== Reset scheme and voltage monitoring ==
=== RTC_PWRONRSTn ===
RTC_PORZ
This signal is connected to processor's RTC_PWRONRSTn (aka RTC_PORZ) signal. It is an output-only signal pulled-down with a 100kOhm resistor. It only affects processor's RTC operations and registers.
=== JTAG_TRSTn ===
JTAG_TRSTn is the test and emulation logic reset input. It is pulled-down with 10kOhm resistor.
== Boot Options ==
AM335x processor provides several boot sequences selectable via BTMODE[15:0] bootstrap pins. In order to fully understand how boot works on Diva platform, please refer to chapter 26 ("Initialization") of the [httphttps://www.ti.com/litvlit/ug/spruh73p/spruh73p.pdf/spruh73g AM335x Technical Reference Manual].
SYSBOOT[15:0] terminals are respectively LCD_DATA[15:0] inputs, latched on the rising edge of PWRONRSTn. The booting device list is created based on the SYSBOOT pins. A booting device can be a memory booting device (soldered flash memory or temporarily booting device like memory card) or a peripheral interface connected to a host. The main loop of the booting procedure goes through the booting device list and tries to search for an image from the currently selected booting device. This loop is exited if a valid booting image is found and successfully executed or upon watchdog expiration. The memory booting procedure is executed when the booting device type is one of NOR, NAND, MMC or SPI-EEPROM. The peripheral booting is executed when the booting device type is Ethernet, USB or UART.
== Recovery ==
For different reason, starting from image corruption due power loss during upgrade or unrecoverable bug while developing a new U-Boot feature, the user will need, sooner or later, to recover (''bare-metal'' restore) the Diva SOM without using the bootloader itself. The following paragraphs introduce the available options. For further information, please refer to Dave '''DAVE Embedded Systems''' Developers Wiki or contact the Technical Support Team.
=== JTAG recovery ===
* Alarm capability
* Backup power from external battery
Backup power is provided through the PMIC_VBACKUP (J1.203) signal. If not used, PMIC_VBACKUP must be externally connected to GNDPMIC.VCC5 (VIN).
For a detailed description of RTC characteristics, please refer to the [http://www.ti.com/lit/ds/symlink/tps65910.pdf TPS65910A3 PMIC datasheet].
An external watchdog (MAX6373 device) is connected to the AM335X_GMII1_TXD2 (J1.159) signal. During normal operation, the microprocessor should repeatedly toggle the watchdog input WDI (AM335X_GMII1_TXD2) before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset the μP.
The MAX6373 watchdog timer is pin-selectable and the timer can be configured through the WD_SET0 (J1.7), WD_SET1 (J1.9) and WD_SET2 (J1.11) signals. As a default, the watchdog is configured through a pull-up/pull-down resistors network (WD_SET[02..20] = 110) that keeps the watchdog timer inactive at startup. Startup delay ends when WDI sees its first level transition. The default watchdog timeout period is 10 s.
The configuration can be changed by optional external circuitry implemented on the carrier board.
{| class="wikitable" |
|-
| align="left" style="background:#f0f0f0;" align="left"| '''Pin'''||Reference to the connector pin
|-
| align="left" style="background:#f0f0f0;" align="left"| '''Pin Name'''||Pin (signal) name on the Diva connectors
|-
| align="left" style="background:#f0f0f0;" align="left"| '''Internal ConnectionsConnection(s)'''||Connections to the Diva components:<br>
CPU.<x> : pin connected to CPU pad named <x><br>
KEY.<x>: pin connected to the key switch controller<br>
TSC.<x> : pin connected to the touchscreen<br>
controller<br>
EEPROM.<x> : pin connected to the EEPROM<br>
CAN.<x> : pin connected to the CAN transceiver<br>
PMIC.<x> : pin connected to the Power Manager IC<br>
LANETHPHY.<x> : pin connected to the LAN PHY<br>USB.<x> : pin connected to the USB transceiver<br>SV.<x>: pin connected to voltage supervisor<br>MTR: pin connected to voltage monitors<br>
|-
| align="left" style="background:#f0f0f0;" align="left"| '''Ball/Pin #'''||Component ball/pin number connected to signal
|-
| align="left" style="background:#f0f0f0;" align="left"| '''Supply GroupVoltage domain'''||Please refer to [[#Power Supply Grouptree and voltage domains|this section]]
|-
| align="left" style="background:#f0f0f0;" align="left"| '''Type'''||Pin type: I = Input, <br>O = Output, <br>D= Differential, <br>Z =High impedance,<br> S = Supply voltage, <br>G = Ground, <br>A= Analog signal
|-
| align="left" style="background:#f0f0f0;" align="left"| '''VoltagePull'''||IThis refers to discrete pull-up/down resistors (if any). Additional pull-up/O voltagedowns may be present if the signal is connected to any integrated circuit. In this case, please refer to the datasheet of the IC.
|-
|+ align="left" style="caption-side: bottom" align="left" | Table: Pinout information
|}
The Internal connection column reports the name of the microprocessor signal, which in turn contains references to all the peripheral functions that can be associated to with that pin. For example, the following pin name
<pre>
CPU.VOUT[1]_B_CB_C[4]GPMC_CSN1/GPMC_CLK/MMC1_CLK/PR1_EDIO_DATA_IN6/EMAC[1]_MRXD[0]PR1_EDIO_DATA_OUT6/VIN[1]A_D[1]PR1_PRU1_PRU_R30_12/UART4_RXDPR1_PRU1_PRU_R31_12/GP3[1GPIO1_30]
</pre>
means INDICATES that the pin can be used configured as:* VOUT[1]_B_CB_C[4]: Video output data, port 1, B/CB/C color bit 4GPMC_CSN1* GPMC_CLK*MMC1_CLK*PR1_EDIO_DATA_IN6* EMAC[1]_MRXD[0]: Ethernet MAC, port 1, [G]MII Receive Data,bit 0PR1_EDIO_DATA_OUT6* VIN[1]A_D[1]: Video input channel 1, port A data input bit 1PR1_PRU1_PRU_R30_12* UART[4]_RXD: UART port 4, receive data inputPR1_PRU1_PRU_R31_12* GP3[1]: General Purpose I/O port 3GPIO1_30.For more details, channel 1please refer to the muxing options described in the Reference Manual of the AM355x.
The following table reports all the function names that can be found on the Internal connection and the associated description.== Carrier board mating SO-DIMM connector - J1 pinout ==
{| class="wikitable" {{table}}| style="background:#f0f0f0;" align="center" |'''Pin'''| style="background:#f0f0f0;" align="center" |'''Pin name'''| style="background:#f0f0f0;" align="center" |'''Internal connection(s)'''| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''| style="background:#f0f0f0;" align="leftcenter" |'''[[#Power tree and voltage domains|Voltage domain]]'''| style="background:#f0f0f0;" align="center"|'''Function nameType'''| style="background:#f0f0f0;" align="leftcenter" |'''Pull <sup>(1)</sup>'''| style="background:#f0f0f0;" align="center"|'''DescriptionNotes'''
|-
| EMAC[x]1||DGND||||||||G|||Ethernet MAC. “x” represents the port number (0 or 1)
|-
| UART2||AM335X_GPMC_WPn||CPU.[xGPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MII1_TXEN/UART4_TXD/GPIO0_31]||UART port. “x” represents U17||VAUX2|IO|||Optionally, this pin can connected to the port number (0 to 5)WP NAND flash
|-
| GPx3||AM335X_I2C0_SCL||CPU.[yI2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6]||General Purpose I/O port. “x” represents C16||VAUX2|IO||10kΩ ↑|Internally connected to the port number (0 to 3)PMIC and EEPROM
|-
| SPI4||AM335X_GPMC_CS0n||CPU.[xGPMC_CSN0///////GPIO1_29]||SPI channel. “x” represents V6||VAUX2|IO||10kΩ ↑|Internally connected to the channel number NAND flash (0 to 3if present)
|-
| DCAN5||AM335X_I2C0_SDA||CPU.[xI2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5]||Controller Area Network module. “x” represents C17||VAUX2|IO||10kΩ ↑|Internally connected to the module number (0 to 1)PMIC and EEPROM
|-
| SD6||AM335X_GPMC_CS1n||CPU.[xGPMC_CSN1/GPMC_CLK/MMC1_CLK/PR1_EDIO_DATA_IN6/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30]||MMC/SD/SDIO interfaces. “x” represents the interface number (0 to 2)U9||VAUX2|IO||||
|-
| MCA[x]7||Multi-Channel Audio Serial Port (McASP)WD_SET0||||||3. “x” represents the port number (0 to 5)3V||I||10kΩ ↓|Optionally, this pin can be pullup
|-
| I2C8||AM335X_GPMC_CS2n||CPU.[xGPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31]||I2C channel. “x” represents the channel number (0 to 3)V9||VAUX2||IO||||
|-
|+ align="bottom" style="caption-side: bottom" 9| Table: Function names|}  == Carrier board mating SO-DIMM connector - J1 pinout == {WD_SET1| class="wikitable" {{table}}| align="center" style="background:#f0f0f0;"|'''Pin'''| align="center" style="background:#f0f0f0;"|'''Pin name'''| align="center" style="background:#f0f0f0;"3.3V|'''Internal connection(s)'''| align="center" style="background:#f0f0f0;"I|'''Ball/pin #'''| align="center" style="background:#f0f0f0;"10kΩ ↑|'''Supply group'''| align="center" style="background:#f0f0f0;"|'''Type'''| align="center" style="background:#f0f0f0;"|'''Voltage'''| align="center" style="background:#f0f0f0;"|'''Notes'''Optionally, this pin can be pulldown
|-
| 110||DGNDAM335X_GPMC_CS3n||CPU.[GPMC_CSN3///MMC2_CMD/PR1_MII0_CRS/PR1_MDIO_DATA/EMU4/GPIO2_0]||T13||VAUX2||IO||||
|-
| 211||AM335X_GPMC_WPnWD_SET2||CPU.[GPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MII1_TXEN/UART4_TXD/GPIO0_31]||U17||3.3V||I||10kΩ ↑||Optionally, this pin can be pulldown
|-
| 312||AM335X_I2C0_SCLDGND||CPU.[I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6]||C16|||||G|||
|-
| 413||AM335X_GPMC_CS0nEEPROM_WP||CPU.[GPMC_CSN0///////GPIO1_29]||V6||3.3V||I||10kΩ ↓||Optionally, this pin can be pullup
|-
| 514||AM335X_I2C0_SDAAM335X_GPMC_CLK||CPU.[I2C0_SDAGPMC_CLK/TIMER4LCD_MEMORY_CLK/UART2_CTSNGPMC_WAIT1/ECAP2_IN_PWM2_OUTMMC2_CLK/PR1_MII1_CRS/PR1_MDIO_MDCLK/MCASP0_FSR/GPIO3_5GPIO2_1]||C17V12||VAUX2||IO||||
|-
| 615||AM335X_GPMC_CS1nEEPROM_A1||CPU.[GPMC_CSN1/GPMC_CLK/MMC1_CLK/PR1_EDIO_DATA_IN6/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30]||U9||3.3V||I||10kΩ ↓||Optionally, this pin can be pullup
|-
| 716||WD_SET0AM335X_GPMC_WEn||CPU.[GPMC_WEN//TIMER6/////GPIO2_4]||U6||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 817||AM335X_GPMC_CS2nEEPROM_A0||CPU.[GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31]||V9||3.3V||I||10kΩ ↓||Optionally, this pin can be pullup
|-
| 918||WD_SET1AM335X_GPMC_OEn_REn||CPU.[GPMC_OEN_REN//TIMER6/////GPIO2_4]||T7||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 1019||AM335X_GPMC_CS3nAM335X_EXT_WAKEUP||CPU.[GPMC_CSN3///MMC2_CMD/PR1_MII0_CRS/PR1_MDIO_DATA/EMU4/GPIO2_0]EXT_WAKEUP||T13C5||VRTC||||||
|-
| 1120||WD_SET2AM335X_GPMC_ADVn_ALE||CPU.[GPMC_ADVN_ALE//TIMER4/////GPIO2_2]||R7||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 1221||DGND|||||||||G|||
|-
| 1322||EEPROM_WPAM335X_GPMC_BE0n_CLE||CPU.[GPMC_BE0N_CLE//TIMER5/////GPIO2_5]||T6||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 1423||AM335X_GPMC_CLKAM335X_RMII1_REFCLK||CPU.[GPMC_CLK/LCD_MEMORY_CLK/GPMC_WAIT1/MMC2_CLK/PR1_MII1_CRS/PR1_MDIO_MDCLK/MCASP0_FSR/GPIO2_1]||V12H18||VAUX2||IO||||HW option (not connected by default)
|-
| 1524||EEPROM_A1AM335X_GPMC_BE1n||CPU.[GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28]||U18||VAUX2||IO||||
|-
| 1625||AM335X_GPMC_WEnAM335X_UART0_TXD||CPU.[GPMC_WENUART0_TXD/SPI1_CS1/TIMER6DCAN0_RX/I2C2_SCL/ECAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/PR1_PRU1_PRU_R31_15/GPIO2_4GPIO1_11]||U6E16||VAUX2||IO||||
|-
| 1726||EEPROM_A0AM335X_GPMC_WAIT||CPU.[GPMC_WAIT0/GMII2_CRS/GPMC_CSN4/RMII2_CRS_DV/MMC1_SDCD/PR1_MII1_COL/UART4_RXD/GPIO0_30]||T17||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 1827||AM335X_GPMC_OEn_REnAM335X_UART0_RXD||CPU.[GPMC_OEN_RENUART0_RXD/SPI1_CS0/TIMER6DCAN0_TX/I2C2_SDA/ECAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/PR1_PRU1_PRU_R31_14/GPIO2_4GPIO1_10]||T7E15||VAUX2||IO||||
|-
| 1928||AM335X_EXT_WAKEUPAM335X_GPMC_A0||CPU.EXT_WAKEUP[GPMC_A0/GMII2_TXEN/RGMII2_TCTL/RMII2_TXEN/GPMC_A16/PR1_MII_MT1_CLK/EHRPWM1_TRIPZONE_INPUT/GPIO1_16]||C5R13||VAUX2||IO||||
|-
| 2029||AM335X_GPMC_ADVn_ALEAM335X_UART0_RTSn||CPU.[GPMC_ADVN_ALEUART0_RTSN/UART4_TXD/TIMER4DCAN1_RX/I2C1_SCL/SPI1_D1/SPI1_CS0/PR1_EDC_SYNC1_OUT/GPIO2_2GPIO1_9]||R7E17||VAUX2||IO||||HW option: connected to PMIC_SLEEP
|-
| 2130||DGNDAM335X_GPMC_A1||CPU.[GPMC_A1/GMII2_RXDV/RGMII2_RCTL/MMC2_DAT0/GPMC_A17/PR1_MII1_TXD3/EHRPWM0_SYNCO/GPIO1_17]||V14||VAUX2||IO||||
|-
| 2231||AM335X_GPMC_BE0n_CLEAM335X_UART0_CTSn||CPU.[GPMC_BE0N_CLEUART0_CTSN/UART4_RXD/TIMER5DCAN1_TX/I2C1_SDA/SPI1_D0/TIMER7/PR1_EDC_SYNC0_OUT/GPIO2_5GPIO1_8]||T6E18||VAUX2||IO||||HW option: connected to PMIC_INT1
|-
| 2332||AM335X_RMII1_REFCLKDGND||||H18|||||G|||
|-
| 2433||AM335X_GPMC_BE1nAM335X_UART1_TXD||CPU.[GPMC_BE1NUART1_TXD/GMII2_COLMMC2_SDWP/GPMC_CSN6DCAN1_RX/MMC2_DAT3I2C1_SCL/GPMC_DIR/PR1_MII1_RXLINKPR1_UART0_TXD/MCASP0_ACLKRPR1_PRU0_PRU_R31_16/GPIO1_28GPIO0_15]||U18D15||VAUX2||IO||||
|-
| 2534||AM335X_UART0_TXDAM335X_GPMC_A2||CPU.[UART0_TXDGPMC_A2/SPI1_CS1GMII2_TXD3/DCAN0_RXRGMII2_TD3/I2C2_SCLMMC2_DAT1/ECAP1_IN_PWM1_OUTGPMC_A18/PR1_PRU1_PRU_R30_15PR1_MII1_TXD2/PR1_PRU1_PRU_R31_15EHRPWM1A/GPIO1_11GPIO1_18]||E16U14||VAUX2||IO||||
|-
| 2635||AM335X_GPMC_WAITAM335X_UART1_RXD||CPU.[GPMC_WAIT0UART1_RXD/GMII2_CRSMMC1_SDWP/GPMC_CSN4DCAN1_TX/RMII2_CRS_DVI2C1_SDA/MMC1_SDCD/PR1_MII1_COLPR1_UART0_RXD/UART4_RXDPR1_PRU1_PRU_R31_16/GPIO0_30GPIO0_14]||T17D16||VAUX2||IO||||
|-
| 2736||AM335X_UART0_RXDAM335X_GPMC_A3||CPU.[UART0_RXDGPMC_A3/SPI1_CS0GMII2_TXD2/DCAN0_TXRGMII2_TD2/I2C2_SDAMMC2_DAT2/ECAP2_IN_PWM2_OUTGPMC_A19/PR1_PRU1_PRU_R30_14PR1_MII1_TXD1/PR1_PRU1_PRU_R31_14EHRPWM1B/GPIO1_10GPIO1_19]||E15T14||VAUX2||IO||||
|-
| 2837||AM335X_GPMC_A0AM335X_UART1_RTSn||CPU.[GPMC_A0UART1_RTSN/GMII2_TXENTIMER5/RGMII2_TCTLDCAN0_RX/RMII2_TXENI2C2_SCL/GPMC_A16SPI1_CS1/PR1_MII_MT1_CLKPR1_UART0_RTS_N/EHRPWM1_TRIPZONE_INPUTPR1_EDC_LATCH1_IN/GPIO1_16GPIO0_13]||R13D17||VAUX2||IO||||
|-
| 2938||AM335X_UART0_RTSnAM335X_GPMC_A4||CPU.[UART0_RTSNGPMC_A4/UART4_TXDGMII2_TXD1/DCAN1_RXRGMII2_TD1/I2C1_SCLRMII2_TXD1/SPI1_D1GPMC_A20/SPI1_CS0PR1_MII1_TXD0/PR1_EDC_SYNC1_OUTEQEP1A_IN/GPIO1_9GPIO1_20]||E17R14||VAUX2||IO||||
|-
| 3039||AM335X_GPMC_A1AM335X_UART1_CTSn||CPU.[GPMC_A1UART1_CTSN/GMII2_RXDVTIMER6/RGMII2_RCTLDCAN0_TX/MMC2_DAT0I2C2_SDA/GPMC_A17SPI1_CS0/PR1_MII1_TXD3PR1_UART0_CTS_N/EHRPWM0_SYNCOPR1_EDC_LATCH0_IN/GPIO1_17GPIO0_12]||V14D18||VAUX2||IO||||
|-
| 3140||AM335X_UART0_CTSnAM335X_GPMC_A5||CPU.[UART0_CTSNGPMC_A5/UART4_RXDGMII2_TXD0/DCAN1_TXRGMII2_TD0/I2C1_SDARMII2_TXD0/SPI1_D0GPMC_A21/TIMER7PR1_MII1_RXD3/PR1_EDC_SYNC0_OUTEQEP1B_IN/GPIO1_8GPIO1_21]||E18V15||VAUX2||IO||||
|-
| 3241||DGND|||||||||G|||
|-
| 3342||AM335X_UART1_TXDAM335X_GPMC_A6||CPU.[UART1_TXDGPMC_A6/MMC2_SDWPGMII2_TXCLK/DCAN1_RXRGMII2_TCLK/I2C1_SCLMMC2_DAT4/GPMC_A22/PR1_UART0_TXDPR1_MII1_RXD2/PR1_PRU0_PRU_R31_16EQEP1_INDEX/GPIO0_15GPIO1_22]||D15U15||VAUX2||IO||||
|-
| 3443||AM335X_GPMC_A2AM335X_SPI0_SCLK||CPU.[GPMC_A2SPI0_SCLK/GMII2_TXD3UART2_RXD/RGMII2_TD3I2C2_SDA/MMC2_DAT1EHRPWM0A/GPMC_A18PR1_UART0_CTS_N/PR1_MII1_TXD2PR1_EDIO_SOF/EHRPWM1AEMU2/GPIO1_18GPIO0_2]||U14A17||VAUX2||IO||||Internally connected to the NOR flash (if present)
|-
| 3544||AM335X_UART1_RXDAM335X_GPMC_A7||CPU.[UART1_RXDGPMC_A7/MMC1_SDWPGMII2_RXCLK/DCAN1_TXRGMII2_RCLK/I2C1_SDAMMC2_DAT5/GPMC_A23/PR1_UART0_RXDPR1_MII1_RXD1/PR1_PRU1_PRU_R31_16EQEP1_STROBE/GPIO0_14GPIO1_23]||D16T15||VAUX2||IO||||
|-
| 3645||AM335X_GPMC_A3AM335X_SPI0_D0||CPU.[GPMC_A3SPI0_D0/GMII2_TXD2UART2_TXD/RGMII2_TD2I2C2_SCL/MMC2_DAT2EHRPWM0B/GPMC_A19PR1_UART0_RTS_N/PR1_MII1_TXD1PR1_EDIO_LATCH_IN/EHRPWM1BEMU3/GPIO1_19GPIO0_3]||T14B17||VAUX2||IO||||Internally connected to the NOR flash (if present)
|-
| 3746||AM335X_UART1_RTSnAM335X_GPMC_A8||CPU.[UART1_RTSNGPMC_A8/TIMER5GMII2_RXD3/DCAN0_RXRGMII2_RD3/I2C2_SCLMMC2_DAT6/SPI1_CS1GPMC_A24/PR1_UART0_RTS_NPR1_MII1_RXD0/PR1_EDC_LATCH1_INMCASP0_ACLKX/GPIO0_13GPIO1_24]||D17V16||VAUX2||IO||||
|-
| 3847||AM335X_GPMC_A4AM335X_SPI0_D1||CPU.[GPMC_A4SPI0_D1/GMII2_TXD1MMC1_SDWP/RGMII2_TD1I2C1_SDA/RMII2_TXD1EHRPWM0_TRIPZONE_INPUT/GPMC_A20PR1_UART0_RXD/PR1_MII1_TXD0PR1_EDIO_DATA_IN0/EQEP1A_INPR1_EDIO_DATA_OUT0/GPIO1_20GPIO0_4]||R14B16||VAUX2||IO||||Internally connected to the NOR flash (if present)
|-
| 3948||AM335X_UART1_CTSnAM335X_GPMC_A9||CPU.[UART1_CTSNGPMC_A9/TIMER6GMII2_RXD2/DCAN0_TXRGMII2_RD2/I2C2_SDAMMC2_DAT7/SPI1_CS0GPMC_A25/PR1_UART0_CTS_NPR1_MII_MR1_CLK/PR1_EDC_LATCH0_INMCASP0_FSX/GPIO0_12GPIO1_25]||D18U16||VAUX2||IO||||
|-
| 4049||AM335X_GPMC_A5AM335X_SPI0_CS0||CPU.[GPMC_A5SPI0_CS0/GMII2_TXD0MMC2_SDWP/RGMII2_TD0I2C1_SCL/RMII2_TXD0EHRPWM0_SYNCI/GPMC_A21PR1_UART0_TXD/PR1_MII1_RXD3PR1_EDIO_DATA_IN1/EQEP1B_INPR1_EDIO_DATA_OUT1/GPIO1_21GPIO0_5]||V15A16||VAUX2||IO||||Internally connected to the NOR flash (if present)
|-
| 4150||DGNDAM335X_GPMC_A10||CPU.[GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_RXDV/MCASP0_AXR0/GPIO1_26]||T16||VAUX2||IO||||
|-
| 4251||AM335X_GPMC_A6AM335X_SPI0_CS1||CPU.[GPMC_A6SPI0_CS1/GMII2_TXCLKUART3_RXD/RGMII2_TCLKECAP1_IN_PWM1_OUT/MMC2_DAT4MMC0_POW/GPMC_A22XDMA_EVENT_INTR2/PR1_MII1_RXD2MMC0_SDCD/EQEP1_INDEXEMU4/GPIO1_22GPIO0_6]||U15C15||VAUX2||IO||||Optionally, this pin can connected to the RFU NOR flash
|-
| 4352||AM335X_SPI0_SCLKDGND||CPU.[SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2]||A17|||||G|||
|-
| 4453||AM335X_GPMC_A7USB0_CE||CPU.[GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/EQEP1_STROBE/GPIO1_23]USB0_CE||T15M15||VAUX33/VAUX1||A||||
|-
| 4554||AM335X_SPI0_D0AM335X_GPMC_A11||CPU.[SPI0_D0GPMC_A11/UART2_TXDGMII2_RXD0/I2C2_SCLRGMII2_RD0/EHRPWM0BRMII2_RXD0/PR1_UART0_RTS_NGPMC_A27/PR1_EDIO_LATCH_INPR1_MII1_RXER/EMU3MCASP0_AXR1/GPIO0_3GPIO1_27]||B17V17||VAUX2||IO||||
|-
| 4655||AM335X_GPMC_A8USB0_ID||CPU.[GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24]USB0_ID||V16P16||VAUX33/VAUX1||A||||
|-
| 4756||AM335X_SPI0_D1AM335X_GPMC_AD0||CPU.[SPI0_D1GPMC_AD0/MMC1_SDWPMMC1_DAT0/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4GPIO1_0]||B16U7||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 4857||AM335X_GPMC_A9USB0_DP||CPU.[GPMC_A9/GMII2_RXD2/RGMII2_RD2/MMC2_DAT7/GPMC_A25/PR1_MII_MR1_CLK/MCASP0_FSX/GPIO1_25]USB0_DP||U16N17||VAUX33/VAUX1||D||||
|-
| 4958||AM335X_SPI0_CS0AM335X_GPMC_AD1||CPU.[SPI0_CS0GPMC_AD1/MMC2_SDWPMMC1_DAT1/I2C1_SCL/EHRPWM0_SYNCI/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5GPIO1_1]||A16V7||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 5059||AM335X_GPMC_A10USB0_DM||CPU.[GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_RXDV/MCASP0_AXR0/GPIO1_26]USB0_DM||T16N18||VAUX33/VAUX1||D||||
|-
| 5160||AM335X_SPI0_CS1AM335X_GPMC_AD2||CPU.[SPI0_CS1GPMC_AD2/UART3_RXDMMC1_DAT2/ECAP1_IN_PWM1_OUT/MMC0_POW/XDMA_EVENT_INTR2/MMC0_SDCD/EMU4/GPIO0_6GPIO1_2]||C15R8||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 5261||DGND|||||||||G|||
|-
| 5362||USB0_CEAM335X_GPMC_AD3||CPU.USB0_CE[GPMC_AD3/MMC1_DAT3//////GPIO1_3]||M15T8||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 5463||AM335X_GPMC_A11USB0_DRVVBUS||CPU.[GPMC_A11/GMII2_RXD0/RGMII2_RD0/RMII2_RXD0/GPMC_A27/PR1_MII1_RXER/MCASP0_AXR1/GPIO1_27]USB0_DRVVBUS||V17F16||VAUX2||O||||
|-
| 5564||USB0_IDAM335X_GPMC_AD4||CPU.USB0_ID[GPMC_AD4/MMC1_DAT4//////GPIO1_4]||P16U8||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 5665||AM335X_GPMC_AD0VUSB_VBUS0||CPU.[GPMC_AD0/MMC1_DAT0//////GPIO1_0]USB0_VBUS||U7P15||VAUX33/VAUX1||A||||
|-
| 5766||USB0_DPAM335X_GPMC_AD5||CPU.USB0_DP[GPMC_AD5/MMC1_DAT5//////GPIO1_5]||N17V8||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 5867||AM335X_GPMC_AD1AM335x_EXTINTn||CPU.[GPMC_AD1/MMC1_DAT1//////GPIO1_1]NMIn||V7B18||VAUX2||I||||
|-
| 5968||USB0_DMAM335X_GPMC_AD6||CPU.USB0_DM[GPMC_AD6/MMC1_DAT6//////GPIO1_6]||N18R9||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 6069||AM335X_GPMC_AD2AM335X_XDMA_EVENT_INTR0||CPU.[GPMC_AD2XDMA_EVENT_INTR0/MMC1_DAT2/TIMER4/CLKOUT1/SPI1_CS1/PR1_PRU1_PRU_R31_16/EMU2/GPIO1_2GPIO0_19]||R8A15||VAUX2||IO||||
|-
| 6170||DGNDAM335X_GPMC_AD7||CPU.[GPMC_AD7/MMC1_DAT7//////GPIO1_7]||T9||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 6271||AM335X_GPMC_AD3AM335X_XDMA_EVENT_INTR1||CPU.[GPMC_AD3XDMA_EVENT_INTR1/MMC1_DAT3/TCLKIN/CLKOUT2/TIMER7/PR1_PRU0_PRU_R31_16/EMU3/GPIO1_3GPIO0_20]||T8D14||VAUX2||IO||||
|-
| 6372||USB0_DRVVBUSDGND||CPU.USB0_DRVVBUS||F16|||||G|||
|-
| 6473||AM335X_GPMC_AD4USB1_CE||CPU.[GPMC_AD4/MMC1_DAT4//////GPIO1_4]USB1_CE||U8P18||VAUX33/VAUX1||A||||
|-
| 6574||VUSB_VBUS0AM335X_GPMC_AD8||CPU.USB0_VBUS[GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22]||P15U10||VAUX2||IO||||
|-
| 6675||AM335X_GPMC_AD5USB1_ID||CPU.[GPMC_AD5/MMC1_DAT5//////GPIO1_5]USB1_ID||V8P17||VAUX33/VAUX1||A||||
|-
| 6776||AM335x_EXTINTnAM335X_GPMC_AD9||CPU.NMIn[GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_COL//GPIO0_23]||B18T10||VAUX2||IO||||
|-
| 6877||AM335X_GPMC_AD6USB1_DP||CPU.[GPMC_AD6/MMC1_DAT6//////GPIO1_6]USB1_DP||R9R17||VAUX33/VAUX1||D||||
|-
| 6978||AM335X_XDMA_EVENT_INTR0AM335X_GPMC_AD10||CPU.[XDMA_EVENT_INTR0GPMC_AD10/LCD_DATA21/TIMER4MMC1_DAT2/CLKOUT1MMC2_DAT6/SPI1_CS1EHRPWM2_TRIPZONE_INPUT/PR1_PRU1_PRU_R31_16PR1_MII0_TXEN/EMU2/GPIO0_19GPIO0_26]||A15T11||VAUX2||IO||||
|-
| 7079||AM335X_GPMC_AD7USB1_DM||CPU.[GPMC_AD7/MMC1_DAT7//////GPIO1_7]USB1_DM||T9R18||VAUX33/VAUX1||D||||
|-
| 7180||AM335X_XDMA_EVENT_INTR1AM335X_GPMC_AD11||CPU.[XDMA_EVENT_INTR1GPMC_AD11/LCD_DATA20/TCLKINMMC1_DAT3/CLKOUT2MMC2_DAT7/TIMER7EHRPWM2_SYNCO/PR1_PRU0_PRU_R31_16PR1_MII0_TXD3/EMU3/GPIO0_20GPIO0_27]||D14U12||VAUX2||IO||||
|-
| 7281||DGND|||||||||G|||
|-
| 7382||USB1_CEAM335X_GPMC_AD12||CPU.USB1_CE[GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12]||P18T12||VAUX2||IO||||
|-
| 7483||AM335X_GPMC_AD8USB1_DRVVBUS||CPU.[GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22]USB1_DRVVBUS||U10F15||VAUX2||O||||
|-
| 7584||USB1_IDAM335X_GPMC_AD13||CPU.USB1_ID[GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13]||P17R12||VAUX2||IO||||
|-
| 7685||AM335X_GPMC_AD9VUSB_VBUS1||CPU.[GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_COL//GPIO0_23]USB1_VBUS||T10T18||VAUX33/VAUX1||A||||
|-
| 7786||USB1_DPAM335X_GPMC_AD14||CPU.USB1_DP[GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14]||R17V13||VAUX2||IO||||
|-
| 7887||AM335X_GPMC_AD10AM335X_AIN0||CPU.[GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26]AIN0||T11|B6||VPLL|A||||
|-
| 7988||USB1_DMAM335X_GPMC_AD15||CPU.USB1_DM[GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15]||R18U13||VAUX2||IO||||
|-
| 8089||AM335X_GPMC_AD11AM335X_AIN1||CPU.[GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCO/PR1_MII0_TXD3//GPIO0_27]AIN1||U12|C7||VPLL|A||||
|-
| 8190||DGNDAM335X_LCD_PCLK||CPU.[LCD_PCLK/GPMC_A10/PR1_MII0_CRS/PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24]||V5||VAUX2||IO||||
|-
| 8291||AM335X_GPMC_AD12AM335X_AIN2||CPU.[GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12]AIN2||T12|B7||VPLL|A||||
|-
| 8392||USB1_DRVVBUSDGND||CPU.USB1_DRVVBUS||F15|||||G|||
|-
| 8493||AM335X_GPMC_AD13AGND_TSC||CPU.[GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13]||R12|||||G|||
|-
| 8594||VUSB_VBUS1AM335X_LCD_VSYNC||CPU.USB1_VBUS[LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22]||T18U5||VAUX2||IO||||
|-
| 8695||AM335X_GPMC_AD14AM335X_AIN3||CPU.[GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14]AIN3||V13|A7||VPLL|A||||
|-
| 8796||AM335X_AIN0AM335X_LCD_HSYNC||CPU.AIN0[LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23]||B6R5||VAUX2||IO||||
|-
| 8897||AM335X_GPMC_AD15AM335X_AIN4||CPU.[GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15]AIN4||U13|C8||VPLL|A||||
|-
| 8998||AM335X_AIN1AM335X_LCD_AC_BIAS_EN||CPU.AIN1[LCD_AC_BIAS_EN/GPMC_A11/PR1_MII1_CRS/PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25]||C7R6||VAUX2||IO||||
|-
| 9099||AM335X_LCD_PCLKAM335X_AIN5||CPU.[LCD_PCLK/GPMC_A10/PR1_MII0_CRS/PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24]AIN5||V5|B8||VPLL|A||||
|-
| 91100||AM335X_AIN2AM335X_LCD_DATA0||CPU.AIN2[LCD_DATA0/GPMC_A0/PR1_MII_MT0_CLK/EHRPWM2A//PR1_PRU1_PRU_R30_0/PR1_PRU1_PRU_R31_0/GPIO2_6]||B7R1||VAUX2||IO||||
|-
| 92101||DGNDAGND_TSC||||||||G||||
|-
| 93102||AGND_TSCAM335X_LCD_DATA1||CPU.[LCD_DATA1/GPMC_A1/PR1_MII0_TXEN/EHRPWM2B//PR1_PRU1_PRU_R30_1/PR1_PRU1_PRU_R31_1/GPIO2_7]||R2||VAUX2||IO||||
|-
| 94103||AM335X_LCD_VSYNCAM335X_AIN6||CPU.[LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22]AIN6||U5|A8||VPLL|A||||
|-
| 95104||AM335X_AIN3AM335X_LCD_DATA2||CPU.AIN3[LCD_DATA2/GPMC_A2/PR1_MII0_TXD3/EHRPWM2_TRIPZONE_INPUT//PR1_PRU1_PRU_R30_2/PR1_PRU1_PRU_R31_2/GPIO2_8]||A7R3||VAUX2||IO||||
|-
| 96105||AM335X_LCD_HSYNCAM335X_AIN7||CPU.[LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23]AIN7||R5|C9||VPLL|A||||
|-
| 97106||AM335X_AIN4AM335X_LCD_DATA3||CPU.AIN4[LCD_DATA3/GPMC_A3/PR1_MII0_TXD2/EHRPWM2_SYNCI_O//PR1_PRU1_PRU_R30_3/PR1_PRU1_PRU_R31_3/GPIO2_9]||C8R4||VAUX2||IO||||
|-
| 98107||AM335X_LCD_AC_BIAS_ENAGND_TSC||CPU.[LCD_AC_BIAS_EN/GPMC_A11/PR1_MII1_CRS/PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25]||R6||||G||||
|-
| 99108||AM335X_AIN5AM335X_LCD_DATA4||CPU.AIN5[LCD_DATA4/GPMC_A4/PR1_MII0_TXD1/EQEP2A_IN//PR1_PRU1_PRU_R30_4/PR1_PRU1_PRU_R31_4/GPIO2_10]||B8T1||VAUX2||IO||||
|-
| 100109||AM335X_LCD_DATA0AM335X_ECAP0_IN_PWM0_OUT||CPU.[LCD_DATA0ECAP0_IN_PWM0_OUT/GPMC_A0UART3_TXD/PR1_MII_MT0_CLKSPI1_CS1/EHRPWM2APR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/PR1_PRU1_PRU_R30_0MMC0_SDWP/PR1_PRU1_PRU_R31_0XDMA_EVENT_INTR2/GPIO2_6GPIO0_7]||R1C18||VAUX2||IO||||HW option: connected to Oscillator EN
|-
| 101110||AGND_TSCAM335X_LCD_DATA5||CPU.[LCD_DATA5/GPMC_A5/PR1_MII0_TXD0/EQEP2B_IN//PR1_PRU1_PRU_R30_5/PR1_PRU1_PRU_R31_5/GPIO2_11]||T2||VAUX2||IO||||
|-
| 102111||AM335X_LCD_DATA1AM335X_MMC_D3||CPU.[LCD_DATA1MMC0_DAT3/GPMC_A1GPMC_A20/PR1_MII0_TXENUART4_CTSN/EHRPWM2BTIMER5/UART1_DCDN/PR1_PRU1_PRU_R30_1PR1_PRU0_PRU_R30_8/PR1_PRU1_PRU_R31_1PR1_PRU0_PRU_R31_8/GPIO2_7GPIO2_26]||R2F17||VMMC||IO||||
|-
| 103112||AM335X_AIN6DGND||CPU.AIN6||A8|||||G|||
|-
| 104113||AM335X_LCD_DATA2AM335X_MMC_D2||CPU.[LCD_DATA2MMC0_DAT2/GPMC_A2GPMC_A21/PR1_MII0_TXD3UART4_RTSN/EHRPWM2_TRIPZONE_INPUTTIMER6/UART1_DSRN/PR1_PRU1_PRU_R30_2PR1_PRU0_PRU_R30_9/PR1_PRU1_PRU_R31_2PR1_PRU0_PRU_R31_9/GPIO2_8GPIO2_27]||R3F18||VMMC||IO||||
|-
| 105114||AM335X_AIN7AM335X_LCD_DATA6||CPU.AIN7[LCD_DATA6/GPMC_A6/PR1_EDIO_DATA_IN6/EQEP2_INDEX/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_6/PR1_PRU1_PRU_R31_6/GPIO2_12]||C9T3||VAUX2||IO||||
|-
| 106115||AM335X_LCD_DATA3AM335X_MMC_D1||CPU.[LCD_DATA3MMC0_DAT1/GPMC_A3GPMC_A22/PR1_MII0_TXD2UART5_CTSN/EHRPWM2_SYNCI_OUART3_RXD/UART1_DTRN/PR1_PRU1_PRU_R30_3PR1_PRU0_PRU_R30_10/PR1_PRU1_PRU_R31_3PR1_PRU0_PRU_R31_10/GPIO2_9GPIO2_28]||R4G15||VMMC||IO||||
|-
| 107116||AGND_TSCAM335X_LCD_DATA7||CPU.[LCD_DATA7/GPMC_A7/PR1_EDIO_DATA_IN7/EQEP2_STROBE/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_7/PR1_PRU1_PRU_R31_7/GPIO2_13]||T4||VAUX2||IO||||
|-
| 108117||AM335X_LCD_DATA4AM335X_MMC_D0||CPU.[LCD_DATA4MMC0_DAT0/GPMC_A4GPMC_A23/PR1_MII0_TXD1UART5_RTSN/EQEP2A_INUART3_TXD/UART1_RIN/PR1_PRU1_PRU_R30_4PR1_PRU0_PRU_R30_11/PR1_PRU1_PRU_R31_4PR1_PRU0_PRU_R31_11/GPIO2_10GPIO2_29]||T1G16||VMMC||IO||||
|-
| 109118||AM335X_ECAP0_IN_PWM0_OUTAM335X_LCD_DATA8||CPU.[ECAP0_IN_PWM0_OUTLCD_DATA8/UART3_TXDGPMC_A12/SPI1_CS1EHRPWM1_TRIPZONE_INPUT/PR1_ECAP0_ECAP_CAPIN_APWM_OMCASP0_ACLKX/SPI1_SCLKUART5_TXD/MMC0_SDWPPR1_MII0_RXD3/XDMA_EVENT_INTR2UART2_CTSN/GPIO0_7GPIO2_14]||C18U1||VAUX2||IO||||
|-
| 110119||AM335X_LCD_DATA5AM335X_MMC_CMD||CPU.[LCD_DATA5MMC0_CMD/GPMC_A5GPMC_A25/PR1_MII0_TXD0UART3_RTSN/EQEP2B_INUART2_TXD/DCAN1_RX/PR1_PRU1_PRU_R30_5PR1_PRU0_PRU_R30_13/PR1_PRU1_PRU_R31_5PR1_PRU0_PRU_R31_13/GPIO2_11GPIO2_31]||T2G18||VMMC||IO||||
|-
| 111120||AM335X_MMC_D3AM335X_LCD_DATA9||CPU.[MMC0_DAT3LCD_DATA9/GPMC_A20GPMC_A13/UART4_CTSNEHRPWM1_SYNCO/TIMER5MCASP0_FSX/UART1_DCDNUART5_RXD/PR1_PRU0_PRU_R30_8PR1_MII0_RXD2/PR1_PRU0_PRU_R31_8UART2_RTSN/GPIO2_26GPIO2_15]||F17U2||VAUX2||IO||||
|-
| 112121||DGND|||||||||G|||
|-
| 113122||AM335X_MMC_D2AM335X_LCD_DATA10||CPU.[MMC0_DAT2LCD_DATA10/GPMC_A21GPMC_A14/UART4_RTSNEHRPWM1A/TIMER6MCASP0_AXR0/UART1_DSRN/PR1_PRU0_PRU_R30_9PR1_MII0_RXD1/PR1_PRU0_PRU_R31_9UART3_CTSN/GPIO2_27GPIO2_16]||F18U3||VAUX2||IO||||
|-
| 114123||AM335X_LCD_DATA6AM335X_MMC_CLK||CPU.[LCD_DATA6MMC0_CLK/GPMC_A6GPMC_A24/PR1_EDIO_DATA_IN6UART3_CTSN/EQEP2_INDEXUART2_RXD/PR1_EDIO_DATA_OUT6DCAN1_TX/PR1_PRU1_PRU_R30_6PR1_PRU0_PRU_R30_12/PR1_PRU1_PRU_R31_6PR1_PRU0_PRU_R31_12/GPIO2_12GPIO2_30]||T3G17||VMMC||IO||||
|-
| 115124||AM335X_MMC_D1AM335X_LCD_DATA11||CPU.[MMC0_DAT1LCD_DATA11/GPMC_A22GPMC_A15/UART5_CTSNEHRPWM1B/UART3_RXDMCASP0_AHCLKR/UART1_DTRNMCASP0_AXR2/PR1_PRU0_PRU_R30_10PR1_MII0_RXD0/PR1_PRU0_PRU_R31_10UART3_RTSN/GPIO2_28GPIO2_17]||G15U4||VAUX2||IO||||
|-
| 116125||AM335X_LCD_DATA7JTAG_EMU1||CPU.[LCD_DATA7EMU1/GPMC_A7/PR1_EDIO_DATA_IN7/EQEP2_STROBE/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_7/PR1_PRU1_PRU_R31_7/GPIO2_13GPIO3_8]||T4B14||VAUX2||IO||10kΩ ↑||
|-
| 117126||AM335X_MMC_D0AM335X_LCD_DATA12||CPU.[MMC0_DAT0LCD_DATA12/GPMC_A23GPMC_A16/UART5_RTSNEQEP1A_IN/UART3_TXDMCASP0_ACLKR/UART1_RINMCASP0_AXR2/PR1_PRU0_PRU_R30_11PR1_MII0_RXLINK/PR1_PRU0_PRU_R31_11UART4_CTSN/GPIO2_29GPIO0_8]||G16V2||VAUX2||IO||||
|-
| 118127||AM335X_LCD_DATA8JTAG_EMU0||CPU.[LCD_DATA8EMU0/GPMC_A12/EHRPWM1_TRIPZONE_INPUT/MCASP0_ACLKX/UART5_TXD/PR1_MII0_RXD3/UART2_CTSN/GPIO2_14GPIO3_7]||U1C14||VAUX2||IO||10kΩ ↑||
|-
| 119128||AM335X_MMC_CMDAM335X_LCD_DATA13||CPU.[MMC0_CMDLCD_DATA13/GPMC_A25GPMC_A17/UART3_RTSNEQEP1B_IN/UART2_TXDMCASP0_FSR/DCAN1_RXMCASP0_AXR3/PR1_PRU0_PRU_R30_13PR1_MII0_RXER/PR1_PRU0_PRU_R31_13UART4_RTSN/GPIO2_31GPIO0_9]||G18V3||VAUX2||IO||||
|-
| 120129||AM335X_LCD_DATA9JTAG_TDO||CPU.[LCD_DATA9/GPMC_A13/EHRPWM1_SYNCO/MCASP0_FSX/UART5_RXD/PR1_MII0_RXD2/UART2_RTSN/GPIO2_15]TDO||U2A11||VAUX2||O||||
|-
| 121130||DGNDAM335X_LCD_DATA14||CPU.[LCD_DATA14/GPMC_A18/EQEP1_INDEX/MCASP0_AXR1/UART5_RXD/PR1_MII_MR0_CLK/UART5_CTSN/GPIO0_10]||V4||VAUX2||IO||||
|-
| 122131||AM335X_LCD_DATA10JTAG_TDI||CPU.[LCD_DATA10/GPMC_A14/EHRPWM1A/MCASP0_AXR0//PR1_MII0_RXD1/UART3_CTSN/GPIO2_16]TDI||U3B11||VAUX2||I||||
|-
| 123132||AM335X_MMC_CLKDGND||CPU.[MMC0_CLK/GPMC_A24/UART3_CTSN/UART2_RXD/DCAN1_TX/PR1_PRU0_PRU_R30_12/PR1_PRU0_PRU_R31_12/GPIO2_30]||G17|||||G|||
|-
| 124133||AM335X_LCD_DATA11JTAG_TMS||CPU.[LCD_DATA11/GPMC_A15/EHRPWM1B/MCASP0_AHCLKR/MCASP0_AXR2/PR1_MII0_RXD0/UART3_RTSN/GPIO2_17]TMS||U4C11||VAUX2||I||||
|-
| 125134||JTAG_EMU1AM335X_LCD_DATA15||CPU.[EMU1LCD_DATA15/GPMC_A19/EQEP1_STROBE/MCASP0_AHCLKX/MCASP0_AXR3/PR1_MII0_RXDV/UART5_RTSN/GPIO3_8GPIO0_11]||B14T5||VAUX2||IO||||
|-
| 126135||AM335X_LCD_DATA12JTAG_TRSTn||CPU.[LCD_DATA12/GPMC_A16/EQEP1A_IN/MCASP0_ACLKR/MCASP0_AXR2/PR1_MII0_RXLINK/UART4_CTSN/GPIO0_8]TRSTn||V2B10||VAUX2||I||10kΩ ↓||
|-
| 127136||JTAG_EMU0AM335X_MCASP0_FSR||CPU.[EMU0MCASP0_FSR/EQEP0B_IN/MCASP0_AXR3/MCASP1_FSX/EMU2/PR1_PRU0_PRU_R30_5/PR1_PRU0_PRU_R31_5/GPIO3_7GPIO3_19]||C14C13||VAUX2||IO||||
|-
| 128137||AM335X_LCD_DATA13JTAG_TCK||CPU.[LCD_DATA13/GPMC_A17/EQEP1B_IN/MCASP0_FSR/MCASP0_AXR3/PR1_MII0_RXER/UART4_RTSN/GPIO0_9]TCK||V3A12||VAUX2||I||||
|-
| 129138||JTAG_TDOAM335X_MCASP0_AXR1||CPU.TDO[MCASP0_AXR1/EQEP0_INDEX//MCASP1_AXR0/EMU3/PR1_PRU0_PRU_R30_6/PR1_PRU0_PRU_R31_6/GPIO3_20]||A11D13||VAUX2||IO||||
|-
| 130139||AM335X_LCD_DATA14ETH_CTTD||CPU.[LCD_DATA14/GPMC_A18/EQEP1_INDEX/MCASP0_AXR1/UART5_RXD/PR1_MII_MR0_CLK/UART5_CTSN/GPIO0_10]||V4||||S||||
|-
| 131140||JTAG_TDIAM335X_MCASP0_FSX||CPU.TDI[MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15]||B11B13||VAUX2||IO||||
|-
| 132141||DGND|||||||||G|||
|-
| 133142||JTAG_TMSAM335X_MCASP0_AXR0||CPU.TMS[MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16]||C11D12||VAUX2||IO||||
|-
| 134143||AM335X_LCD_DATA15ETH_CTRD||CPU.[LCD_DATA15/GPMC_A19/EQEP1_STROBE/MCASP0_AHCLKX/MCASP0_AXR3/PR1_MII0_RXDV/UART5_RTSN/GPIO0_11]||T5||||S||||
|-
| 135144||JTAG_TRSTnAM335X_MCASP0_AHCLKR||CPU.TRSTn[MCASP0_AHCLKR/EHRPWM0_SYNCI_O/MCASP0_AXR2/SPI1_CS0/ECAP2_IN_PWM2_OUT/PR1_PRU0_PRU_R30_3/PR1_PRU0_PRU_R31_3/GPIO3_17]||B10C12||VAUX2||IO||||
|-
| 136145||AM335X_MCASP0_FSRETH_TX-||CPUETHPHY.[MCASP0_FSR/EQEP0B_IN/MCASP0_AXR3/MCASP1_FSX/EMU2/PR1_PRU0_PRU_R30_5/PR1_PRU0_PRU_R31_5/GPIO3_19]TXN||C1328||||D||||
|-
| 137146||JTAG_TCKAM335X_MCASP0_ACLKR||CPU.TCK[MCASP0_ACLKR/EQEP0A_IN/MCASP0_AXR2/MCASP1_ACLKX/MMC0_SDWP/PR1_PRU0_PRU_R30_4/PR1_PRU0_PRU_R31_4/GPIO3_18]||A12B12||VAUX2||IO||||
|-
| 138147||AM335X_MCASP0_AXR1ETH_TX+||CPUETHPHY.[MCASP0_AXR1/EQEP0_INDEX//MCASP1_AXR0/EMU3/PR1_PRU0_PRU_R30_6/PR1_PRU0_PRU_R31_6/GPIO3_20]TXP||D1329||||D||||
|-
| 139148||ETH_CTTDAM335X_MCASP0_AHCLKX||CPU.[MCASP0_AHCLKX/EQEP0_STROBE/MCASP0_AXR3/MCASP1_AXR1/EMU4/PR1_PRU0_PRU_R30_7/PR1_PRU0_PRU_R31_7/GPIO3_21]||A14||VAUX2||IO||||
|-
| 140149||AM335X_MCASP0_FSXETH_RX-||CPUETHPHY.[MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15]RXN||B1330||||D||||
|-
| 141150||DGNDAM335X_MCASP0_ACLKX||CPU.[MCASP0_ACLKX/EHRPWM0A//SPI1_SCLK/MMC0_SDCD/PR1_PRU0_PRU_R30_0/PR1_PRU0_PRU_R31_0/GPIO3_14]||A13||VAUX2||IO||||
|-
| 142151||AM335X_MCASP0_AXR0ETH_RX+||CPUETHPHY.[MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16]RXP||D1231||||D||||
|-
| 143152||ETH_CTRD|DGND||||||||G|||
|-
| 144153||AM335X_MCASP0_AHCLKREMAC0_PHY_LED_SPEED||CPUETHPHY.[MCASP0_AHCLKRLED2/EHRPWM0_SYNCI_O/MCASP0_AXR2/SPI1_CS0/ECAP2_IN_PWM2_OUT/PR1_PRU0_PRU_R30_3/PR1_PRU0_PRU_R31_3/GPIO3_17]nINTSEL||C122||3.3V||O||10kΩ ↓||10kOhm pull-down
|-
| 145154||ETH_TX-NC Optional routing:* PMIC_VRTC* VDD3_SMPS* VDIG1||ETHPHY.TXN||28||||||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 146155||AM335X_MCASP0_ACLKREMAC0_PHY_LED_LINK/ACT||CPUETHPHY.[MCASP0_ACLKR/EQEP0A_IN/MCASP0_AXR2/MCASP1_ACLKX/MMC0_SDWP/PR1_PRU0_PRU_R30_4/PR1_PRU0_PRU_R31_4LED1/GPIO3_18]nREGOFF||B123||3.3V||O||10kΩ ↓||10kOhm pull-down
|-
| 147156||ETH_TX+NC Options routing: VRTC_LDO||ETHPHY.TXP||29||||||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 148157||AM335X_MCASP0_AHCLKXAM335X_GMII1_TXD3||CPU.[MCASP0_AHCLKXGMII1_TXD3/EQEP0_STROBEDCAN0_TX/MCASP0_AXR3RGMII1_TD3/MCASP1_AXR1UART4_RXD/EMU4MCASP1_FSX/PR1_PRU0_PRU_R30_7MMC2_DAT1/PR1_PRU0_PRU_R31_7MCASP0_FSR/GPIO3_21GPIO0_16]||A14J18||VAUX2||IO||||
|-
| 149158||ETH_RX-NCOptional routing: VDAC||ETHPHY.RXN||30||||||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 150159||AM335X_MCASP0_ACLKX|AM335X_GMII1_TXD2Ordering codes:* DDxxxxx1xxx* DDxxxxx2xxx* DDxxxxx5xxx|CPU.[MCASP0_ACLKXGMII1_TXD2/EHRPWM0ADCAN0_RX/RGMII1_TD2/SPI1_SCLKUART4_TXD/MMC0_SDCDMCASP1_AXR0/PR1_PRU0_PRU_R30_0MMC2_DAT2/PR1_PRU0_PRU_R31_0MCASP0_AHCLKX/GPIO3_14GPIO0_17]||A13K15||VAUX2||IO||||Internally connected to the WDT
|-
| 151||ETH_RX+||ETHPHY.RXP||31|159|NCOrdering codes:* DDxxxxx0xxx* DDxxxxx3xxx||||||
|-
| 152160||DGND|NCOptional routing: VPLL|||||||||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 153161||EMAC0_PHY_LED_SPEEDDGND||ETHPHY.LED2/nINTSEL||2||||G||||10kOhm pull-down
|-
| 154162||NC/OUT_PMIC_VRTC//OUT_VDD3_SMPS//OUT_VDIG1|Optional routing: VAUX1|||||||||||By default , this pin must not be connected. Optionally , it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. For As these options require custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information please contact technical support.
|-
| 155163||EMAC0_PHY_LED_LINK/ACTAM335X_GMII1_RXDV||ETHPHYCPU.LED1[GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/nREGOFFGPIO3_4]||3J17||VAUX2||IO||||
|-
| 156164||NC/Voltage monitoring|Optional routing: VAUX2|||||||||||By default , this pin must not be connected. Optionally , it can route power voltage voltages generated by Diva PSU. This option is meant to allow monitoring of such voltage voltages by carrier board circuitry. It is not meant to power carrier board devices. For As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information please contact technical support.
|-
| 157165||AM335X_GMII1_TXD3AM335X_GMII1_MDIO_CLK||CPU.[GMII1_TXD3MDIO_CLK/DCAN0_TXTIMER5/RGMII1_TD3UART5_TXD/UART4_RXDUART3_RTSN/MCASP1_FSXMMC0_SDWP/MMC2_DAT1MMC1_CLK/MCASP0_FSRMMC2_CLK/GPIO0_16GPIO0_1]||J18M18||VAUX2||IO||||Internally connected to the ETH PHY
|-
| 158166||NC/Voltage monitoring| Optional routing: VDD1_SMPS|||||||||||By default , this pin must not be connected. Optionally , it can route power voltage voltages generated by Diva PSU. This option is meant to allow monitoring of such voltage voltages by carrier board circuitry. It is not meant to power carrier board devices. For As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information please contact technical support.
|-
| 159167||AM335X_GMII1_TXD2AM335X_GMII1_MDIO_DATA||CPU.[GMII1_TXD2MDIO_DATA/DCAN0_RXTIMER6/RGMII1_TD2UART5_RXD/UART4_TXDUART3_CTSN/MCASP1_AXR0MMC0_SDCD/MMC2_DAT2MMC1_CMD/MCASP0_AHCLKXMMC2_CMD/GPIO0_17GPIO0_0]||K15M17||VAUX2||IO||1.5kΩ ↑||Internally connected to the ETH PHY
|-
| 160168||NC/Voltage monitoring|Optional routing: VDD2_SMPS|||||||||||By default , this pin must not be connected. Optionally , it can route power voltage voltages generated by Diva PSU. This option is meant to allow monitoring of such voltage voltages by carrier board circuitry. It is not meant to power carrier board devices. For As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information please contact technical support.
|-
| 161169||DGNDAM335X_GMII1_COL||CPU.[GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0]||H16||VAUX2||IO||||Internally used for DDR power management (if required) – HW option
|-
| 162170||NC/Voltage monitoringPORSTn_OUT||||||VAUX2||I||10kΩ ↓||By default this pin must not be connected. Optionally it can route power See [[#Reset scheme and voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support]].
|-
| 163171||AM335X_GMII1_RXDVAM335X_GMII1_RXD3||CPU.[GMII1_RXDVGMII1_RXD3/LCD_MEMORY_CLKUART3_RXD/RGMII1_RCTLRGMII1_RD3/UART5_TXDMMC0_DAT5/MCASP1_ACLKXMMC1_DAT2/MMC2_DAT0UART1_DTRN/MCASP0_ACLKRMCASP0_AXR0/GPIO3_4GPIO2_18]||J17L17||VAUX2||IO||||
|-
| 164172||NC/Voltage monitoringDGND||||||||G||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 165173||AM335X_GMII1_MDIO_CLKAM335X_GMII1_RXD2||CPU.[MDIO_CLKGMII1_RXD2/TIMER5UART3_TXD/UART5_TXDRGMII1_RD2/UART3_RTSNMMC0_DAT4/MMC0_SDWPMMC1_DAT3/MMC1_CLKUART1_RIN/MMC2_CLKMCASP0_AXR1/GPIO0_1GPIO2_19]||M18L16||VAUX2||IO||||
|-
| 166174||NC/Voltage monitoringCB_PWR_GOOD||||||VIN|I|||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva See [[#Power Supply Unit (PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to ) and recommended power carrier board devices. For more information please contact technical support-up sequence]].
|-
| 167175||AM335X_GMII1_MDIO_DATAAM335X_GMII1_RXCLK||CPU.[MDIO_DATAGMII1_RXCLK/TIMER6UART2_TXD/UART5_RXDRGMII1_RCLK/UART3_CTSNMMC0_DAT6/MMC0_SDCDMMC1_DAT1/MMC1_CMDUART1_DSRN/MMC2_CMDMCASP0_FSX/GPIO0_0GPIO3_10]||M17L18||VAUX2||IO||||
|-
| 168176||NC/Voltage monitoring| Optional routing: VDIG2|||||||||||By default , this pin must not be connected. Optionally , it can route power voltage voltages generated by Diva PSU. This option is meant to allow monitoring of such voltage voltages by carrier board circuitry. It is not meant to power carrier board devices. For As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information please contact technical support.
|-
| 169177||AM335X_GMII1_COLAM335X_GMII1_TXCLK||CPU.[GMII1_COLGMII1_TXCLK/RMII2_REFCLKUART2_RXD/SPI1_SCLKRGMII1_TCLK/UART5_RXDMMC0_DAT7/MCASP1_AXR2MMC1_DAT0/MMC2_DAT3UART1_DCDN/MCASP0_AXR2MCASP0_ACLKX/GPIO3_0GPIO3_9]||H16K18||VAUX2||IO||||
|-
| 170178||PORSTn_OUTNC Optional routing: DDR_VDDS||||||||||||See By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [[#Reset scheme and voltage monitoring]mailto:sales@dave.eu Sales Department]for more information.
|-
| 171179||AM335X_GMII1_RXD3PMIC_CLK32OUT||CPUPMIC.[GMII1_RXD3/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18]CLK32KOUT||L17|PMIC.38||VAUX33|O||||
|-
| 172180||DGNDOUT_VAUX33||PMIC.VAUX33||PMIC.4||VAUX33|O||||This signal can be used to synchronize powering on/off of carrier board circuitry that interfaces CPU I/O directly. Please refer to section [[Hardware_Manual_(Diva)#Power_Supply_Unit_.28PSU.29_and_recommended_power-up_sequence |PSU and recommended power up sequence]].
|-
| 173181||AM335X_GMII1_RXD2DGND||CPU.[GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1/GPIO2_19]||L16|||||G|||
|-
| 174182||CB_PWR_GOODNC Optional routing: VMMC||||||||||||See [[#Power Supply Unit (By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU) and recommended . This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power-up sequence]carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department]for more information.
|-
| 175183||AM335X_GMII1_RXCLKPMIC_PWR_EN||CPU.[GMII1_RXCLK/UART2_TXD/RGMII1_RCLK/MMC0_DAT6/MMC1_DAT1/UART1_DSRN/MCASP0_FSX/GPIO3_10]PMIC_PWR_EN, PMIC.PWRHOLD||L18CPU.C6, PMIC.1||VRTC||O||||
|-
| 176184||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 177||AM335X_GMII1_TXCLK||CPUOptional routing: 3.[GMII1_TXCLK/UART2_RXD/RGMII1_TCLK/MMC0_DAT7/MMC1_DAT0/UART1_DCDN/MCASP0_ACLKX/GPIO3_9]||K18|||||||||-3V| 178||NC/Voltage monitoring||||||||||||By default , this pin must not be connected. Optionally , it can route power voltage voltages generated by Diva PSU. This option is meant to allow monitoring of such voltage voltages by carrier board circuitry. It is not meant to power carrier board devices. For more information As these options requires custom manufacturing BOMs, please contact technical supportthe [mailto:sales@dave.|-| 179||PMIC_CLK32OUT||PMIC.CLK32KOUT||PMIC.38|||||||||-| 180||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For eu Sales Department] for more information please contact technical support.|-| 181||DGND|||||||||||||-| 182||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 183||PMIC_PWR_EN||CPU.PMIC_PWR_EN, PMIC.PWRHOLD||CPU.C6, PMIC.1|||||||||-| 184||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
|-
| 185||PMIC_INT1||PMIC.INT1||PMIC.45||VAUX33||O||||
|-
| 186||VIN||||||||S||||
|-
| 187||PMIC_SLEEP||PMIC.SLEEP||PMIC.37||VAUX33||I||||
|-
| 188||VIN||||||||S||||
|-
| 189||PMIC_PWRON||PMIC.PWRON||PMIC.33|VIN||I|||10kΩ ↑||
|-
| 190||VIN||||||||S||||
|-
| 191||PMIC_nRESPWRON||PMIC.nRESPWRON||PMIC.40|VAUX33|O||||10kΩ ↓||
|-
| 192||DGND|||||||||G|||
|-
| 193||MRSTn||||||3.3V||I||10kΩ ↑||Internally connected to PORSTn with logic port
|-
| 194||VIN||||||||S||||
|-
| 195||RTC_PWRONRSTn||CPU.RTC_PWRONRSTn||B5||VRTC||I||100kΩ ↓||Internally connected to VRTC with logic port
|-
| 196||VIN||||||||S||||
|-
| 197||WARMRSTn||CPU.WARMRSTn|A10|VAUX2||O||10kΩ ↑||||Internally connected to NOR flash and ETH PHY
|-
| 198||VIN||||||||S||||
|-
| 199||EXT_PORSTn||||||3.3V||I||10kΩ ↑||Internally connected to PORSTn_OUT with logic port
|-
| 200||VIN||||||||S||||
|-
| 201||DGND|||||||||G|||
|-
| 202||VIN||||||||S||||
|-
| 203||PMIC_VBACKUP||PMIC.VBACKUP||27||VBACKUP|S|||||Short to VIN if No not used
|-
| 204||VIN||||||||S||||
|-
|}
|I2C0 clock
|J1.3
|Internally connected to a 10K pull-up resistor
|-
|I2C0_SDA
|I2C0 data
|J1.5
|Internally connected to a 10K pull-up resistor
|-
|}
|I2C1 clock
|J1.29<br>J1.33<br>J1.49
|No pull-up/pull-down
|-
|I2C1_SDA
|I2C1 data
|J1.31<br>J1.35<br>J1.47
|No pull-up/pull-down
|-
|}
|I2C2 clock
|J1.25<br>J1.37<br>J1.45
|No pull-up/pull-down
|-
|I2C2_SDA
|I2C2 data
|J1.27<br>J1.39<br>J1.43
|No pull-up/pull-down|-|} == EEPROM ==One EEPROM is available to provide additional non-volatile storage area for user-specific usage. It is connected to the I2C-0 bus. A1 and A0 bits of address can be configured at carrier board level. Device address is 10100[A1][A0]b.The following table describes the interface signals: {| class="wikitable" |-!Pin name!Connector pin!Function!Notes|-|EEPROM_A0|J1.17|I²C Address pin|A0 address bit can be configured at carrier board level|-|EEPROM_A1|J1.15|I²C Address pin|A1 address bit can be configured at carrier board level|-|EEPROM_WP|J1.13|Write protect|Active high
|-
|}
|}
== 3.3V GPIOs ==
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs, for connections to external devices. In addition, the GPIO peripheral can produce CPU interrupts in different interrupt generation modes. The device contains four 3.3 V GPIO modules and each GPIO module is made up of up to 32 identical channels. The device GPIO peripheral supports , for up to 118 1.8-V/3.3-V GPIO pins, (GP0[0:31], GP1[0:31], GP2[0:31], and GP3[0:21]). Each channel must be properly configured, since GPIO signals are multiplexed with other interfaces signals.
= Operational Characteristics =
|-
|Main power supply voltage
|3.6|35.3V0|5.5
|V
|-
|-
|Main power supply voltage
|3.6|35.3V0|5.5
|V
|-
Measurements have been performed on the following platform:
* Diva SOM@ 5V* CPU frequency: 800 MHz
* Carrier board: DivaEVB-Lite on DACU
* System software: DELK DIVELK preliminary version
The test bench runs the following softwarea stress test suite, comprising several processes:
* burnCortexA8 in continuous loop
==== Results ====
With this test bench, the CPU load is always 100% and many components are active at the same time, so this is a non-realistic worst case scenario. The average measured power consumption is 2,.6 W. == Heat dissipation == This section will be completed in a future version of this manual.
= Application notes =
Please refer to the following documents available on Dave '''DAVE Embedded Systems''' Developers Wiki:
* [[Carrier_board_design_guidelines_%28SOM%29]]
* [[Integration_guide_%28Diva%29]]
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