|
|
| Line 1: |
Line 1: |
| − | {{InfoBoxTop}}
| + | = Introduction = |
| − | {{Applies To Bora}}
| |
| − | {{InfoBoxBottom}}
| |
| | | | |
| − | | + | Bora Hardware Manual describes the Bora CPU modules family design and functions. |
| − | = Preface =
| |
| − | | |
| − | == About this manual ==
| |
| − | | |
| − | This Hardware Manual describes the Bora CPU module design and functions.
| |
| − | Precise specifications for the Xilinx Zynq processor can be found in the CPU datasheets and/or reference manuals.
| |
| − | | |
| − | == Copyright/Trademarks ==
| |
| − | | |
| − | Ethernet® is a registered trademark of XEROX Corporation.
| |
| − | | |
| − | All other products and trademarks mentioned in this manual are property of their respective owners.
| |
| − | | |
| − | All rights reserved. Specifications may change at any time without notice.
| |
| − | | |
| − | == Standards ==
| |
| − | | |
| − | Dave SrL is certified to ISO 9001 standards.
| |
| − | | |
| − | == Disclaimers ==
| |
| − | | |
| − | DAVE does not assume any responsibility about availability, supplying and support regarding all the products mentioned in this manual that are not strictly part of the Bora CPU module.
| |
| − | Bora CPU Modules are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Dave Srl customers who are using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Dave Srl for any damage resulting from such improper use or sale.
| |
| − | | |
| − | == Warranty ==
| |
| − | | |
| − | Bora is warranted against defects in material and workmanship for the warranty period from the date of shipment. During the warranty period, Dave Srl will at its discretion decide to repair or replace defective products. Within the warranty period, the repair of products is free of charge as long as warranty conditions are observed.
| |
| − | The warranty does not apply to defects resulting from improper or inadequate maintenance or handling by the buyer, unauthorized modification or misuse, operation outside of the product’s environmental specifications or improper installation or maintenance.
| |
| − | Dave Srl will not be responsible for any defects or damages to other products not supplied by Dave Srl that are caused by a faulty Bora module.
| |
| − | | |
| − | == Technical Support ==
| |
| − | | |
| − | We are committed to making our product easy to use and will help customers use our CPU modules in their systems. Technical support is delivered through email to our valued customers. Support requests can be sent to '''support-bora@dave.eu'''.
| |
| − | Software upgrades are available for download in the restricted access download area of DAVE web site: http://www.dave.eu/reserved-area. An account is required to access this area and is provided to customers who purchase the development kit (please contact support-bora@dave.eu for account requests)..
| |
| − | Please refer to our Web site at http://www.dave.eu/dave-cpu-module-zynq-bora.html for the latest product documentation, utilities, drivers, Product Change Notifications, Board Support Packages, Application Notes, mechanical drawings and additional tools and software.
| |
| − | | |
| − | == Related Documents ==
| |
| − | | |
| − | {| class="wikitable" |
| |
| − | | align="center" style="background:#f0f0f0;"|'''Document'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Location'''
| |
| − | |-
| |
| − | | Dave Developers' Wiki||http://wiki.dave.eu/index.php/Main_Page
| |
| − | |-
| |
| − | | <br>||
| |
| − | |-
| |
| − | |+ align="bottom" style="caption-side: bottom" | Table: related documents
| |
| − | |}
| |
| − | | |
| − | == Hardware Manual in PDF format ==
| |
| | | | |
| | Please download the [http://www.dave.eu/sites/default/files/files/bora-hm.pdf Bora Hardware Manual in pdf format] | | Please download the [http://www.dave.eu/sites/default/files/files/bora-hm.pdf Bora Hardware Manual in pdf format] |
| − |
| |
| − | == Conventions, Abbreviations, Acronyms ==
| |
| − | {| class="wikitable" |
| |
| − | | align="center" style="background:#f0f0f0;"|'''Abbreviation'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Definition'''
| |
| − | |-
| |
| − | | BTN||Button
| |
| − | |-
| |
| − | | GPI||General Purpose Input
| |
| − | |-
| |
| − | | GPIO||Generla Purpose Input and Output
| |
| − | |-
| |
| − | | GPO||General Purpose Output
| |
| − | |-
| |
| − | | BELK||Bora Embedded Linux Kit
| |
| − | |-
| |
| − | | PCB||Printed Circuit Board
| |
| − | |-
| |
| − | | RTC||Real Time Clock
| |
| − | |-
| |
| − | | SOM||System On Module
| |
| − | |-
| |
| − | | PMIC||Power Managemente Integrated Circuit
| |
| − | |-
| |
| − | | <br>||
| |
| − | |-
| |
| − | | <br>||
| |
| − | |-
| |
| − | | <br>||
| |
| − | |-
| |
| − | |+ align="bottom" style="caption-side: bottom" | Table: Abbreviations and acronyms used in this manual
| |
| − | |}
| |
| − |
| |
| − | = Introduction =
| |
| − |
| |
| − | BORA is the new top-class Dual Cortex-A9 + FPGA CPU module by DAVE, based on the recent Xilinx Zynq XC7Z010/XC7Z020 application processor.
| |
| − | Thanks to BORA, customers are going to save time and resources by using a compact solution that includes both a CPU and an FPGA, avoiding complexities on the carrier PCB.
| |
| − | The use of this processor enables extensive system-level differentiation of new applications in many industry fields, where high performances and extremely compact form factor (85mm x 50mm) are key factors. Smarter system designs are made possible, following the trends in functionalities and interfaces of the new, state-of-the-art embedded products.
| |
| − | BORA offers great computational power, thanks to the rich set of peripherals, the Dual Cortex-A9 and the Artix-7 FPGA together with a large set of high-speed I/Os (up to 5GHz).
| |
| − | BORA enables designers to create rugged products suitable for harsh mechanical and thermal environments, allowing the development of the most advanced and robust products.
| |
| − | Thanks to the tight integration between the ARM-based processing system and the on-chip programmable logic, designers are free to add virtually any peripheral or create custom accelerators that extend system performance and better match specific application requirements.
| |
| − | BORA is designed and manufactured according to DAVE Ultra Line specifications, in order to guarantee premium quality and technical value for customers who require top performances and flexibility. BORA is suitable for high-end applications such as medical instrumentation, advanced communication systems, critical real-time operations and safety applications.
| |
| − |
| |
| − | == Product Highlights ==
| |
| − |
| |
| − | * Unmatched performance thanks to dual ARM Cortex-A9 @ 800 MHz
| |
| − | * All memories you need: on-board NOR and NAND Flash
| |
| − | * Enabling smarter system thanks to Artix-7 FPGA integrated on chip
| |
| − | * FPGA banks with wide-range PSU input (from 1.2V to 3.3V)
| |
| − | * Highest security and reliability: internal voltage monitoring and power good enable
| |
| − | * Reduced carrier complexity: dual CAN, USB, Ethernet GB and native 3.3V I/O
| |
| − | * Easy to fi t thanks to its small form factor
| |
| − | * Precise timing application thanks to on-board 5ppm RTC
| |
| − |
| |
| − | == Block Diagram ==
| |
| − |
| |
| − | The following image shows Bora's block diagram:
| |
| − |
| |
| − | [[File:Bora-bd.png|700px|center]]
| |
| − |
| |
| − | == Feature Summary ==
| |
| − | {| class="wikitable" |
| |
| − | | align="center" style="background:#f0f0f0;"|'''Feature'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Specifications'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Options'''
| |
| − | |-
| |
| − | | CPU||Xilinx Dual ARM Cortex-A9<br>ZYNQ XC7Z010/ZC7Z020 @ 800MHz ||
| |
| − | |-
| |
| − | | Cache||L1: 32Kbyte instruction, 32Kbyte data<br>L2: 512Kbyte for each core ||
| |
| − | |-
| |
| − | | RAM|| DDR3 SDRAM @ 533 MHz<br>Up to 1 GB ||
| |
| − | |-
| |
| − | | Storage||Flash NOR SPI (8, 16, 32 MB)<br>Flash NAND (all sizes, on request) ||
| |
| − | |-
| |
| − | |+ align="bottom" style="caption-side: bottom" | Table: CPU and Memories
| |
| − | |}
| |
| − |
| |
| − | {| class="wikitable" |
| |
| − | | align="center" style="background:#f0f0f0;"|'''Feature'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Specifications'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Options'''
| |
| − | |-
| |
| − | | Coprocessors|| NEON™ & Single / Double Precision<br>Floating Point for each processor||
| |
| − | |-
| |
| − | | USB||Up to 2x 2.0 OTG ports ||
| |
| − | |-
| |
| − | | UARTs||Up to 2x UART ports ||
| |
| − | |-
| |
| − | | GPIO||Up to x lines, shared with other functions (interrupts available) ||
| |
| − | |-
| |
| − | | Networks||Fast Ethernet 10/100Mbps ||
| |
| − | |-
| |
| − | | CAN||2x full CAN 2.0B compliant interfaces ||
| |
| − | |-
| |
| − | | SD/MMC||2x SD/SDIO 2.0/MMC3.31 compliant controllers ||
| |
| − | |-
| |
| − | | Serial buses||2x full-duplex SPI ports with three peripheral chip selects<br>2x master and slave I²C interfaces ||
| |
| − | |-
| |
| − | | Timers||2x triple timers/counters (TTC) ||
| |
| − | |-
| |
| − | | RTC ||On board (DS3232), external battery powered ||
| |
| − | |-
| |
| − | | Debug||JTAG IEEE 1149.1 Test Access Port<br>CoreSight™ and Program Trace Macrocell (PTM) ||
| |
| − | |-
| |
| − | |+ align="bottom" style="caption-side: bottom" | Table: Peripherals
| |
| − | |}
| |
| − |
| |
| − | {| class="wikitable" |
| |
| − | | align="center" style="background:#f0f0f0;"|'''Feature'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Specifications'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Options'''
| |
| − | |-
| |
| − | | FPGA model||Artix™-7||
| |
| − | |-
| |
| − | | Logic cells||28K to 56K||
| |
| − | |-
| |
| − | | LUTs||17K to 53K||
| |
| − | |-
| |
| − | | Flip flops||35K to 100K||
| |
| − | |-
| |
| − | | RAM||240KB to 560KB||
| |
| − | |-
| |
| − | | DSP slices||80 to 220||
| |
| − | |-
| |
| − | | Differential pairs||Up to 34 differential pairs for high freq. interfaces||
| |
| − | |-
| |
| − | |+ align="bottom" style="caption-side: bottom" | Table: Electrical, Mechanical and Environmental Specifications
| |
| − | |}
| |
| − |
| |
| − | {| class="wikitable" |
| |
| − | | align="center" style="background:#f0f0f0;"|'''Feature'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Specifications'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Options'''
| |
| − | |-
| |
| − | | Supply Voltage||3.3V, on-board voltage regulation||
| |
| − | |-
| |
| − | | Active power consumption|| Please refer to [[Hardware_Manual_(Bora)#Power_consumption | Power consumption]] section||
| |
| − | |-
| |
| − | | Dimensions||85mm x 50mm||
| |
| − | |-
| |
| − | | Weight|| ||
| |
| − | |-
| |
| − | | MTBF|| ||
| |
| − | |-
| |
| − | | Operating temperature||0..70 °C<br>-40..+85 °C||
| |
| − | |-
| |
| − | | Connectors||3 x 140 pins 0.6mm pitch||
| |
| − | |-
| |
| − | |+ align="bottom" style="caption-side: bottom" | Table: Electrical, Mechanical and Environmental Specifications
| |
| − | |}
| |
| − |
| |
| − | = Design Overview =
| |
| − |
| |
| − | The heart of Bora module is composed of the following components:
| |
| − | * Xilinx Zynq Z-7010 (XC7Z010) / Z-7020 (XC7Z020) SoC
| |
| − | * Power supply unit
| |
| − | * DDR memory banks
| |
| − | * NOR and NAND flash banks
| |
| − | * 3x 140 pin connectors with interfaces signals
| |
| − |
| |
| − | This chapter shortly describes the main Bora components.
| |
| − |
| |
| − | == Processor Info ==
| |
| − |
| |
| − | The Zynq™-7000 family is based on the Xilinx Extensible Processing Platform (EPP) architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.
| |
| − | The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 AP SoC family enables designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a result, the Zynq-7000 AP SoC devices are able to serve a wide range of applications including:
| |
| − | * Automotive driver assistance, driver information, and infotainment
| |
| − | * Broadcast camera
| |
| − | * Industrial motor control, industrial networking, and machine vision
| |
| − | * IP and Smart camera
| |
| − | * LTE radio and baseband
| |
| − | * Medical diagnostics and imaging
| |
| − | * Multifunction printers
| |
| − | * Video and night vision equipment
| |
| − |
| |
| − | The following table shows a comparison between the devices, highlighting the differences:
| |
| − |
| |
| − | {| class="wikitable" |
| |
| − | | align="center" style="background:#f0f0f0;"|'''Processor'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Programmable logic cells'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''LUTs'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Flip flops'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Extensible block RAM'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''DSP slices'''
| |
| − | | align="center" style="background:#f0f0f0;"|'''Peak DSP performance'''
| |
| − | |-
| |
| − | | XC7Z010 ||28K Logic Cells ||17600 ||35200 ||240 KB ||80 ||58 GMACs
| |
| − | |-
| |
| − | | XC7Z020 ||85K Logic Cells ||53200 ||106400 ||560 KB ||220 ||158 GMACs
| |
| − | |-
| |
| − | |+ align="bottom" style="caption-side: bottom" | Table: XC7-Z0x0 comparison
| |
| − | |}
| |
| − |
| |
| − | == RAM memory bank ==
| |
| − |
| |
| − | DDR3 SDRAM memory bank is composed by 2x 16-bit width chips resulting in a 32-bit combined width bank. The following table reports the SDRAM specifications:
| |
| − |
| |
| − | {| class="wikitable" |
| |
| − | |-
| |
| − | | '''CPU connection'''||SDRAM bus
| |
| − | |-
| |
| − | | '''Size min'''||512 MB
| |
| − | |-
| |
| − | | '''Size max'''||1 GB
| |
| − | |-
| |
| − | | '''Width'''||32 bit
| |
| − | |-
| |
| − | | '''Speed'''||533 MHz
| |
| − | |-
| |
| − | |}
| |
| − |
| |
| − | == NOR flash bank ==
| |
| − |
| |
| − | NOR flash is a Serial Peripheral Interface (SPI) device. By default this device is connected to SPI channel 0 and acts as boot memory. The following table reports the NOR flash specifications:
| |
| − |
| |
| − | {| class="wikitable" |
| |
| − | |-
| |
| − | | '''CPU connection'''||SPI Channel 0
| |
| − | |-
| |
| − | | '''Size min'''||8 MB
| |
| − | |-
| |
| − | | '''Size max'''||64 MB
| |
| − | |-
| |
| − | | '''Chip select'''||SPI_CS0n
| |
| − | |-
| |
| − | | '''Bootable'''||Yes
| |
| − | |-
| |
| − | |}
| |
| − |
| |
| − | == NAND flash bank ==
| |
| − |
| |
| − | On board main storage memory is a 8-bit wide NAND flash. By default it is connected to chip select. The following table reports the NAND flash specifications:
| |
| − |
| |
| − | {| class="wikitable" |
| |
| − | |-
| |
| − | | '''CPU connection'''||Static memory controller
| |
| − | |-
| |
| − | | '''Page size'''|| 512 byte, 2 kbyte or 4 kbyte
| |
| − | |-
| |
| − | | '''Size min'''||128 MB
| |
| − | |-
| |
| − | | '''Size max'''||2 GB
| |
| − | |-
| |
| − | | '''Width'''||8 bit
| |
| − | |-
| |
| − | | '''Chip select'''||NAND_CS0
| |
| − | |-
| |
| − | | '''Bootable'''||Yes
| |
| − | |-
| |
| − | |}
| |
| − |
| |
| − | == Memory map ==
| |
| − |
| |
| − | This section will be completed in a future version of this manual.
| |
| − |
| |
| − | == Power supply unit ==
| |
| − |
| |
| − | Bora, as the other Ultra Line CPU modules, embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters. For detailed information, please refer to Section 5.1.
| |
| − |
| |
| − | == CPU module connectors ==
| |
| − |
| |
| − | All interface signals Bora provides are routed through three 140 pin 0.6mm pitch stacking connectors (named J1, J2 and J3). The dedicated carrier board must mount the mating connectors and connect the desired peripheral interfaces according to Bora pinout specifications.
| |
| − |
| |
| − | = Mechanical specifications =
| |
| − |
| |
| − | This chapter describes the mechanical characteristics of the Bora module.
| |
| − |
| |
| − | == Board Layout ==
| |
| − |
| |
| − | The following figure shows the physical dimensions of the Bora module:
| |
| − |
| |
| − | [[File:Bora-top-quoted.png|800px|frameless|border]]
| |
| − |
| |
| − | The following figure highlights the maximum components' heights on Bora module:
| |
| − |
| |
| − | [[File:Bora-side-view-quoted.png|750px|frameless|border]]
| |
| − |
| |
| − | == Connectors ==
| |
| − |
| |
| − | The following figure shows the Diva connector layout:
| |
| − |
| |
| − | [[File:Bora-bottom-quoted.png|700px|frameless|border]]
| |
| − |
| |
| − | = Power, reset and control =
| |
| − |
| |
| − | == Power Supply Unit (PSU) and recommended power-up sequence==
| |
| − |
| |
| − |
| |
| − |
| |
| − | The recommended power-up sequence is:
| |
| − |
| |
| − | === PMIC ===
| |
| − |
| |
| − | == Reset scheme and voltage monitoring ==
| |
| − |
| |
| − | Some of these reset signals are accessible by carrier board circuitry as described below.
| |
| − | === EXT_PORSTn ===
| |
| − | === PORSTn_OUT ===
| |
| − | === WARMRSTn ===
| |
| − | === RTC_PWRONRSTn ===
| |
| − | === JTAG_TRSTn ===
| |
| − | === PMIC_nRESPWRON ===
| |
| − | === MRSTn ===
| |
| − |
| |
| − |
| |
| − | == Boot Options ==
| |
| − |
| |
| − |
| |
| − | === Default boot configuration ===
| |
| − |
| |
| − |
| |
| − | === Boot sequence customization ===
| |
| − |
| |
| − |
| |
| − |
| |
| − | == Clock scheme ==
| |
| − |
| |
| − |
| |
| − |
| |
| − | == Recovery ==
| |
| − |
| |
| − |
| |
| − | === JTAG recovery ===
| |
| − |
| |
| − |
| |
| − | === SD/MMC recovery ===
| |
| − |
| |
| − | == Multiplexing ==
| |
| − |
| |
| − | == RTC ==
| |
| − |
| |
| − | == Watchdog ==
| |
| − |
| |
| − |
| |
| − | = Pinout table =
| |
| − |
| |
| − | This chapter contains the pinout description of the connectors of the Bora module.
| |
| − |
| |
| − | = Peripheral interfaces =
| |
| − |
| |
| − |
| |
| − | = Operational Characteristics =
| |
| − |
| |
| − | == Maximum ratings ==
| |
| − |
| |
| − | {| class="wikitable"
| |
| − | |-
| |
| − | !Parameter
| |
| − | !Min
| |
| − | !Typ
| |
| − | !Max
| |
| − | !Unit
| |
| − | |-
| |
| − | |Main power supply voltage
| |
| − | |
| |
| − | |
| |
| − | |
| |
| − | |V
| |
| − | |-
| |
| − | |}
| |
| − |
| |
| − | == Recommended ratings ==
| |
| − |
| |
| − | {| class="wikitable"
| |
| − | |-
| |
| − | !Parameter
| |
| − | !Min
| |
| − | !Typ
| |
| − | !Max
| |
| − | !Unit
| |
| − | |-
| |
| − | |Main power supply voltage
| |
| − | |
| |
| − | |
| |
| − | |
| |
| − | |V
| |
| − | |-
| |
| − | |}
| |
| − |
| |
| − | == Power consumption ==
| |
| − |
| |
| − | == Heat dissipation ==
| |
| − |
| |
| − | This section will be completed in a future version of this manual.
| |
| − |
| |
| − | = Application notes =
| |
| − |
| |
| − | Please refer to the following documents available on Dave Developers Wiki:
| |
| − |
| |
| − | * [[Carrier_board_design_guidelines_%28SOM%29]]
| |
| − | * [[Integration_guide_%28Bora%29]]
| |
GET A QUOTE
ONLINE HELPDESK
