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==== Option 1 ====
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=== Pin Mux Option ===
SPI signals are available at different Naon pins. Please note that the NaonEVB-Mid carrier board provides the SPI1 and SPI3 signals at the J21 connector, so the configuration described below is dedicated to the NaonEVB-Mid board.
The following is the pin multiplexing configuration can be used:
{|class="wikitable" style="text-align:right"
!Signal
|}
=== U-Boot patches patch ===
{{ImportantMessage|text=The patches below applies to NELK 4.0.0 and above U-Boot source tree.}}
The files <code>arch/arm/mach-omap2/board-diva.c</code> and <code>arch/armdave/mach-omap2naon/diva_pinmux_tablepinmux_evb_mid.h</code> must be modified according to the following patchespatch:
<diff>
diff --git a/board/dave/naon/pinmux_evb_mid.h b/board/dave/naon/pinmux_evb_mid.h
index ae21ca3..df3783f 100644
--- a/board/dave/naon/pinmux_evb_mid.h
+++ b/board/dave/naon/pinmux_evb_mid.h
@@ -45,7 +45,7 @@ MUX_VAL(PINCNTL3, (IEN | IPU | FCN1 )) /* SD1_DAT[0] */\
MUX_VAL(PINCNTL4, (IEN | IPU | FCN1 )) /* SD1_DAT[1]_SDIRQ */\
MUX_VAL(PINCNTL5, (IEN | IPU | FCN1 )) /* SD1_DAT[2]_SDRW */\
MUX_VAL(PINCNTL6, (IEN | IPU | FCN1 )) /* SD1_DAT[3] */\
-MUX_VAL(PINCNTL7, (IEN | IPU | DISABLED )) /* safe_mode */\
+MUX_VAL(PINCNTL7, (IEN | IPU | FCN2 )) /* SPI[1]_SCS[1] */\
MUX_VAL(PINCNTL8, (IEN | IPU | FCN1 )) /* SD0_CLK */\
MUX_VAL(PINCNTL9, (IEN | IPU | FCN1 )) /* SD0_CMD */\
MUX_VAL(PINCNTL10, (IEN | IPU | FCN1 )) /* SD0_DAT[0] */\
@@ -258,10 +258,10 @@ MUX_VAL(PINCNTL218, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL219, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL220, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL221, (IEN | IPD | DISABLED )) /* safe_mode */\
-MUX_VAL(PINCNTL222, (IEN | IPD | DISABLED )) /* safe_mode */\
-MUX_VAL(PINCNTL223, (IEN | IPD | DISABLED )) /* safe_mode */\
-MUX_VAL(PINCNTL224, (IEN | IPD | DISABLED )) /* safe_mode */\
-MUX_VAL(PINCNTL225, (IEN | IPD | DISABLED )) /* safe_mode */\
+MUX_VAL(PINCNTL222, (IEN | IPU | FCN6 )) /* SPI[3]_SCS[1] */\
+MUX_VAL(PINCNTL223, (IEN | DIS | FCN6 )) /* SPI[3]_SCLK_MUX1 */\
+MUX_VAL(PINCNTL224, (IEN | DIS | FCN6 )) /* SPI[3]_D[1]_MUX1 */\
+MUX_VAL(PINCNTL225, (IEN | DIS | FCN6 )) /* SPI[3]_D[0]_MUX1 */\
MUX_VAL(PINCNTL226, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL227, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL228, (IEN | IPU | FCN7 )) /* I2C[2]_SCL_MUX2 */\
</diff>
=== Linux kernel patches patch ===
{{ImportantMessage|text=The patches below applies to NELK 4.0.0 and above Linux source tree.}}
The files <code>arch/arm/mach-omap2/board-divanaon.c</code> and <code>archdrivers/armspi/mach-omap2/diva_pinmux_tableomap2_mcspi.hc</code> must be modified according to the following patchespatch:
<diff>
diff --git a/arch/arm/mach-omap2/board-naon.c b/arch/arm/mach-omap2/board-naon.c
index 683af8e..e9d5023 100644
--- a/arch/arm/mach-omap2/board-naon.c
+++ b/arch/arm/mach-omap2/board-naon.c
@@ -794,6 +794,21 @@ struct spi_board_info __initdata naon_spi_slave_info[] = {
.chip_select = 0,
},
#endif
+
+ {
+ .modalias = "spidev",
+ .mode=SPI_MODE_0,
+ .max_speed_hz = 2000000, /* max spiclock (SCK) speed in HZ */
+ .bus_num = 2,
+ .chip_select = 1,
+ },
+ {
+ .modalias = "spidev",
+ .mode=SPI_MODE_0,
+ .max_speed_hz = 2000000, /* max spiclock (SCK) speed in HZ */
+ .bus_num = 4,
+ .chip_select = 1,
+ },
};
void __init naon_spi_init(void)
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index 06f586e..848a8e7 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -1182,7 +1182,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
case 4:
rxdma_id = spi4_rxdma_id;
txdma_id = spi4_txdma_id;
- num_chipselect = 1;
+ num_chipselect = 2;
break;
#endif
default:
</diff>
Please note that SPI bus_num values to be used into the naon_spi_slave_info are:
* SPI1: .bus_num = 2
* SPI3: .bus_num = 4
The kernel must be rebuilt to make these modifications effective.