Difference between revisions of "ETRA SOM/ETRA Hardware/Power and Reset/System boot"
| Line 28: | Line 28: | ||
* once it is satisfied, it executes the boot code | * once it is satisfied, it executes the boot code | ||
| − | == Boot options == | + | === Boot options === |
The default primary boot device is internally set by pull-up or pull-down resistors according to the Boot Mode fileld of the ordering code. | The default primary boot device is internally set by pull-up or pull-down resistors according to the Boot Mode fileld of the ordering code. | ||
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System boot[edit | edit source]
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:
- determines whether the boot is secure or non-secure
- performs some initialization of the system and clean-ups
- reads the OTP settings
- reads the mode pins to determine the primary boot device
- once it is satisfied, it executes the boot code
Boot options[edit | edit source]
The default primary boot device is internally set by pull-up or pull-down resistors according to the Boot Mode fileld of the ordering code.
The BOOT_MODEx signals are also present on the SoM connector to override the primary boot device.
The following table shows all the available options:
| BOOT_MODE2 | BOOT_MODE1 | BOOT_MODE0 | PRIMARY BOOT DEVICE |
| 0 | 0 | 0 | UART and USB |
| 0 | 0 | 1 | Serial NOR on QUADSPI |
| 0 | 1 | 0 | eMMC on SDMMC2 |
| 0 | 1 | 1 | SLC NAND on FMC |
| 1 | 0 | 0 | no boot (for debug access) |
| 1 | 0 | 1 | SD card on SDMMC1 |
| 1 | 1 | 0 | UART and USB |
| 1 | 1 | 1 | Serial NAND on QUADSPI |
Use 1k resistors either to VDD or DGND to drive externally the BOOT_MODEx signals.
On board OTP[edit | edit source]
The reading of BOOT_MODEx pins can be disabled by OTP configuration, in this case the OTP settings are used by the ROM code to determine the boot device.
Boot sources can be individually disabled by the OTP settings.
