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'''NOTE:''' the FDCAN1 pins are shared with touchscreen I2C interface and are not available when using I2C5.
 
See the [[ETRA SOM/ETRA Hardware/Peripherals/CAN|CAN]] page for more informations.
==== I2C5 ====
Configured by deafult for touchscreen I2C interface.
 
See the [[ETRA SOM/ETRA Hardware/Peripherals/I2C|I2C]] page for more informations.
==== SPI5 ====
'''NOTE:''' these pins are shared with UART7, cannot be used at the same time.
 
See the [[ETRA SOM/ETRA Hardware/Peripherals/SPI|SPI]] page for more informations.
==== UART7 ====
'''NOTE:''' these pins are shared with SPI5, cannot be used at the same time.
 
See the [[ETRA SOM/ETRA Hardware/Peripherals/USART|UART]] page for more informations.
==== SAI2 ====
''TBD''See the [[ETRA SOM/ETRA Hardware/Peripherals/Audio|Audio]] page for more informations.
==== LED driver ====
==== keyboard matrix ====
See '''NOTE:''' COLUMN[0:5] are not available by default as the pins are routed to the LED open collector outputs. Please send an e-mail to [[ETRA SOM/ETRA Hardware/Peripherals/IO expander|IO_expandermailto:helpdesk@dave.eu helpdesk@dave.eu]] page for more detailscustom configurations. (''TBD'')
'''NOTE:''' COLUMNSee the [0:5[ETRA SOM/ETRA Hardware/Peripherals/IO expander|IO_expander] are not available by default as the pins are routed to the LED open collector outputs] page for more informations.
==== Interface membrane ====
==== JTAG ====
See the [[ETRA SOM/ETRA Hardware/Power and Reset/JTAG|JTAG]] page for more informations.
 
==== System control ====
See the [[ETRA SOM/ETRA Hardware/Power and Reset/Reset scheme and control signals|reset scheme]] for more informations.
 
The system control signals are the following:
* system reset
** tie to ground for reset the system
* power key
** tie to ground for power up and down the system
* write protect for carrier eeprom
** tie to ground for write inside the carrier eeprom
** the first ''xxx'' byte of the eeprom are used to store the CB ConfigID, the corruption of these bytes prevents the system from boot.
* write protect for NAND
** this pin allow to prevent unwanted writes, tie to ground when the NAND are not to be written.
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[[Category:ETRA]]
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