Open main menu
DAVE Developer's Wiki
β
Search
Changes
← Older edit
Newer edit →
Design overview (AXEL ULite)
No change in size
,
08:52, 19 July 2016
→
RAM memory bank
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
|-
| '''Size min'''||
512
256
MB
|-
| '''Size max'''||2 GB
U0007
Bureaucrats
, dave_user,
Administrators
8,226
edits