Connectors, buttons and switches (SBC Lynx)

Info Box Applies to SBC Lynx

SBC Lynx is extremely flexible in terms of hardware configurations. This document details connector's pinout of common SBC Lynx models. For more information about models not documented here, please contact Sales department.

Introduction

This document details connectors, buttons and switches that equip SBC Lynx board. Please note that not all of them are available on all models.

The following table lists connectors, buttons and switches available on SBC Lynx.

Reference	Function	Type	Part number	Notes
J35	Power supply	2-pin header, male pins, Shrouded 0.200in pitch	Phoenix 1757242 MSTBA 2.5/2-G-5.08	[1]
JP1	Power supply	2.1mm ID, 5.5mm OD	CUI PJ-002A	[1]
J42	System console	TTL 3.3V UART 4-pin Header, Male 0.100in pitch
J50	System ONOFF / Power Reset	4-pin Header, Male 0.100in pitch
J16	10/100 Base-T Ethernet port	RJ-45	Wurth 74990112116A
J43	microSD slot	push-pull slot	Molex 47571-0001
J47	USB OTG	USB type micro AB	Hirose ZX62D-AB-5P8
J55	USB OTG	USB type micro B vertical	Molex 105133-0011
J48	USB host	USB type A Right Angle	Wurth WE-614 004 134 726
J34	MPUART0 ( RS232 / RS485 / RS422 )	DB9 90° Connector Male or Female		[2]
J38	MPUART0 ( RS232 / RS485 / RS422 )	3-pins Header, Male Pins, Shrouded 0.200in pitch	Phoenix 1755749 MSTBVA2.5/3-G5.08	[2]
J21	MPUART1 ( RS232 / RS485 / RS422 / CAN)	DB9 90° Connector Male or Female		[3]
J39	MPUART1 ( RS232 / RS485 / RS422 / CAN)	3-pins Header, Male Pins, Shrouded 0.200in pitch	Phoenix 1755749 MSTBVA2.5/3-G5.08	[3]
J40	CAN	3-pins Header, Male Pins, Shrouded 0.200in pitch	Phoenix 1755749 MSTBVA2.5/3-G5.08
J46	DAVE DWM WiFi/Bluetooth module interface	30-pins SlimStack™ Receptacle 0.50mm pitch	Molex 52991-0308
J45/J52	ONE Piece	30x2 pins, pitch 1.00mm One Piece Interface	Samtec FSI-130-03-G-D-M-K-TR
J53/J54	Mezzanine Board Connectors	10-pins Header 0.100inch
S11	Reset button
S12	Boot Mode / UART Termination resistors	8-positions DIP Switches	WE-416131160808
J49	JTAG	1.27mm-pitch 5x2 header

[1] These parts are mutually exclusive.

[2] These parts are mutually exclusive.

[3] These parts are mutually exclusive.

The following image shows where connectors, buttons and switches are located.

Connectors and switches layout

Connectors

Power supply connector (J35 / JP1)

J35

Pin #	Name	Description	Notes
1	GND	Ground
2	VIN	Positive supply voltage	Range: 5 ÷ 24 V

JP1

Pin #	Name	Description	Notes
1	VIN	Positive supply voltage	Range: 5 ÷ 24 V
2	GND	Ground
3	GND	Ground

Serial console (J42)

System console is by default routed to this interface. This is typically used during the development stage.

Pin #	Processor ball	Name	Default function	Default type	Notes
1	K14	UART1_TX_DATA	UART1 transmit line	Output, 3.3V LVTTL
2	K16	UART1_RX_DATA	UART1 receive line	Input, 3.3V LVTTL
3	-	IO_3.3V	UART1 I/O voltage reference	3.3V
4	-	DGND	Ground	0V

Ethernet connector (J16)

J16 is a standard RJ45 10/100BaseT Ethernet connector - incorporating magnetics - connected to the Ethernet controller and PHY.

J16 integrates a status LED providing connection information:

• LED on: link established
• LED blinking: activity.

The following table describes the interface signals:

Pin #	Name	Function	Notes
1	TDP	TX+
2	TCT	TX center tap
3	TDN	TX-
4	RDP	RX+
5	RCT	RX center tap
6	RDN	RX-
7	NC	Not connected
8	CHS_GND	Chassis ground	See also this page

microSD slot (J43)

J43 is a push-pull microSD card slot connected to uSDHC1 port of MX6UL processor.

The following table details the pinout:

Pin #	Name	Function	Notes
1	DAT2	Data line #2
2	DAT3	Data line #3
3	CMD	Command
4	VDD	3.3V
5	CLK	Clock
6	Vss	Ground
7	DAT0	Data line #0
8	DAT1	Data line #2	See also this page
9	SD_SHIELD	Metal case	See also this page
10	SD_SHIELD	Metal case	See also this page
11	SD_SHIELD	Metal case	See also this page
12	Vss	Ground
13	CD	Card detect	Pulled-up to 3.3V

USB host port (J48)

J48 is a standard USB Type A right angle connector connected to the MX6UL USB_OTG2 port signals. The following table reports the connector's pinout:

Pin #	iMX6UL ball#	Pin name	Function	Notes
1	U12	USB_HOST_VBUS	5V	up to 470mA
2	T13	USB_OTG2_DN	USB2 Data -	-
3	U13	USB_OTG2_DP	USB2 Data +	-
4	-	DGND	Ground	-
5, 6, 7, 8	-	PCB_GND_RNG	Connector Shield	-

USB OTG port (J47)

J47 is a standard USB Type micro AB connector connected to the MX6UL USB_OTG1 port signals. The following table reports the connector's pinout:

Pin #	iMX6UL ball#	Pin name	Function	Notes
1	T12	USB_OTG_VBUS	Reference voltage from ext or 5V in HOST mode	Up to 75mA (HOST)
2	T15	USB_OTG1_DN	USB1 OTG Data -	-
3	U15	USB_OTG1_DP	USB1 OTG Data +	-
4	K13	USB_OTG1_ID	OTG ID	-
5	-	USB_GND	Ground	-
6, 7, 8, 9	-	PCB_GND_RNG	Connector Shield	-

Mezzanine board connectors (J53/J54)

J53 and J54 are 10x1-pin 2.54mm-pitch vertical headers for optional mezzanine expansion boards. These boards can be implemented to extend SBC Lynx functionalities and/or interfaces.

It is worth remembering that some of the mezzanine board connectors signals are reserved for internal use or shared with One Piece connector (J45 / J52). Please contact Sales department for more information.

The following tables report the connectors' pinout.

J53

Pin #	Processor ball	Name	Default function	Type	Voltage domain	Notes
1	J16	UART2_RX_DATA	UART2_RX	I/O	IO_3.3V	[1], [2]
2	H14	UART2_nRTS	UART2_RTS	I/O	IO_3.3V	[1], [2]
3	J17	UART2_TX_DATA	UART2_TX	I/O	IO_3.3V	[1], [2]
4	J15	UART2_nCTS	UART2_CTS	I/O	IO_3.3V	[1], [2]
5	F17	UART5_TX_DATA	UART5_TX / I2C2_SCL	I/O	IO_3.3V
6	G13	UART5_RX_DATA	UART5_RX / I2C2_SDA	I/O	IO_3.3V
7	D14	MEZZANINE_GP0	GPIO / PWM	I/O	IO_3.3V	[3], [4]
8	A14	MEZZANINE_GP1	GPIO	I/O	IO_3.3V	[3], [4]
9	B16	MEZZANINE_GP2	GPIO	I/O	IO_3.3V	[3], [4]
10		DGND	Ground	-	-

[1] This group of signals can be configured to implement this alternative functions:

• I2C4
• CAN2
• SPI3 (CS0).

[2] Not available is DWM WIFI present

[3] This signal acts as bootstrap configuration flag and may be pulled up or down with 10kOhm resistor. Do not drive these signals until CPU_PORn is deasserted. For more details please refer to this section.

[4] Not available if 24-bit LCD interface is used.

J54

Pin #	Processor ball	Name	Default function	Type	Voltage domain	Notes
1	-	VIN	-	Power	-	Power supply of VIN_5_24V domain
2	-	PMIC_5V	-	Power	-	Power supply of AUX_5V domain
3	-	3V3_AUX	-	Power	-	Power supply of AUX_3.3V domain
4	-	VDDA_ADC_3P3	-	Power	-	Power supply of ADC_3.3V domain [5]
5	L15	GPIO1_IO01	GPIO / ADC	I/O	ADC_3.3V	12-bit ADC
6	L14	GPIO1_IO02	GPIO / ADC	I/O	ADC_3.3V	12-bit ADC
7	L17	GPIO1_IO03	GPIO / ADC	I/O	ADC_3.3V	12-bit ADC
8	M16	GPIO1_IO04	GPIO / ADC	I/O	ADC_3.3V	12-bit ADC
9	M17	GPIO1_IO05	GPIO / ADC	I/O	ADC_3.3V	12-bit ADC
10	-	DGND	Ground	-	-

[5] To be used for voltage reference only.

Handling bootstrap signals

MEZZANINE_GP0, MEZZANINE_GP1 and MEZZANINE_GP2 are connected to LCD_DATA19, LCD_DATA22 and LCD_DATA23 respectively. As such, they act as bootstrap configuration signals as well. They can be used by application software freely and the can be connected to user's application circuitry. However, any electrical interference during the processor reset cycle must be avoided.

There are different solutions to comply with this requirement. The following image shows a concept solution for this problem.

Concept solution to use bootstrap signals

During the processor reset cycle, MEZZANINE_GP0, MEZZANINE_GP1 and MEZZANINE_GP2 [1] are isolated from user's application logic by a bus switch that is in high-impedence state. Bus switch's BUS_SW_OE_n signal is connected to another processor's GPIO (GPIO1_IO01 in the example). Before configuring and using MEZZANINE_GPx signals, application software needs to:

• initialize GPIO1_IO01 as GPIO ouput
• set GPIO1_IO01 to logic level 0 in order to enable the switch.

[1] The same considerations apply to all of LCD_DATAx signals that are routed to J45/J52 connectors.

One-piece interfaces (J45 / J52)

J45 and J52 are two interfaces designed to be populated with Samtec 1.00mm-pitch 30x2-pin FSI One-piece connectors. The peculiarity of this kind of connectors if the fact that they

• allow to mate two boards by using one connector only
• the connector is mounted on one of the two boards indifferently.

J45 and J52 that share the same pinout, however they are intended to be used for different goals. J45 - that is placed on the top side of the PCB - is generally used to mate an optional expansion board. J52 - that is placed on the bottom side of the PCB - is conceived to mate SBC Lynx to a larger carrier board. In this case SBC Lynx can be thought as as an add-on for another board and can be powered via J52 interface itself.

It is worth remembering that some of the J45/J52 signals are reserved for internal use or shared with mezzanine board connectors. Please contact DAVE Embedded Systems' Sales department to get more information.

The following tables reports the interfaces' pinout:

Pin #	iMX6UL ball#	Pin name	Function	Notes
1	-	DGND	Ground	-
3	A8	LCD_CLK	LCD / UART4_TX	-
5	B8	LCD_DATA_EN	LCD / UART4_RX	-
7	D9	LCD_HSYNC	LCD / UART4_CTSn	-
9	C9	LCD_VSYNC	LCD / UART4_RTSn	-
11	E9	LCD_RESET	LCD RESET	-
13	-	DGND	Ground	-
15	B9	LCD_DATA00	LCD_DATA00	-
17	A9	LCD_DATA01	LCD_DATA01	-
19	E10	LCD_DATA02	LCD_DATA02	-
21	D10	LCD_DATA03	LCD_DATA03	-
23	C10	LCD_DATA04	LCD_DATA04	-
25	B10	LCD_DATA05	LCD_DATA05	-
27	A10	LCD_DATA06	LCD_DATA06 / UART7_CTSn	-
29	-	DGND	Ground	-
31	D11	LCD_DATA07	LCD_DATA07 / UART7_RTSn	-
33	B11	LCD_DATA08	LCD_DATA08 / CAN1_TX	-
35	A11	LCD_DATA09	LCD_DATA09 / CAN1_RX	-
37	E12	LCD_DATA10	LCD_DATA10 / CAN2_TX / SAI3_RX_SYNC	-
39	D12	LCD_DATA11	LCD_DATA11 / CAN2_RX / SAI3_RX_BCLK	-
41	C12	LCD_DATA12	LCD_DATA12 / SAI3_TX_SYNC	-
43	-	DGND	Ground	-
45	T13	USB_OTG2_EXP_DN	USB_OTG2_DN	-
47	U13	USB_OTG2_EXP_DP	USB_OTG2_DP	-
49	U12	USB_OTG2_VBUS	USB_OTG2_VBUS	-
51	K15	UART1_nCTS	GPIO	-
53	-	CPU_PORn	Reset	-
55	-	3V3_AUX	3V3 PMIC regulator	< 1A – shared with J54.3
57	-	VIN	Power Supply	-
59	-	DGND	Ground	-
2	B12	LCD_DATA13	LCD_DATA13 / SAI3_TX_BCLK / SDHC2_RST	-
4	A12	LCD_DATA14	LCD_DATA14 / SAI3_RX_DATA / SDHC2_DATA4	-
6	D13	LCD_DATA15	LCD_DATA15 / SAI3_TX_DATA / SDHC2_DATA5	-
8	C13	LCD_DATA16	LCD_DATA16 / UART7_TX / SDHC2_DATA6	-
10	B13	LCD_DATA17	LCD_DATA17 / UART7_RX / SDHC2_DATA7	-
12	A13	LCD_DATA18	LCD_DATA18 / PWM5 / SDHC2_CMD	-
14	D14	LCD_DATA19	LCD_DATA19 / PWM6 / SDHC2_CLK	-
16	C14	LCD_DATA20	LCD_DATA20 / SPI1_SCLK / SDHC2_DATA0	SPI1 is available only if NOR is not mounted
18	B14	LCD_DATA21	LCD_DATA21 / SPI1_SS0 / SDHC2_DATA1	SPI1 is available only if NOR is not mounted
20	A14	LCD_DATA22	LCD_DATA20 / SPI1_MOSI / SDHC2_DATA2	SPI1 is available only if NOR is not mounted
22	B16	LCD_DATA23	LCD_DATA20 / SPI1_MISO / SDHC2_DATA3	SPI1 is available only if NOR is not mounted
24	-	DGND	Ground	-
26	C17	ENET2_RX_DATA0	ENET2_RX_DATA0 / UART6_TX / I2C3_SCL /	Default: internally used as USB OTG power
28	C16	ENET2_RX_DATA1	ENET2_RX_DATA1 / UART6_RX / I2C3_SDA	Default: internally used as USB OTG over current
30	B17	ENET2_RX_EN	ENET2_RX_EN / UART7_TX / I2C4_SCL /	-
32	A15	ENET2_TX_DATA0	ENET2_TX_DATA0 / UART7_RX / I2C4_SDA /	-
34	A16	ENET2_TX_DATA1	ENET2_TX_DATA1 / UART8_TX / SPI4_SCLK	Default: internally used as USB HOST pwr
36	B15	ENET2_TX_EN	ENET2_TX_EN / UART8_RX / SPI4_MOSI	Default: internally used as USB HOST over current
38	D17	ENET2_TX_CLK	ENET2_TX_CLK / UART8_CTS / SPI4_MISO / USB_OTG2_ID	Default: internally used as UART8_CTS on MPUART0
40	D16	ENET2_RX_ER	ENET2_RX_ER / UART8_RTS / SPI4_SS0	Default: internally used as UART8_RTS on MPUART0
42	-	DGND	Ground	-
44	L16	GPIO1_IO07	GPIO / ENET2_MDIO / ADC	Internally used as ENET1_MDIO
46	K17	GPIO1_IO06	GPIO / ENET2_MDC / ADC	Internally used as ENET1_MDC
48	M17	GPIO1_IO05	GPIO / UART5_RX / ADC	-
50	M16	GPIO1_IO04	GPIO / UART5_TX / TSCX+ / ADC	-
52	L17	GPIO1_IO03	GPIO / TSCX- / ADC	-
54	L14	GPIO1_IO02	GPIO / TSCY+ / ADC	-
56	L15	GPIO1_IO01	GPIO / TSCY- / ADC	-
58	K13	GPIO1_IO00	GPIO / TSC_WIPER / ADC	Default: internally used as USB OTG ID
60	-	DGND	Ground	-

DWM WiFi/Bluetooth module Connector (J46)

J46 is a 30-pins SlimStack™ Receptacle 0.50mm pitch that allows to connect to DAVE Embedded Systems' DWM Wifi/BT module. The following table reports the connector's pinout:

Pin #	iMX6UL ball#	Pin name	Function	Notes
1,2	-	PMIC_5V	5V DWM Module Power Supply	Up to 500mA shared with USB Host / OTG Mezzanine Board Connector
3,4	-	3V3_IO	DWM Level Shifter Power Supply	-
5, 6, 9, 10, 19	-	DGND	Ground	-
12, 14, 16, 18, 20, 22	-	NC	-	-
7	F3	WIFI_CMD	WIFI_CMD / uSDHC2_CMD	-
8	F2	WIFI_CLK	WIFI_CLK / uSDHC2_CLK	-
11	E4	WIFI_DATA0	WIFI_DATA0 / uSDHC2_DATA0	-
13	E3	WIFI_DATA1	WIFI_DATA1 / uSDHC2_DATA1	-
15	E2	WIFI_DATA2	WIFI_DATA2 / uSDHC2_DATA2	-
17	E1	WIFI_DATA3	WIFI_DATA3 / uSDHC2_DATA3	-
21	J16	BT_UART_RX	BT_UART_RX / UART2_RX_DATA	-
23	H14	BT_UART_CTS	BT_UART_CTS / UART2_nRTS	-
24	R9	TIWI_BT_F5	TIWI_BT_F5 / DWM_BT_F5	-
25	J17	BT_UART_TX	BT_UART_TX / UART2_TX_DATA	-
26	R10	TIWI_BT_F2	TIWI_BT_F2 / DWM_BT_F2	-
27	J15	BT_UART_RTS	BT_UART_RTS / UART2_nCTS	-
28	P10	TIWI_IRQ	TIWI_IRQ / 3V3_WLAN_IRQ	-
29	N10	TIWI_BT_EN	TIWI_BT_EN / 3V3_BT_EN	Internally used for CB_Configid
30	P9	TIWI_EN	TIWI_EN / 3V3_WLAN_EN	-

Multiprotocol UARTs and CAN interfaces

There are two UART multiprotocol ports (RS232 / RS485 / RS422) and one CAN interface available on SBC LYNX. The two UART interfaces are named as MPUART0 (MX6UL UART8) and MPUART1 (MX6UL UART3) and are routed through two dual protocol ISL3330 transceivers. CAN interface is connected to MX6UL Flexcan1 controller through an SN65HVD23x CAN transceiver.

The following table describes the MPUART0 signals to the ISL3330 transceiver:

Pin #	iMX6UL ball#	Pin name	Function	Notes
8	-	MPUART0_485/232#	Protocol Selection	Fixed with Pull UP/DOWN resistor
9	N9	MPUART0_DEN	Driver Output Enable	-
12	R6	MPUART0_RXEN	Receiver Output Enable	-
13	F5	MPUART0_ON	RS232 Charge Pump Enable	-
14	D16	MPUART0_nRTS	-	-
15	C14	MPUART0_TX_DATA	-	-
16	D17	MPUART0_nCTS	-	-
17	B14	MPUART0_RX_DATA	-	-

The following table describes the MPUART1 signals to the ISL3330 transceiver:

Pin #	iMX6UL ball#	Pin name	Function	Notes
8	-	MPUART1_485/232#	Protocol Selection	Fixed with Pull UP/DOWN resistor
9	N8	MPUART1_DEN	Driver Output Enable	-
12	N11	MPUART1_RXEN	Receiver Output Enable	-
13	E5	MPUART1_ON	RS232 Charge Pump Enable	-
14	G14	MPUART1_nRTS	-	-
15	H17	MPUART1_TX_DATA	-	-
16	H15	MPUART1_nCTS	-	-
17	H16	MPUART1_RX_DATA	-	-

The following table describes the CAN to the SN65HVD23x transceiver:

Pin #	iMX6UL ball#	Pin name	Function	Notes
1	H15	CAN_D	Transmit data input	Alternative to MPUART1_nCTS
4	G14	CAN_R	Receive data output	Alternative to MPUART1_nRTS

CPU ONOFF / Power Reset connector (J50)

J50 is a 0.100in-pitch 4-pin male header that allows connection to signals needed to implement advanced power modes.

The following table reports the connector pinout:

Pin #	Processor ball	Name	Default function	Default type	Notes
1	K14	UART1_TX_DATA	UART1 transmit line	Output, 3.3V LVTTL
2	K16	UART1_RX_DATA	UART1 receive line	Input, 3.3V LVTTL
3	-	IO_3.3V	UART1 I/O voltage reference	3.3V
4	-	DGND	Ground	0V

For more details please refer to this page.

Buttons

Reset button (S11)

When pressed, a full power-up cycle is triggered, resulting in a complete hardware reset of the system.

Switches

Boot mode (S12)

Please refer to this page.

Multiprotocol UARTs/CAN settings (S12)

Please refer to TBD.