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→Mezzanine board connectors (J53/J54)
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[1] Pulled '''This signal acts as bootstrap configuration flag''' and '''may be pulled up or down for boot configurationwith 10kOhm resistor'''. '''Do not drive these signals until CPU_PORn is deasserted'''. For more details please refer to [[Handling bootstrap signals|this section]].
[2] Not available if 24-bit LCD interface is used.
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[3] '''To be used for voltage reference only'''.
====Handling bootstrap signals====
MEZZANINE_GP0, MEZZANINE_GP1 and MEZZANINE_GP2 are connected to LCD_DATA19, LCD_DATA22 and LCD_DATA23 respectively. As such, they act as bootstrap configuration signals as well. They can be used by application software freely and the can be connected to user's application circuitry. However, '''any electrical interference during the processor reset cycle must be avoided'''.
There are different solutions to comply with this requirement. The following image shows a concept solution for this problem.
[[File:TBD.png|thumb|center|600px|caption]]
During the processor reset cycle, MEZZANINE_GP0, MEZZANINE_GP1 and MEZZANINE_GP2 [1] are isolated from user's application logic by a bus switch. Bus switch's BUS_SW_OE_n signal is connetcted to another processor's GPIO (GPIO1_IO01 in the example). Before configuring and using MEZZANINE_GPx signals, application software needs to:
*initialize GPIO1_IO01 as GPIO ouput
*set GPIO1_IO01 to logic level 0 in order to enable the switch.
[1] The same considerations apply to all of the remaining LCD_DATAx signals that are routed to J45/J52 connectors.
===One-piece interfaces (J45 / J52)===