Difference between revisions of "Connectors, buttons and switches (SBC Lynx)"
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=Introduction= | =Introduction= | ||
This document details connectors, buttons and switches that equip SBC Lynx board. '''Please note that not all of them are available on all models'''. | This document details connectors, buttons and switches that equip SBC Lynx board. '''Please note that not all of them are available on all models'''. | ||
| + | |||
| + | For some connectors, information related to the internal connections to the processor are provided. In these cases, 14x14mm-package processor's balls references are indicated. | ||
The following table lists connectors, buttons and switches available on SBC Lynx. | The following table lists connectors, buttons and switches available on SBC Lynx. | ||
| Line 143: | Line 145: | ||
|4||-||DGND||Ground||-||-||- | |4||-||DGND||Ground||-||-||- | ||
|} | |} | ||
| + | |||
| + | J42 connector is compatible with [http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232RG_CABLES.pdf FTDI TTL-232RG-VIP-WE cable]. To connect it, please use this wiring: | ||
| + | *J42.1: yellow wire | ||
| + | *J42.2: orange wire | ||
| + | *J42.3: red wire | ||
| + | *J42.4: black wire | ||
==Ethernet connector (J16)== | ==Ethernet connector (J16)== | ||
| Line 150: | Line 158: | ||
J16 is a standard RJ45 10/100BaseT Ethernet connector - incorporating magnetics - connected to the Ethernet controller and PHY. | J16 is a standard RJ45 10/100BaseT Ethernet connector - incorporating magnetics - connected to the Ethernet controller and PHY. | ||
| − | J16 integrates a status LED providing connection information: | + | J16 integrates a green status LED providing connection information: |
*LED on: link established | *LED on: link established | ||
*LED blinking: activity. | *LED blinking: activity. | ||
| Line 276: | Line 284: | ||
==Mezzanine board connectors (J53/J54)== | ==Mezzanine board connectors (J53/J54)== | ||
| − | [[File:SBC Lynx-J53-J54.png|thumb|center|300px|J53-J54]] | + | {| class="wikitable" | width="100%" |
| + | | [[File:SBC Lynx-J53-J54.png|thumb|center|300px|J53-J54]] | ||
| + | | [[File:SBCLYNX_ADDON_XUAL Mounted.JPG|thumb|center|300px|Example of mezzanine usability]] | ||
| + | |} | ||
J53 and J54 are 10x1-pin 2.54mm-pitch vertical headers for optional mezzanine expansion boards. These boards can be implemented to extend SBC Lynx functionalities and/or interfaces. | J53 and J54 are 10x1-pin 2.54mm-pitch vertical headers for optional mezzanine expansion boards. These boards can be implemented to extend SBC Lynx functionalities and/or interfaces. | ||
| Line 360: | Line 371: | ||
[5] '''To be used for voltage reference only'''. | [5] '''To be used for voltage reference only'''. | ||
===Handling bootstrap signals=== | ===Handling bootstrap signals=== | ||
| − | MEZZANINE_GP0, MEZZANINE_GP1 and MEZZANINE_GP2 are connected to LCD_DATA19, LCD_DATA22 and LCD_DATA23 respectively. As such, they act as bootstrap configuration signals as well. They can be used by application software freely and | + | MEZZANINE_GP0, MEZZANINE_GP1 and MEZZANINE_GP2 are connected to LCD_DATA19, LCD_DATA22 and LCD_DATA23 respectively. As such, they act as bootstrap configuration signals as well. They can be used by application software freely and they can be connected to user's application circuitry. However, '''any electrical interference during the processor reset cycle must be avoided'''. |
There are different solutions to comply with this requirement. The following image shows a concept solution for this problem. | There are different solutions to comply with this requirement. The following image shows a concept solution for this problem. | ||
| Line 377: | Line 388: | ||
==One-piece interfaces (J45 / J52)== | ==One-piece interfaces (J45 / J52)== | ||
| − | [[File:SBC Lynx-J45-52.png|thumb|center|300px|J45 J52]] | + | |
| + | {| class="wikitable" | width="100%" | ||
| + | | [[File:SBC Lynx-J45-52.png|thumb|center|300px|J45]] | ||
| + | | [[File:XUAE-side-mount.png|thumb|center|300px|example of possible connections on J45]] | ||
| + | | [[File:Mech-design-XUAE-bottom.png|thumb|center|300px|J52]] | ||
| + | | [[File:SBC-Lynx-onepiece-bottom.png|thumb|center|300px|example of possible connections on J52]] | ||
| + | |} | ||
| + | |||
J45 and J52 are two interfaces designed to be populated with Samtec 1.00mm-pitch 30x2-pin FSI One-piece connectors. The peculiarity of this kind of connectors if the fact that they | J45 and J52 are two interfaces designed to be populated with Samtec 1.00mm-pitch 30x2-pin FSI One-piece connectors. The peculiarity of this kind of connectors if the fact that they | ||
| Line 414: | Line 432: | ||
| 13||-||DGND||Ground|| || ||- | | 13||-||DGND||Ground|| || ||- | ||
|- | |- | ||
| − | | 15||B9||LCD_DATA00|||| Output || IO_3.3V || | + | | 15||B9||LCD_DATA00|||| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 17||A9||LCD_DATA01|||| Output || IO_3.3V || | + | | 17||A9||LCD_DATA01|||| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 19||E10||LCD_DATA02|||| Output || IO_3.3V || | + | | 19||E10||LCD_DATA02|||| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 21||D10||LCD_DATA03|||| Output || IO_3.3V || | + | | 21||D10||LCD_DATA03|||| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 23||C10||LCD_DATA04|||| Output || IO_3.3V || | + | | 23||C10||LCD_DATA04|||| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 25||B10||LCD_DATA05|||| Output || IO_3.3V || | + | | 25||B10||LCD_DATA05|||| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 27||A10||LCD_DATA06||UART7_CTS_B|| Output || IO_3.3V || | + | | 27||A10||LCD_DATA06||UART7_CTS_B|| Output || IO_3.3V ||[3] |
|- | |- | ||
| 29||-||DGND||Ground|| || ||- | | 29||-||DGND||Ground|| || ||- | ||
|- | |- | ||
| − | | 31||D11||LCD_DATA07||UART7_RTS_B|| Output || IO_3.3V || | + | | 31||D11||LCD_DATA07||UART7_RTS_B|| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 33||B11||LCD_DATA08||FLEXCAN1_TX|| Output || IO_3.3V || | + | | 33||B11||LCD_DATA08||FLEXCAN1_TX|| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 35||A11||LCD_DATA09||FLEXCAN1_RX|| Output || IO_3.3V || | + | | 35||A11||LCD_DATA09||FLEXCAN1_RX|| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 37||E12||LCD_DATA10||FLEXCAN2_TX / SAI3_RX_SYNC|| Output || IO_3.3V || | + | | 37||E12||LCD_DATA10||FLEXCAN2_TX / SAI3_RX_SYNC|| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 39||D12||LCD_DATA11||FLEXCAN2_RX / SAI3_RX_BCLK|| Output || IO_3.3V || | + | | 39||D12||LCD_DATA11||FLEXCAN2_RX / SAI3_RX_BCLK|| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 41||C12||LCD_DATA12||SAI3_TX_SYNC|| Output || IO_3.3V || | + | | 41||C12||LCD_DATA12||SAI3_TX_SYNC|| Output || IO_3.3V ||[3] |
|- | |- | ||
| 43||-||DGND||Ground|| || ||- | | 43||-||DGND||Ground|| || ||- | ||
| Line 460: | Line 478: | ||
| 59||-||DGND||Ground|| || IO_3.3V ||- | | 59||-||DGND||Ground|| || IO_3.3V ||- | ||
|- | |- | ||
| − | | 2||B12||LCD_DATA13|| SAI3_TX_BCLK / USDHC2_RESET_B || Output || IO_3.3V || | + | | 2||B12||LCD_DATA13|| SAI3_TX_BCLK / USDHC2_RESET_B || Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 4||A12||LCD_DATA14|| SAI3_RX_DATA / USDHC2_DATA4 || Output || IO_3.3V || | + | | 4||A12||LCD_DATA14|| SAI3_RX_DATA / USDHC2_DATA4 || Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 6||D13||LCD_DATA15|| SAI3_TX_DATA / USDHC2_DATA5 || Output || IO_3.3V || | + | | 6||D13||LCD_DATA15|| SAI3_TX_DATA / USDHC2_DATA5 || Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 8||C13||LCD_DATA16|| UART7_TX / USDHC2_DATA6 || Output || IO_3.3V || | + | | 8||C13||LCD_DATA16|| UART7_TX / USDHC2_DATA6 || Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 10||B13||LCD_DATA17|| UART7_RX / USDHC2_DATA7 || Output || IO_3.3V || | + | | 10||B13||LCD_DATA17|| UART7_RX / USDHC2_DATA7 || Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 12||A13||LCD_DATA18|| PWM5_OUT / USDHC2_CMD|| Output || IO_3.3V || | + | | 12||A13||LCD_DATA18|| PWM5_OUT / USDHC2_CMD|| Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 14||D14||LCD_DATA19|| PWM6_OUT / USDHC2_CLK || Output || IO_3.3V || | + | | 14||D14||LCD_DATA19|| PWM6_OUT / USDHC2_CLK || Output || IO_3.3V ||[3] |
|- | |- | ||
| − | | 16||C14||LCD_DATA20|| ECSPI1_SCLK / USDHC2_DATA0 || Output || IO_3.3V ||SPI1 is available only if NOR is not mounted | + | | 16||C14||LCD_DATA20|| ECSPI1_SCLK / USDHC2_DATA0 || Output || IO_3.3V ||SPI1 is available only if NOR is not mounted, [3] |
|- | |- | ||
| − | | 18||B14||LCD_DATA21|| ECSPI1_SS0 / USDHC2_DATA1 || Output || IO_3.3V ||SPI1 is available only if NOR is not mounted | + | | 18||B14||LCD_DATA21|| ECSPI1_SS0 / USDHC2_DATA1 || Output || IO_3.3V ||SPI1 is available only if NOR is not mounted, [3] |
|- | |- | ||
| − | | 20||A14||LCD_DATA22|| ECSPI1_MOSI / USDHC2_DATA2 || Output || IO_3.3V ||SPI1 is available only if NOR is not mounted | + | | 20||A14||LCD_DATA22|| ECSPI1_MOSI / USDHC2_DATA2 || Output || IO_3.3V ||SPI1 is available only if NOR is not mounted, [3] |
|- | |- | ||
| − | | 22||B16||LCD_DATA23|| ECSPI1_MISO / USDHC2_DATA3|| Output || IO_3.3V ||SPI1 is available only if NOR is not mounted | + | | 22||B16||LCD_DATA23|| ECSPI1_MISO / USDHC2_DATA3|| Output || IO_3.3V ||SPI1 is available only if NOR is not mounted, [3] |
|- | |- | ||
| 24||-||DGND||Ground|| || ||- | | 24||-||DGND||Ground|| || ||- | ||
| Line 525: | Line 543: | ||
[2] This signal can be routed here instead of connector J48. Please refer to the [mailto:sales@dave.eu Sale Deparment] for more details. | [2] This signal can be routed here instead of connector J48. Please refer to the [mailto:sales@dave.eu Sale Deparment] for more details. | ||
| + | |||
| + | [3] LCD_DATAx signals act as bootstrap configuration pins as well. They can be used by application software freely and they can be connected to user's application circuitry. However, '''any electrical interference during the processor reset cycle must be avoided'''. Please see [[#Handling bootstrap signals|Handling bootstrap signals]] section for more details. | ||
==DWM WiFi/Bluetooth module connector (J46)== | ==DWM WiFi/Bluetooth module connector (J46)== | ||
| + | |||
| + | [[File:SBC Lynx-J46.png|thumb|center|300px|J46]] | ||
| + | |||
J46 is a 30-pins SlimStack™ Receptacle 0.50mm pitch that allows to connect to DAVE Embedded Systems' DWM Wifi/BT module. | J46 is a 30-pins SlimStack™ Receptacle 0.50mm pitch that allows to connect to DAVE Embedded Systems' DWM Wifi/BT module. | ||
The following table reports the connector's pinout: | The following table reports the connector's pinout: | ||
| Line 594: | Line 617: | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | ! rowspan="3" style="text-align: center; font-weight: bold;" | P/N | + | ! rowspan="3" style="text-align: center; font-weight: bold;" | P/N and image |
! colspan="5" style="text-align: center; font-weight: bold;" | MPUART0 | ! colspan="5" style="text-align: center; font-weight: bold;" | MPUART0 | ||
! colspan="5" style="text-align: center; font-weight: bold;" | MPUART1 | ! colspan="5" style="text-align: center; font-weight: bold;" | MPUART1 | ||
| Line 612: | Line 635: | ||
| style="text-align: center; font-weight: bold;" | Type | | style="text-align: center; font-weight: bold;" | Type | ||
|- | |- | ||
| − | | style="text-align: center;" | XUBx0xxxxx | + | | style="text-align: center;" | XUBx0xxxxx [[File:SBC Lynx-top.png|thumb|center|100px|XUBx0xxxxx ]] |
| style="text-align: center;" | J34 | | style="text-align: center;" | J34 | ||
| style="text-align: center;" | Right-angle male DB9 | | style="text-align: center;" | Right-angle male DB9 | ||
| style="text-align: center;" | UART8 | | style="text-align: center;" | UART8 | ||
| − | | style="text-align: center;" | | + | | style="text-align: center;" | See [[#RS232 on DB9 (J34, J21)|this section]]. |
| style="text-align: center;" | RS232 | | style="text-align: center;" | RS232 | ||
| style="text-align: center;" | J21 | | style="text-align: center;" | J21 | ||
| style="text-align: center;" | Right-angle male DB9 | | style="text-align: center;" | Right-angle male DB9 | ||
| style="text-align: center;" | UART3 | | style="text-align: center;" | UART3 | ||
| − | | style="text-align: center;" | | + | | style="text-align: center;" | See [[#RS232 on DB9 (J34, J21)|this section]]. |
| style="text-align: center;" | RS485 | | style="text-align: center;" | RS485 | ||
|- | |- | ||
| − | | style="text-align: center;" | XUBx1xxxxx | + | | style="text-align: center;" | XUBx1xxxxx [[File:SXUBx1xxx.png|thumb|center|100px|XUBx1xxxxx ]] |
| style="text-align: center;" | J38 | | style="text-align: center;" | J38 | ||
| style="text-align: center;" | Phoenix 1755749 MSTBVA2.5/3-G5.08 | | style="text-align: center;" | Phoenix 1755749 MSTBVA2.5/3-G5.08 | ||
| style="text-align: center;" | UART8 | | style="text-align: center;" | UART8 | ||
| − | | style="text-align: center;" | | + | | style="text-align: center;" | See [[#RS485 on Phoenix 1755749 MSTBVA2.5/3-G5.08 (vertical; J38, J39)|this section]]. |
| style="text-align: center;" | RS485 | | style="text-align: center;" | RS485 | ||
| style="text-align: center;" | not populated | | style="text-align: center;" | not populated | ||
| Line 716: | Line 739: | ||
=====RS232 on DB9 (J34, J21)===== | =====RS232 on DB9 (J34, J21)===== | ||
| − | [[File:SBC Lynx-J34-J21.png|thumb|center|300px| | + | {| class="wikitable" | width="100%" |
| + | |[[File:SBC Lynx-J34.png|thumb|center|300px|J34]] | ||
| + | |[[File:SBC Lynx-J21.png|thumb|center|300px|J21]] | ||
| + | |} | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART0 | + | |+MPUART0 J34 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 749: | Line 775: | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART1 | + | |+MPUART1 J21 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 780: | Line 806: | ||
=====RS422 on DB9 (J34, J21)===== | =====RS422 on DB9 (J34, J21)===== | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART0 | + | |+MPUART0 J34 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 810: | Line 836: | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART1 | + | |+MPUART1 J21 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 840: | Line 866: | ||
=====RS485 on DB9 (J34, J21)===== | =====RS485 on DB9 (J34, J21)===== | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART0 | + | |+MPUART0 J34 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 870: | Line 896: | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART1 | + | |+MPUART1 J21 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 898: | Line 924: | ||
|- | |- | ||
|} | |} | ||
| − | =====RS232 on Phoenix 1755749 MSTBVA2.5/3-G5.08 (vertical; J38, | + | =====RS232 on Phoenix 1755749 MSTBVA2.5/3-G5.08 (vertical; J38, J39)===== |
| + | |||
| + | {| class="wikitable outercollapse" | width="100%" | ||
| + | |[[File:SBC Lynx-J38.png|thumb|center|300px|J38]] | ||
| + | |[[File:SBC Lynx-J39.png|thumb|center|300px|J39]] | ||
| + | |} | ||
| + | |||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART0 | + | |+MPUART0 J38 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 916: | Line 948: | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART1 | + | |+MPUART1 J39 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 930: | Line 962: | ||
|- | |- | ||
|} | |} | ||
| − | =====RS232 on Phoenix 1757255 MSTBVA2.5/3-G5.08 (right-angle; J38, | + | |
| + | =====RS232 on Phoenix 1757255 MSTBVA2.5/3-G5.08 (right-angle; J38, J39)===== | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART0 | + | |+MPUART0 J38 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 948: | Line 981: | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART1 | + | |+MPUART1 J39 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 963: | Line 996: | ||
|} | |} | ||
| − | =====RS485 on Phoenix 1755749 MSTBVA2.5/3-G5.08 (vertical; J38, | + | =====RS485 on Phoenix 1755749 MSTBVA2.5/3-G5.08 (vertical; J38, J39)===== |
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART0 | + | |+MPUART0 J38 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 981: | Line 1,014: | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART1 | + | |+MPUART1 J39 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 995: | Line 1,028: | ||
|- | |- | ||
|} | |} | ||
| − | =====RS485 on Phoenix 1757255 MSTBVA2.5/3-G5.08 (right-angle; J38, | + | =====RS485 on Phoenix 1757255 MSTBVA2.5/3-G5.08 (right-angle; J38, J39)===== |
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART0 | + | |+MPUART0 J38 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 1,013: | Line 1,046: | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+MPUART1 | + | |+MPUART1 J39 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 1,033: | Line 1,066: | ||
=====RS485 alternative pinout for DB9 connector===== | =====RS485 alternative pinout for DB9 connector===== | ||
| + | |||
| + | [[File:SBC Lynx-J21.png|thumb|center|300px|J21]] | ||
| + | |||
On request, it is possible to implement the following pinout. | On request, it is possible to implement the following pinout. | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| Line 1,065: | Line 1,101: | ||
===CAN (J40 or J21)=== | ===CAN (J40 or J21)=== | ||
| + | |||
| + | {| class="wikitable outercollapse" | width="100%" | ||
| + | |[[File:SBC Lynx-J40.png|thumb|center|300px|J40]] | ||
| + | |[[File:SBC Lynx-J21.png|thumb|center|300px|J21]] | ||
| + | |} | ||
| + | |||
CAN interface is associated to the i.MX6UL's FLEXCAN1 controller. Transceiver is Texas Instruments SN65HVD23x. | CAN interface is associated to the i.MX6UL's FLEXCAN1 controller. Transceiver is Texas Instruments SN65HVD23x. | ||
| Line 1,072: | Line 1,114: | ||
If J21 is selected, MPUART1 is not available and the connector's pinout is the one detailed in the following table. | If J21 is selected, MPUART1 is not available and the connector's pinout is the one detailed in the following table. | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+CAN interface on | + | |+CAN interface on J21 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 1,079: | Line 1,121: | ||
!Notes | !Notes | ||
|- | |- | ||
| − | | 1|| | + | | 1||not connected||n/a|| |
|- | |- | ||
| − | | 2|| | + | | 2||Dominant low||CAN_M|| |
|- | |- | ||
| 3||Ground||CAN_GND|| | | 3||Ground||CAN_GND|| | ||
|- | |- | ||
| − | | 4|| | + | | 4||not connected||n/a|| |
|- | |- | ||
| − | | 5|| | + | | 5||Shield||CAN_SHIELD|| |
|- | |- | ||
| 6||not connected||n/a|| | | 6||not connected||n/a|| | ||
|- | |- | ||
| − | | 7|| | + | | 7||Dominant high||CAN_P|| |
|- | |- | ||
| − | | 8|| | + | | 8||not connected||n/a|| |
|- | |- | ||
| 9||not connected||n/a|| | | 9||not connected||n/a|| | ||
| Line 1,104: | Line 1,146: | ||
J40 is a 0.200-inch pitch 3-pin shrouded header (Phoenix 1755749 MSTBVA2.5/3-G5.08). Please refer to the following table for the detailed pinout. | J40 is a 0.200-inch pitch 3-pin shrouded header (Phoenix 1755749 MSTBVA2.5/3-G5.08). Please refer to the following table for the detailed pinout. | ||
{|class="wikitable" style="text-align: center;" | {|class="wikitable" style="text-align: center;" | ||
| − | |+CAN interface on | + | |+CAN interface on J40 |
|- | |- | ||
!Pin # | !Pin # | ||
| Line 1,174: | Line 1,216: | ||
| rowspan="2" style="text-align: center;" | 3 | | rowspan="2" style="text-align: center;" | 3 | ||
| style="text-align: center;" | on | | style="text-align: center;" | on | ||
| − | | Connect | + | | Connect 120 Ohm termination for transmitter pair |
|- | |- | ||
| style="text-align: center;" | off | | style="text-align: center;" | off | ||
| − | | Disconnect any | + | | Disconnect any termination for transmitter pair |
|- | |- | ||
| rowspan="2" style="text-align: center;" | 4 | | rowspan="2" style="text-align: center;" | 4 | ||
| style="text-align: center;" | on | | style="text-align: center;" | on | ||
| − | | Connect | + | | Connect 120 Ohm termination for receiver pair |
|- | |- | ||
| style="text-align: center;" | off | | style="text-align: center;" | off | ||
| − | | Disconnect any | + | | Disconnect any termination for receiver pair |
|} | |} | ||
| Line 1,196: | Line 1,238: | ||
| rowspan="2" style="text-align: center;" | 5 | | rowspan="2" style="text-align: center;" | 5 | ||
| style="text-align: center;" | on | | style="text-align: center;" | on | ||
| − | | Connect | + | | Connect 120 Ohm termination for transmitter pair |
|- | |- | ||
| style="text-align: center;" | off | | style="text-align: center;" | off | ||
| − | | Disconnect any | + | | Disconnect any termination for transmitter pair |
|- | |- | ||
| rowspan="2" style="text-align: center;" | 6 | | rowspan="2" style="text-align: center;" | 6 | ||
| style="text-align: center;" | on | | style="text-align: center;" | on | ||
| − | | Connect | + | | Connect 120 Ohm termination for receiver pair |
|- | |- | ||
| style="text-align: center;" | off | | style="text-align: center;" | off | ||
| − | | Disconnect any | + | | Disconnect any termination for receiver pair |
|} | |} | ||
| + | |||
===RS485 configuration=== | ===RS485 configuration=== | ||
{| class="wikitable" style="text-align: center;" | {| class="wikitable" style="text-align: center;" | ||
Latest revision as of 08:43, 26 September 2017
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 SBC Lynx is extremely flexible in terms of hardware configurations. This document details connector's pinout of common SBC Lynx models. For more information about models not documented here, please contact Sales department. |
Contents
- 1 Introduction
- 2 Connectors
- 2.1 Power supply connector (J35 / JP1)
- 2.2 Serial console (J42)
- 2.3 Ethernet connector (J16)
- 2.4 microSD slot (J43)
- 2.5 USB host port (J48)
- 2.6 USB OTG port (J47)
- 2.7 Mezzanine board connectors (J53/J54)
- 2.8 One-piece interfaces (J45 / J52)
- 2.9 DWM WiFi/Bluetooth module connector (J46)
- 2.10 Multiprotocol UARTs and CAN interfaces
- 2.10.1 Multiprotocol UARTs
- 2.10.1.1 Transceivers' connection
- 2.10.1.2 Connector's pinout
- 2.10.1.2.1 RS232 on DB9 (J34, J21)
- 2.10.1.2.2 RS422 on DB9 (J34, J21)
- 2.10.1.2.3 RS485 on DB9 (J34, J21)
- 2.10.1.2.4 RS232 on Phoenix 1755749 MSTBVA2.5/3-G5.08 (vertical; J38, J39)
- 2.10.1.2.5 RS232 on Phoenix 1757255 MSTBVA2.5/3-G5.08 (right-angle; J38, J39)
- 2.10.1.2.6 RS485 on Phoenix 1755749 MSTBVA2.5/3-G5.08 (vertical; J38, J39)
- 2.10.1.2.7 RS485 on Phoenix 1757255 MSTBVA2.5/3-G5.08 (right-angle; J38, J39)
- 2.10.1.3 Additional options for RS422 and RS485 interfaces
- 2.10.2 CAN (J40 or J21)
- 2.10.1 Multiprotocol UARTs
- 2.11 CPU ONOFF / Power reset connector (J50)
- 3 Buttons
- 4 Switches
Introduction[edit | edit source]
This document details connectors, buttons and switches that equip SBC Lynx board. Please note that not all of them are available on all models.
For some connectors, information related to the internal connections to the processor are provided. In these cases, 14x14mm-package processor's balls references are indicated.
The following table lists connectors, buttons and switches available on SBC Lynx.
| Reference | Function | Type | Part number | Notes |
|---|---|---|---|---|
| J35 | Power supply | 2-pin header, male pins, Shrouded 0.200in pitch | Phoenix 1757242 MSTBA 2.5/2-G-5.08 | [1] |
| JP1 | Power supply | 2.1mm ID, 5.5mm OD | CUI PJ-002A | [1] |
| J42 | System console | TTL 3.3V UART 4-pin Header, Male 0.100in pitch | ||
| J50 | System ONOFF / Power reset | 4-pin Header, Male 0.100in pitch | ||
| J16 | 10/100 Base-T Ethernet port | RJ-45 | Wurth 74990112116A | |
| J43 | microSD slot | push-pull slot | Molex 47571-0001 | |
| J47 | USB OTG | USB type micro AB | Hirose ZX62D-AB-5P8 | |
| J55 | USB OTG | USB type micro B vertical | Molex 105133-0011 | |
| J48 | USB host | USB type A Right Angle | Wurth WE-614 004 134 726 | |
| J34 | MPUART0 ( RS232 / RS485 / RS422 ) | DB9 90° Connector Male or Female | [2], [3] | |
| J38 | MPUART0 ( RS232 / RS485 / RS422 ) | 3-pins Header, Male Pins, Shrouded 0.200in pitch | Phoenix 1755749 MSTBVA2.5/3-G5.08 | [3] |
| J21 | MPUART1 ( RS232 / RS485 / RS422 / CAN) | DB9 90° Connector Male or Female | [2], [4] | |
| J39 | MPUART1 ( RS232 / RS485 / RS422 / CAN) | 3-pins Header, Male Pins, Shrouded 0.200in pitch | Phoenix 1755749 MSTBVA2.5/3-G5.08 | [2] |
| J40 | CAN | 3-pins Header, Male Pins, Shrouded 0.200in pitch | Phoenix 1755749 MSTBVA2.5/3-G5.08 | [4] |
| J46 | DAVE DWM WiFi/Bluetooth module interface | 30-pins SlimStack™ Receptacle 0.50mm pitch | Molex 52991-0308 | |
| J45/J52 | ONE Piece | 30x2 pins, pitch 1.00mm One Piece Interface | Samtec FSI-130-03-G-D-M-K-TR | |
| J53/J54 | Mezzanine Board Connectors | 10-pins Header 0.100inch | ||
| S11 | Reset button | |||
| S12 | Boot Mode / UART Termination resistors | 8-positions DIP Switches | WE-416131160808 | |
| J49 | JTAG | 1.27mm-pitch 5x2 header |
[1] These parts are mutually exclusive.
[2] Because mechanical interferences, the following combinations are allowed:
| Reference | Option #1 | Option #2 | Option #3 | Option #4 | Option #5 |
|---|---|---|---|---|---|
| J39 | populated | not populated | not populated | not populated | not populated |
| J21 | not populated | populated | populated | not populated | not populated |
| J34 | not populated | populated | not populated | populated | not populated |
[3] These parts are mutually exclusive.
[4] These parts are mutually exclusive.
The following image shows where connectors, buttons and switches are located.
Connectors[edit | edit source]
Power supply connector (J35 / JP1)[edit | edit source]
J35[edit | edit source]
| Pin # | Name | Description | Notes |
|---|---|---|---|
| 1 | GND | Ground | |
| 2 | VIN | Positive supply voltage | Range: 5 ÷ 24 V |
JP1[edit | edit source]
| Pin # | Name | Description | Notes |
|---|---|---|---|
| 1 | VIN | Positive supply voltage | Range: 5 ÷ 24 V |
| 2 | GND | Ground | |
| 3 | GND | Ground |
Serial console (J42)[edit | edit source]
System console is by default routed to this interface. This is typically used during the development stage.
| Pin # | Processor ball | Name | Default function | Type | Voltage domain | Notes |
|---|---|---|---|---|---|---|
| 1 | K14 | UART1_TX_DATA | UART1 transmit line | Output | IO_3.3V | - |
| 2 | K16 | UART1_RX_DATA | UART1 receive line | Input | IO_3.3V | - |
| 3 | - | IO_3.3V | UART1 I/O voltage reference | Voltage reference | IO_3.3V | - |
| 4 | - | DGND | Ground | - | - | - |
J42 connector is compatible with FTDI TTL-232RG-VIP-WE cable. To connect it, please use this wiring:
- J42.1: yellow wire
- J42.2: orange wire
- J42.3: red wire
- J42.4: black wire
Ethernet connector (J16)[edit | edit source]
J16 is a standard RJ45 10/100BaseT Ethernet connector - incorporating magnetics - connected to the Ethernet controller and PHY.
J16 integrates a green status LED providing connection information:
- LED on: link established
- LED blinking: activity.
The following table describes the interface signals:
| Pin # | Name | Function | Notes |
|---|---|---|---|
| 1 | TDP | TX+ | |
| 2 | TCT | TX center tap | |
| 3 | TDN | TX- | |
| 4 | RDP | RX+ | |
| 5 | RCT | RX center tap | |
| 6 | RDN | RX- | |
| 7 | NC | Not connected | |
| 8 | CHS_GND | Chassis ground | See also this page |
microSD slot (J43)[edit | edit source]
J43 is a push-pull microSD card slot connected to uSDHC1 port of MX6UL processor.
The following table details the pinout:
| Pin # | Name | Function | Notes |
|---|---|---|---|
| 1 | DAT2 | Data line #2 | |
| 2 | DAT3 | Data line #3 | |
| 3 | CMD | Command | |
| 4 | VDD | 3.3V | |
| 5 | CLK | Clock | |
| 6 | Vss | Ground | |
| 7 | DAT0 | Data line #0 | |
| 8 | DAT1 | Data line #2 | See also this page |
| 9 | SD_SHIELD | Metal case | See also this page |
| 10 | SD_SHIELD | Metal case | See also this page |
| 11 | SD_SHIELD | Metal case | See also this page |
| 12 | Vss | Ground | |
| 13 | CD | Card detect | Pulled-up to 3.3V |
USB host port (J48)[edit | edit source]
J48 is a standard USB Type A right angle connector connected to the MX6UL USB_OTG2 port signals.
The following table reports the connector's pinout:
| Pin # | iMX6UL ball# | Pin name | Function | Notes |
| 1 | U12 | USB_HOST_VBUS | 5V | up to 470mA |
| 2 | T13 | USB_OTG2_DN | USB2 Data - | - |
| 3 | U13 | USB_OTG2_DP | USB2 Data + | - |
| 4 | - | DGND | Ground | - |
| 5, 6, 7, 8 | - | PCB_GND_RNG | Connector Shield | - |
USB OTG port (J47)[edit | edit source]
J47 is a standard USB Type micro AB connector connected to the MX6UL USB_OTG1 port signals.
The following table reports the connector's pinout:
| Pin # | iMX6UL ball# | Pin name | Function | Notes |
| 1 | T12 | USB_OTG_VBUS | Reference voltage from ext or 5V in HOST mode | Up to 75mA (HOST) |
| 2 | T15 | USB_OTG1_DN | USB1 OTG Data - | - |
| 3 | U15 | USB_OTG1_DP | USB1 OTG Data + | - |
| 4 | K13 | USB_OTG1_ID | OTG ID | - |
| 5 | - | USB_GND | Ground | - |
| 6, 7, 8, 9 | - | PCB_GND_RNG | Connector Shield | - |
Mezzanine board connectors (J53/J54)[edit | edit source]
J53 and J54 are 10x1-pin 2.54mm-pitch vertical headers for optional mezzanine expansion boards. These boards can be implemented to extend SBC Lynx functionalities and/or interfaces.
It is worth remembering that some of the mezzanine board connectors signals are reserved for internal use or shared with One Piece connector (J45 / J52). Please contact Sales department for more information.
The following tables report the connectors' pinout.
| Pin # | Processor ball | Name | Default function | Type | Voltage domain | Notes |
|---|---|---|---|---|---|---|
| 1 | J16 | UART2_RX_DATA | UART2_RX | I/O | IO_3.3V | [1], [2] |
| 2 | H14 | UART2_nRTS | UART2_RTS | I/O | IO_3.3V | [1], [2] |
| 3 | J17 | UART2_TX_DATA | UART2_TX | I/O | IO_3.3V | [1], [2] |
| 4 | J15 | UART2_nCTS | UART2_CTS | I/O | IO_3.3V | [1], [2] |
| 5 | F17 | UART5_TX_DATA | UART5_TX / I2C2_SCL | I/O | IO_3.3V | |
| 6 | G13 | UART5_RX_DATA | UART5_RX / I2C2_SDA | I/O | IO_3.3V | |
| 7 | D14 | MEZZANINE_GP0 | GPIO / PWM | I/O | IO_3.3V | [3], [4] |
| 8 | A14 | MEZZANINE_GP1 | GPIO | I/O | IO_3.3V | [3], [4] |
| 9 | B16 | MEZZANINE_GP2 | GPIO | I/O | IO_3.3V | [3], [4] |
| 10 | DGND | Ground | - | - |
[1] This group of signals can be configured to implement this alternative functions:
- I2C4
- CAN2
- SPI3 (CS0).
[2] Not available is DWM WIFI present
[3] This signal acts as bootstrap configuration flag and may be pulled up or down with 10kOhm resistor. Do not drive these signals until CPU_PORn is deasserted. For more details please refer to this section.
[4] Not available if 24-bit LCD interface is used.
| Pin # | Processor ball | Name | Default function | Type | Voltage domain | Notes |
|---|---|---|---|---|---|---|
| 1 | - | VIN | - | Power | - | Power supply of VIN_5_24V domain |
| 2 | - | PMIC_5V | - | Power | - | Power supply of AUX_5V domain |
| 3 | - | 3V3_AUX | - | Power | - | Power supply of AUX_3.3V domain |
| 4 | - | VDDA_ADC_3P3 | - | Power | - | Power supply of ADC_3.3V domain [5] |
| 5 | L15 | GPIO1_IO01 | GPIO / ADC | I/O | ADC_3.3V | 12-bit ADC |
| 6 | L14 | GPIO1_IO02 | GPIO / ADC | I/O | ADC_3.3V | 12-bit ADC |
| 7 | L17 | GPIO1_IO03 | GPIO / ADC | I/O | ADC_3.3V | 12-bit ADC |
| 8 | M16 | GPIO1_IO04 | GPIO / ADC | I/O | ADC_3.3V | 12-bit ADC |
| 9 | M17 | GPIO1_IO05 | GPIO / ADC | I/O | ADC_3.3V | 12-bit ADC |
| 10 | - | DGND | Ground | - | - |
[5] To be used for voltage reference only.
Handling bootstrap signals[edit | edit source]
MEZZANINE_GP0, MEZZANINE_GP1 and MEZZANINE_GP2 are connected to LCD_DATA19, LCD_DATA22 and LCD_DATA23 respectively. As such, they act as bootstrap configuration signals as well. They can be used by application software freely and they can be connected to user's application circuitry. However, any electrical interference during the processor reset cycle must be avoided.
There are different solutions to comply with this requirement. The following image shows a concept solution for this problem.
During the processor reset cycle, MEZZANINE_GP0, MEZZANINE_GP1 and MEZZANINE_GP2 [1] are isolated from user's application logic by a bus switch that is in high-impedence state. Bus switch's BUS_SW_OE_n signal is connected to another processor's GPIO (GPIO1_IO01 in the example). Before configuring and using MEZZANINE_GPx signals, application software needs to:
- initialize GPIO1_IO01 as GPIO ouput
- set GPIO1_IO01 to logic level 0 in order to enable the switch.
[1] The same considerations apply to all of LCD_DATAx signals that are routed to J45/J52 connectors.
One-piece interfaces (J45 / J52)[edit | edit source]
J45 and J52 are two interfaces designed to be populated with Samtec 1.00mm-pitch 30x2-pin FSI One-piece connectors. The peculiarity of this kind of connectors if the fact that they
- allow to mate two boards by using one connector only
- the connector is mounted on one of the two boards indifferently.
J45 and J52 that share the same pinout, however they are intended to be used for different goals. J45 - that is placed on the top side of the PCB - is generally used to mate an optional expansion board. J52 - that is placed on the bottom side of the PCB - is conceived to mate SBC Lynx to a larger carrier board. In this case SBC Lynx can be thought as as an add-on for another board and can be powered via J52 interface itself.
It is worth remembering that some of the J45/J52 signals are reserved for internal use or shared with mezzanine board connectors. Please contact DAVE Embedded Systems' Sales department to get more information.
The following tables reports the interfaces' pinout that is the same for J45 and J52:
| Pin # | Processor ball | Name and default function | Alternative functions [1] |
Type (Assuming default function is selected) |
Voltage domain | Notes |
|---|---|---|---|---|---|---|
| 1 | - | DGND | Ground | - | ||
| 3 | A8 | LCD_CLK | UART4_TX | Output | IO_3.3V | - |
| 5 | B8 | LCD_ENABLE | UART4_RX | Output | IO_3.3V | - |
| 7 | D9 | LCD_HSYNC | UART4_CTS_B | Output | IO_3.3V | - |
| 9 | C9 | LCD_VSYNC | UART4_RTS_B | Output | IO_3.3V | - |
| 11 | E9 | LCD_RESET | Output | IO_3.3V | - | |
| 13 | - | DGND | Ground | - | ||
| 15 | B9 | LCD_DATA00 | Output | IO_3.3V | [3] | |
| 17 | A9 | LCD_DATA01 | Output | IO_3.3V | [3] | |
| 19 | E10 | LCD_DATA02 | Output | IO_3.3V | [3] | |
| 21 | D10 | LCD_DATA03 | Output | IO_3.3V | [3] | |
| 23 | C10 | LCD_DATA04 | Output | IO_3.3V | [3] | |
| 25 | B10 | LCD_DATA05 | Output | IO_3.3V | [3] | |
| 27 | A10 | LCD_DATA06 | UART7_CTS_B | Output | IO_3.3V | [3] |
| 29 | - | DGND | Ground | - | ||
| 31 | D11 | LCD_DATA07 | UART7_RTS_B | Output | IO_3.3V | [3] |
| 33 | B11 | LCD_DATA08 | FLEXCAN1_TX | Output | IO_3.3V | [3] |
| 35 | A11 | LCD_DATA09 | FLEXCAN1_RX | Output | IO_3.3V | [3] |
| 37 | E12 | LCD_DATA10 | FLEXCAN2_TX / SAI3_RX_SYNC | Output | IO_3.3V | [3] |
| 39 | D12 | LCD_DATA11 | FLEXCAN2_RX / SAI3_RX_BCLK | Output | IO_3.3V | [3] |
| 41 | C12 | LCD_DATA12 | SAI3_TX_SYNC | Output | IO_3.3V | [3] |
| 43 | - | DGND | Ground | - | ||
| 45 | T13 | USB_OTG2_EXP_DN | USB_OTG2_DN | [2] | ||
| 47 | U13 | USB_OTG2_EXP_DP | USB_OTG2_DP | [2] | ||
| 49 | U12 | USB_OTG2_VBUS | USB_OTG2_VBUS | - | ||
| 51 | K15 | UART1_CTS_B | GPIO1_IO18 | Input | IO_3.3V | - |
| 53 | - | CPU_PORn | Reset | Input | - | |
| 55 | - | 3V3_AUX | 3V3 PMIC regulator | < 1A – shared with J54.3 | ||
| 57 | - | VIN | Power Supply | - | ||
| 59 | - | DGND | Ground | IO_3.3V | - | |
| 2 | B12 | LCD_DATA13 | SAI3_TX_BCLK / USDHC2_RESET_B | Output | IO_3.3V | [3] |
| 4 | A12 | LCD_DATA14 | SAI3_RX_DATA / USDHC2_DATA4 | Output | IO_3.3V | [3] |
| 6 | D13 | LCD_DATA15 | SAI3_TX_DATA / USDHC2_DATA5 | Output | IO_3.3V | [3] |
| 8 | C13 | LCD_DATA16 | UART7_TX / USDHC2_DATA6 | Output | IO_3.3V | [3] |
| 10 | B13 | LCD_DATA17 | UART7_RX / USDHC2_DATA7 | Output | IO_3.3V | [3] |
| 12 | A13 | LCD_DATA18 | PWM5_OUT / USDHC2_CMD | Output | IO_3.3V | [3] |
| 14 | D14 | LCD_DATA19 | PWM6_OUT / USDHC2_CLK | Output | IO_3.3V | [3] |
| 16 | C14 | LCD_DATA20 | ECSPI1_SCLK / USDHC2_DATA0 | Output | IO_3.3V | SPI1 is available only if NOR is not mounted, [3] |
| 18 | B14 | LCD_DATA21 | ECSPI1_SS0 / USDHC2_DATA1 | Output | IO_3.3V | SPI1 is available only if NOR is not mounted, [3] |
| 20 | A14 | LCD_DATA22 | ECSPI1_MOSI / USDHC2_DATA2 | Output | IO_3.3V | SPI1 is available only if NOR is not mounted, [3] |
| 22 | B16 | LCD_DATA23 | ECSPI1_MISO / USDHC2_DATA3 | Output | IO_3.3V | SPI1 is available only if NOR is not mounted, [3] |
| 24 | - | DGND | Ground | - | ||
| 26 | C17 | ENET2_RX_DATA0 | UART6_TX / I2C3_SCL | Input | IO_3.3V | Default: internally used as USB OTG power |
| 28 | C16 | ENET2_RX_DATA1 | UART6_RX / I2C3_SDA | Input | IO_3.3V | Default: internally used as USB OTG over current |
| 30 | B17 | ENET2_RX_EN | UART7_TX / I2C4_SCL | Input | IO_3.3V | - |
| 32 | A15 | ENET2_TX_DATA0 | UART7_RX / I2C4_SDA / | Output | IO_3.3V | - |
| 34 | A16 | ENET2_TX_DATA1 | UART8_TX / ECSPI4_SCLK | Output | IO_3.3V | Default: internally used as USB HOST pwr |
| 36 | B15 | ENET2_TX_EN | UART8_RX / ECSPI4_MOSI | Output | IO_3.3V | Default: internally used as USB HOST over current |
| 38 | D17 | ENET2_TX_CLK | UART8_CTS_B / ECSPI4_MISO / ANATOP_OTG2_ID | Output | IO_3.3V | Default: internally used as UART8_CTS on MPUART0 |
| 40 | D16 | ENET2_RX_ER | UART8_RTS_B / ECSPI4_SS0 | Input | IO_3.3V | Default: internally used as UART8_RTS on MPUART0 |
| 42 | - | DGND | Ground | IO_3.3V | - | |
| 44 | L16 | GPIO1_IO07 | ENET2_MDC / ADC1_IN7 | Input/Output | IO_3.3V | Default: Internally used as ENET1_MDC |
| 46 | K17 | GPIO1_IO06 | ENET2_MDIO / ADC1_IN6 | Input/Output | IO_3.3V | Default: Internally used as ENET1_MDIO |
| 48 | M17 | GPIO1_IO05 | UART5_RX / ADC1_IN5 | Input/Output | IO_3.3V | - |
| 50 | M16 | GPIO1_IO04 | UART5_TX / TSC(xpul) / ADC1_IN4 | Input/Output | IO_3.3V | - |
| 52 | L17 | GPIO1_IO03 | TSC(xnur) / ADC1_IN3 | Input/Output | IO_3.3V | - |
| 54 | L14 | GPIO1_IO02 | TSC(ypll) / ADC1_IN2 | Input/Output | IO_3.3V | - |
| 56 | L15 | GPIO1_IO01 | TSC(ynlr) / ADC1_IN1 | Input/Output | IO_3.3V | - |
| 58 | K13 | GPIO1_IO00 | TSC(wiper) / ADC1_IN0 | Input/Output | IO_3.3V | Default: internally used as USB OTG ID |
| 60 | - | DGND | Ground | - |
[1] Please contact the Sales Deparment for more details.
[2] This signal can be routed here instead of connector J48. Please refer to the Sale Deparment for more details.
[3] LCD_DATAx signals act as bootstrap configuration pins as well. They can be used by application software freely and they can be connected to user's application circuitry. However, any electrical interference during the processor reset cycle must be avoided. Please see Handling bootstrap signals section for more details.
DWM WiFi/Bluetooth module connector (J46)[edit | edit source]
J46 is a 30-pins SlimStack™ Receptacle 0.50mm pitch that allows to connect to DAVE Embedded Systems' DWM Wifi/BT module. The following table reports the connector's pinout:
| Pin # | Processor ball | Name | Default function | Type | Voltage domain | Notes |
|---|---|---|---|---|---|---|
| 1,2 | - | PMIC_5V | 5V DWM Module Power Supply | Up to 500mA shared with USB Host / OTG Mezzanine Board Connector | ||
| 3,4 | - | 3V3_IO | DWM Level Shifter Power Supply | - | ||
| 5, 6, 9, 10, 19 | - | DGND | Ground | - | ||
| 12, 14, 16, 18, 20, 22 | - | NC | - | - | ||
| 7 | F3 | WIFI_CMD | USDHC2_CMD | Output | IO_3.3V | - |
| 8 | F2 | WIFI_CLK | USDHC2_CLK | Output | IO_3.3V | - |
| 11 | E4 | WIFI_DATA0 | USDHC2_DATA0 | Input/Output | IO_3.3V | - |
| 13 | E3 | WIFI_DATA1 | USDHC2_DATA1 | Input/Output | IO_3.3V | - |
| 15 | E2 | WIFI_DATA2 | USDHC2_DATA2 | Input/Output | IO_3.3V | - |
| 17 | E1 | WIFI_DATA3 | USDHC2_DATA3 | Input/Output | IO_3.3V | - |
| 21 | J16 | BT_UART_RX | UART2_RX_DATA | Input | IO_3.3V | - |
| 23 | H14 | BT_UART_CTS | UART2_CTS_B | Input | IO_3.3V | - |
| 24 | R9 | TIWI_BT_F5 | GPIO3_IO23 | Input | IO_3.3V | - |
| 25 | J17 | BT_UART_TX | UART2_TX_DATA | Output | IO_3.3V | - |
| 26 | R10 | TIWI_BT_F2 | GPIO3_IO24 | Output | IO_3.3V | - |
| 27 | J15 | BT_UART_RTS | UART2_RTS_B | Output | IO_3.3V | - |
| 28 | P10 | TIWI_IRQ | GPIO5_IO04 | Input | IO_3.3V | - |
| 29 | N10 | TIWI_BT_EN | SNVS_TAMPER7 | Output | IO_3.3V | - |
| 30 | P9 | TIWI_EN | GPIO5_IO03 | Output | IO_3.3V | - |
Multiprotocol UARTs and CAN interfaces[edit | edit source]
There are two UART multiprotocol ports (RS232 / RS485 / RS422) and one CAN interface available on SBC LYNX. They are described in the same section because they share some resources. Please refer to this section for more details about allowable combinations.
Multiprotocol UARTs[edit | edit source]
Multiprotocol UARTs are named as MPUART0 and MPUART1. They are associated to i.MX6UL's native UART8 and UART3 respectively. They are routed to connectors through Intersil ISL3330 transceivers (one for each port).
Generally speaking, multiprotocol UARTs
- supports RS232, RS485 and RS422 electrical protocols independently (meaning that, for example, MPUART0 can be configured as RS485 and MPUART1 can be configured as RS485)
- electrical protocol is selected by different mounting options
- can be routed to different types of connector independently; supported connectors are:
- right-angle male DB9
- Phoenix 1755749 MSTBVA2.5/3-G5.08 (vertical)
- Phoenix 1757255 MSTBA 2.5/3-G-5.08 (righ-angle).
This wide flexibility allows to implement many different combinations. The following table details two of them. For actual available options, please contact Sales department.
| P/N and image | MPUART0 | MPUART1 | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| Connector | i.MX6UL's native port | Pinout | Electrical protocol | Connector | i.MX6UL's native port | Pinout | Electrical protocol | |||
| Reference | Type | Reference | Type | |||||||
| XUBx0xxxxx | J34 | Right-angle male DB9 | UART8 | See this section. | RS232 | J21 | Right-angle male DB9 | UART3 | See this section. | RS485 |
| XUBx1xxxxx | J38 | Phoenix 1755749 MSTBVA2.5/3-G5.08 | UART8 | See this section. | RS485 | not populated | n/a | n/a | n/a | n/a |
Transceivers' connection[edit | edit source]
The following table describes the MPUART0 signals to the ISL3330 transceiver:
| Pin # | Processor ball | Name | Default function | Type | Voltage domain | Notes |
|---|---|---|---|---|---|---|
| 8 | - | MPUART0_485/232# | Protocol Selection | Fixed with Pull UP/DOWN resistor | ||
| 9 | N9 | MPUART0_DEN | Driver Output Enable | Output | IO_3.3V | - |
| 12 | R6 | MPUART0_RXEN | Receiver Output Enable | Output | IO_3.3V | - |
| 13 | F5 | MPUART0_ON | RS232 Charge Pump Enable | Output | IO_3.3V | - |
| 14 | D16 | MPUART0_nRTS | UART8_RTS_B | Output | IO_3.3V | - |
| 15 | C14 | MPUART0_TX_DATA | UART8_TX | Output | IO_3.3V | - |
| 16 | D17 | MPUART0_nCTS | UART8_CTS_B | Input | IO_3.3V | - |
| 17 | B14 | MPUART0_RX_DATA | UART8_RX | Input | IO_3.3V | - |
The following table describes the MPUART1 signals to the ISL3330 transceiver:
| Pin # | Processor ball | Name | Default function | Type | Voltage domain | Notes |
|---|---|---|---|---|---|---|
| 8 | - | MPUART1_485/232# | Protocol Selection | Fixed with Pull UP/DOWN resistor | ||
| 9 | N8 | MPUART1_DEN | Driver Output Enable | Output | IO_3.3V | - |
| 12 | N11 | MPUART1_RXEN | Receiver Output Enable | Output | IO_3.3V | - |
| 13 | E5 | MPUART1_ON | RS232 Charge Pump Enable | Output | IO_3.3V | - |
| 14 | G14 | MPUART1_nRTS | UART3_RTS_B | Output | IO_3.3V | - |
| 15 | H17 | MPUART1_TX_DATA | UART3_TX_DATA | Output | IO_3.3V | - |
| 16 | H15 | MPUART1_nCTS | UART3_CTS_B | Input | IO_3.3V | - |
| 17 | H16 | MPUART1_RX_DATA | UART3_RX_DATA | Input | IO_3.3V | - |
The following table describes the CAN to the SN65HVD23x transceiver:
| Pin # | Processor ball | Name | Default function | Type | Voltage domain | Notes |
|---|---|---|---|---|---|---|
| 1 | H15 | CAN_D | Transmit data input | Input | IO_3.3V | Alternative to MPUART1_nCTS |
| 4 | G14 | CAN_R | Receive data output | Output | IO_3.3V | Alternative to MPUART1_nRTS |
Connector's pinout[edit | edit source]
The following sections detail connectcors' pinout for the supported configuration. In case RS422 or RS485 configurations are used, termination options are selectable by acting on S12 switches, as described in this section.
RS232 on DB9 (J34, J21)[edit | edit source]
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | not connected | n/a | |
| 2 | MPUART0_A | RXD | |
| 3 | MPUART0_Y | TXD | |
| 4 | not connected | n/a | |
| 5 | DGND | Ground | |
| 6 | not connected | n/a | |
| 7 | MPUART0_Z | RTS | |
| 8 | MPUART0_B | CTSn | |
| 9 | not connected | n/a | |
| SH1, SH2 | PCB_GND_RNG | Shield |
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | not connected | n/a | |
| 2 | MPUART1_A | RXD | |
| 3 | MPUART1_Y | TXD | |
| 4 | not connected | n/a | |
| 5 | DGND | Ground | |
| 6 | not connected | n/a | |
| 7 | MPUART1_Z | RTS | |
| 8 | MPUART1_B | CTSn | |
| 9 | not connected | n/a | |
| SH1, SH2 | PCB_GND_RNG | Shield |
RS422 on DB9 (J34, J21)[edit | edit source]
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | not connected | n/a | |
| 2 | MPUART0_A | Inverting receiver input | |
| 3 | MPUART0_Y | Inverting driver output | |
| 4 | not connected | n/a | |
| 5 | DGND | Ground | |
| 6 | not connected | n/a | |
| 7 | MPUART0_Z | Non-inverting driver output | |
| 8 | MPUART0_B | Non-inverting receiver input | |
| 9 | not connected | n/a | |
| SH1, SH2 | PCB_GND_RNG | Shield |
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | not connected | n/a | |
| 2 | MPUART1_A | Inverting receiver input | |
| 3 | MPUART1_Y | Inverting driver output | |
| 4 | not connected | n/a | |
| 5 | DGND | Ground | |
| 6 | not connected | n/a | |
| 7 | MPUART1_Z | Non-inverting driver output | |
| 8 | MPUART1_B | Non-inverting receiver input | |
| 9 | not connected | n/a | |
| SH1, SH2 | PCB_GND_RNG | Shield |
RS485 on DB9 (J34, J21)[edit | edit source]
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | not connected | n/a | |
| 2 | MPUART0_A, MPUART0_Y | Inverting receiver input, inverting driver output | |
| 3 | MPUART0_A, MPUART0_Y | Inverting receiver input, inverting driver output | |
| 4 | not connected | n/a | |
| 5 | DGND | Ground | |
| 6 | not connected | n/a | |
| 7 | MPUART0_B, MPUART0_Z | Non-inverting receiver input, non-inverting driver output | |
| 8 | MPUART0_B, MPUART0_Z | Non-inverting receiver input, non-inverting driver output | |
| 9 | not connected | n/a | |
| SH1, SH2 | PCB_GND_RNG | Shield |
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | not connected | n/a | |
| 2 | MPUART1_A, MPUART1_Y | Inverting receiver input, inverting driver output | |
| 3 | MPUART1_A, MPUART1_Y | Inverting receiver input, inverting driver output | |
| 4 | not connected | n/a | |
| 5 | DGND | Ground | |
| 6 | not connected | n/a | |
| 7 | MPUART1_B, MPUART1_Z | Non-inverting receiver input, non-inverting driver output | |
| 8 | MPUART1_B, MPUART1_Z | Non-inverting receiver input, non-inverting driver output | |
| 9 | not connected | n/a | |
| SH1, SH2 | PCB_GND_RNG | Shield |
RS232 on Phoenix 1755749 MSTBVA2.5/3-G5.08 (vertical; J38, J39)[edit | edit source]
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | MPUART0_A | RXD | |
| 2 | MPUART0_Y | TXD | |
| 3 | DGND | Ground |
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | MPUART1_A | RXD | |
| 2 | MPUART1_Y | TXD | |
| 3 | DGND | Ground |
RS232 on Phoenix 1757255 MSTBVA2.5/3-G5.08 (right-angle; J38, J39)[edit | edit source]
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | MPUART0_A | RXD | |
| 2 | MPUART0_Y | TXD | |
| 3 | DGND | Ground |
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | MPUART1_A | RXD | |
| 2 | MPUART1_Y | TXD | |
| 3 | DGND | Ground |
RS485 on Phoenix 1755749 MSTBVA2.5/3-G5.08 (vertical; J38, J39)[edit | edit source]
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | MPUART0_A | Inverting receiver input, inverting driver output | |
| 2 | MPUART0_B | Non-inverting receiver input, non-inverting driver output | |
| 3 | DGND | Ground |
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | MPUART1_A | Inverting receiver input, inverting driver output | |
| 2 | MPUART1_B | Non-inverting receiver input, non-inverting driver output | |
| 3 | DGND | Ground |
RS485 on Phoenix 1757255 MSTBVA2.5/3-G5.08 (right-angle; J38, J39)[edit | edit source]
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | MPUART0_A | Inverting receiver input, inverting driver output | |
| 2 | MPUART0_B | Non-inverting receiver input, non-inverting driver output | |
| 3 | DGND | Ground |
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | MPUART1_A | Inverting receiver input, inverting driver output | |
| 2 | MPUART1_B | Non-inverting receiver input, non-inverting driver output | |
| 3 | DGND | Ground |
Additional options for RS422 and RS485 interfaces[edit | edit source]
Other options are available on request, as described in the following sections. For more information, please contact Sales department.
Fail-safe resistors[edit | edit source]
On request, it is possible to populate fail-safe resistors on RS422/RS485 differential signals. For more information, please contact Sales department.
RS485 alternative pinout for DB9 connector[edit | edit source]
On request, it is possible to implement the following pinout.
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | not connected | n/a | |
| 2 | MPUARTx_B, MPUARTx_Z | Non-inverting receiver input, non-inverting driver output | |
| 3 | not connected | n/a | |
| 4 | not connected | n/a | |
| 5 | DGND | Ground | |
| 6 | not connected | n/a | |
| 7 | not connected | n/a | |
| 8 | MPUARTx_A, MPUARTx_Y | Inverting receiver input, inverting driver output | |
| 9 | not connected | n/a | |
| SH1, SH2 | PCB_GND_RNG | Shield |
CAN (J40 or J21)[edit | edit source]
CAN interface is associated to the i.MX6UL's FLEXCAN1 controller. Transceiver is Texas Instruments SN65HVD23x.
There are two mutually exclusive moounting options available for CAN bus:
- J40 (3-pin shrouded header)
- J21 (DB9).
If J21 is selected, MPUART1 is not available and the connector's pinout is the one detailed in the following table.
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | not connected | n/a | |
| 2 | Dominant low | CAN_M | |
| 3 | Ground | CAN_GND | |
| 4 | not connected | n/a | |
| 5 | Shield | CAN_SHIELD | |
| 6 | not connected | n/a | |
| 7 | Dominant high | CAN_P | |
| 8 | not connected | n/a | |
| 9 | not connected | n/a | |
| SH1, SH2 | PCB_GND_RNG | Shield |
J40 is a 0.200-inch pitch 3-pin shrouded header (Phoenix 1755749 MSTBVA2.5/3-G5.08). Please refer to the following table for the detailed pinout.
| Pin # | Internal connection | Signal name | Notes |
|---|---|---|---|
| 1 | Dominant high | CAN_P | |
| 2 | Dominant low | CAN_M | |
| 3 | Ground | DGND | |
| 4 | PCB_GND_RNG | Guard ring |
CPU ONOFF / Power reset connector (J50)[edit | edit source]
J50 is a 0.100in-pitch 4-pin male header that allows connection to signals needed to implement advanced power modes.
The following table reports the connector pinout:
| Pin # | Processor ball | Name | Default function | Default type | Voltage domain | Notes |
|---|---|---|---|---|---|---|
| 1 | R8 | CPU_ONOFF | See this page. | - | SNVS | |
| 2 | - | SXUB_ENA | Main DC/DC enable | Input | VIN_5_24V | See this page. |
| 3 | - | PMIC_PWRON | See this page. | - | SNVS | |
| 4 | - | DGND | Ground | 0V | - |
For more details please refer to this page.
Buttons[edit | edit source]
Reset button (S11)[edit | edit source]
When pressed, a full power-up cycle is triggered, resulting in a complete hardware reset of the system.
Switches[edit | edit source]
Boot mode (S12)[edit | edit source]
Please refer to this page.
Multiprotocol UARTs settings (S12)[edit | edit source]
RS422 configuration[edit | edit source]
| Switch # | Position | Setting |
|---|---|---|
| 3 | on | Connect 120 Ohm termination for transmitter pair |
| off | Disconnect any termination for transmitter pair | |
| 4 | on | Connect 120 Ohm termination for receiver pair |
| off | Disconnect any termination for receiver pair |
| Switch # | Position | Setting |
|---|---|---|
| 5 | on | Connect 120 Ohm termination for transmitter pair |
| off | Disconnect any termination for transmitter pair | |
| 6 | on | Connect 120 Ohm termination for receiver pair |
| off | Disconnect any termination for receiver pair |
RS485 configuration[edit | edit source]
| Switch # | Position | Setting |
|---|---|---|
| 3 | on | 120R Termination for Bidirectional Differential Pair |
| off | No Termination for Bidirectional Differential Pair | |
| 4 | on | N.C. |
| off | N.C. |
| Switch # | Position | Setting |
|---|---|---|
| 5 | on | 120R Termination for Bidirectional Differential Pair |
| off | No Termination for Bidirectional Differential Pair | |
| 6 | on | N.C. |
| off | N.C. |
CAN bus settings (S12)[edit | edit source]
S12.7 switch allows to connect/disconnect 120 Ohm termination between dominant high and low signals.
| S12.7 position | Termination |
|---|---|
| on | connected |
| off | disconnected |
