Difference between revisions of "Category:BoraX"

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__TOC__
 
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 +
  
 
= BORA Xpress XILINX Zynq CPU module =
 
= BORA Xpress XILINX Zynq CPU module =
  
−
[[File:BORA Xpress.png|200px|frameless|border]]
+
[[File:BORA Xpress.png|200px|frameless|border|left]]
  
 
BORA Xpress is the top-class Dual Cortex-A9 + FPGA CPU module by DAVE Embedded Systems, based on the recent Xilinx "Zynq" XC7Z015 / XC7Z030 application processor.
 
BORA Xpress is the top-class Dual Cortex-A9 + FPGA CPU module by DAVE Embedded Systems, based on the recent Xilinx "Zynq" XC7Z015 / XC7Z030 application processor.
Line 26: Line 12:
 
BORA Xpress is designed in order to keep full compatibility with the ULTRA Line CPU modules, to guarantee the premium quality and technical value of those customers that require top performances.
 
BORA Xpress is designed in order to keep full compatibility with the ULTRA Line CPU modules, to guarantee the premium quality and technical value of those customers that require top performances.
  
−
== Main Features ==
+
The [[BORA_Xpress_SOM#Hardware | Hardware]] section provides detailed information about hardware interfaces and characteristics. This document will provide a functional overview of the module and will focus on system-related issues.
−
* Unmatched performance thanks to Dual ARM Cortex-A9 @ up to 1GHz
 
−
* SERDES: Xpress lanes up to 6.25 Gbps
 
−
* All memories you need: on-board NOR and NAND Flash
 
−
* Enabling smarter system thanks to Artix-7 or Kintex-7 FPGA integrated on-chip
 
−
* FPGA banks wide range PSU input from 1.2V to 3.3V
 
−
* Highest security and reliability: internal voltage monitoring and power good enable
 
−
* Reduced carrier complexity: dual CAN, USB, Ethernet GB and native 3.3 V I/O
 
−
* Easy to fit thanks to its small form factor
 
−
* Accurate timing application thanks to on-board 5ppm RTC
 
−
* Pin2Pin Compatibility with BORA SOM based on Zynq XC7Z010/XC7Z020
 
  
 
For detailed information about BORA Xpress, please refer to the [[BORA Xpress SOM]] article.
 
For detailed information about BORA Xpress, please refer to the [[BORA Xpress SOM]] article.
  
−
== BORA Xpress RSS Feed ==
 
−
 
−
Please subscribe to the <newsfeedlink feed="Bora Pages Updates" format="rss">Bora Pages Updates</newsfeedlink> RSS Feed using your favourite RSS reader to be notified on '''wiki pages updates related to BORA'''.
 
−
 
−
Please refer to the [[Dave_Developer's_Wiki_Conventions#Keeping_updated_on_Dave_Developer.27s_wiki_pages.27_modifications | Keeping updated on '''DAVE Embedded Systems''' Developer's wiki pages modifications]] section for further information on how to subscribe to the RSS feed.
 
−
 
−
== BORA Xpress Product Page ==
 
−
Please visit [http://www.dave.eu/products/som/xilinx/zynq-XC7Z015-XC7Z030_bora-xpress BORA Xpress Web Page] for more product information.
 
−
 
−
== BORA Xpress Leaflet ==
 
−
Please download the latest leaflet of BORA Xpress from the following link:[http://www.dave.eu/sites/default/files/files/boraxpress-leaflet.pdf]
 
−
 
−
== BORA Xpress Evaluation Kit ==
 
−
 
−
BORA Evaluation Kit BELK is a development/test board designed to start working with the BORA Xpress platform and experimenting with the implemented features.
 
−
 
−
=== Linux Evaluation Kit ===
 
−
Please refer to [[BELK|this page]] for more details.
 
−
 
−
== BORA Xpress technical details ==
 
−
 
−
=== Introduction ===
 
−
 
−
=== Block diagram ===
 
−
 
−
The following picture shows a simplified block diagram of BORA Xpress module.
 
−
 
−
[[File:BORA-Xpress-bd-1600.png|600px|center]]
 
−
 
−
 
−
=== Product Highlights ===
 
  
 +
== Main Features ==
 
* Unmatched performance thanks to Dual ARM Cortex-A9 @ up to 1GHz
 
* Unmatched performance thanks to Dual ARM Cortex-A9 @ up to 1GHz
 
* SERDES: Xpress lanes up to 6.25 Gbps
 
* SERDES: Xpress lanes up to 6.25 Gbps
Line 83: Line 29:
 
* Pin2Pin Compatibility with BORA SOM based on Zynq XC7Z010/XC7Z020
 
* Pin2Pin Compatibility with BORA SOM based on Zynq XC7Z010/XC7Z020
  
−
=== Feature Summary ===
+
== BORA Xpress technical specification ==
−
 
+
{| class="wikitable outercollapse" | width="100%"
−
{| class="wikitable" |  
+
|
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| align="center" style="background:#f0f0f0;"|'''Feature'''
+
{| class="wikitable mw-collapsible mw-collapsed"
−
| align="center" style="background:#f0f0f0;"|'''Specifications'''
+
! colspan="3" style="text-align:left" | CPU and Memories
−
| align="center" style="background:#f0f0f0;"|'''Options'''
 
 
|-
 
|-
 
| CPU|| Xilinx Dual ARM Cortex-A9 ZYNQ XC7Z015/ZC7Z030 @ up to 1GHz ||
 
| CPU|| Xilinx Dual ARM Cortex-A9 ZYNQ XC7Z015/ZC7Z030 @ up to 1GHz ||
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| Expansion bus|| ||
 
| Expansion bus|| ||
 
|-
 
|-
−
|+ align="bottom" style="caption-side: bottom" | Table: CPU and Memories
 
 
|}
 
|}
  
−
{| class="wikitable" |  
+
{| class="wikitable mw-collapsible mw-collapsed"
 +
! colspan="3" style="text-align:left" | Peripherals
 +
|-
 
| align="center" style="background:#f0f0f0;"|'''Feature'''
 
| align="center" style="background:#f0f0f0;"|'''Feature'''
 
| align="center" style="background:#f0f0f0;"|'''Specifications'''
 
| align="center" style="background:#f0f0f0;"|'''Specifications'''
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| Debug||JTAG IEEE 1149.1 Test Access Port<br>CoreSight™ and Program Trace Macrocell (PTM) ||
 
| Debug||JTAG IEEE 1149.1 Test Access Port<br>CoreSight™ and Program Trace Macrocell (PTM) ||
 
|-
 
|-
−
|+ align="bottom" style="caption-side: bottom" | Table: Peripherals
 
 
|}
 
|}
  
−
{| class="wikitable" |  
+
{| class="wikitable mw-collapsible mw-collapsed"
 +
! colspan="3" style="text-align:left" | Specifications
 +
|-
 
| align="center" style="background:#f0f0f0;"|'''Feature'''
 
| align="center" style="background:#f0f0f0;"|'''Feature'''
−
| colspan="2" align="center" style="background:#f0f0f0;"|'''Specifications'''
+
| align="center" style="background:#f0f0f0;"|'''Specifications'''
 
| align="center" style="background:#f0f0f0;"|'''Options'''
 
| align="center" style="background:#f0f0f0;"|'''Options'''
 
|-
 
|-
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| Differential pairs|| colspan="2" align="center" | Up to 4 PCI Express gen2 ||
 
| Differential pairs|| colspan="2" align="center" | Up to 4 PCI Express gen2 ||
 
|-
 
|-
−
|+ align="bottom" style="caption-side: bottom" | Table: Electrical, Mechanical and Environmental Specifications
 
 
|}
 
|}
  
−
{| class="wikitable" |  
+
{| class="wikitable mw-collapsible mw-collapsed"
 +
! colspan="3" style="text-align:left" | Electrical, mechanical and environmental specification
 +
|-
 
| align="center" style="background:#f0f0f0;"|'''Feature'''
 
| align="center" style="background:#f0f0f0;"|'''Feature'''
 
| align="center" style="background:#f0f0f0;"|'''Specifications'''
 
| align="center" style="background:#f0f0f0;"|'''Specifications'''
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| Connectors||3 x 140 pin 0.6mm pitch ||
 
| Connectors||3 x 140 pin 0.6mm pitch ||
 
|-
 
|-
−
|+ align="bottom" style="caption-side: bottom" | Table: Electrical, Mechanical and Environmental Specifications
+
|}
 +
| [[File:BORA-Xpress-bd-1600.png|300px|center]]
 +
|
 +
* [http://www.dave.eu/products/som/xilinx/zynq-XC7Z015-XC7Z030_bora-xpress BORA Xpress Web Page]
 +
* [http://www.dave.eu/sites/default/files/files/boraxpress-leaflet.pdf BORA Xpress leaflet]
 +
* [http://www.dave.eu/sites/default/files/files/boraxpress-bd.pdf BORA Xpress Block Diagram]
 
|}
 
|}
  
−
=== Hardware ===
+
== Hardware Documentation ==
  
−
Please refer to [[Hardware Manual (BORAXpress)]] for detailed hardware related information on BORA Xpress SOM.
+
{| class="wikitable" |width="100%"
 +
| '''Electrical Schematics'''
 +
|
 +
* [[BORA_Xpress_SOM | Harware Manual]]
 +
* [[BORA_Xpress_SOM#Reset_scheme | Reset Block Diagram]]
 +
* [[RTC_(BORAXpress)|On board RTC specifications]]
 +
* [[Pinout_(BORAXpress)| BORA Xpress Electrical pinout]]
 +
| '''Mechanical Documentation'''
 +
|
 +
* [http://www.dave.eu/sites/default/files/files/BORA-Xpress-dxf.zip BORA Xpress 2D Mechanical Drawing (DXF format)]
 +
* [http://www.dave.eu/sites/default/files/files/BORA-Xpress-stp.zip BORA Xpress 3D Mechanical Drawing (STEP format)]
 +
|'''Carrier Board design'''
 +
|
 +
* [[Carrier_board_design_guidelines_(SOM)| General carrier board design guidelines]]
 +
* [[Integration_guide_(Bora/BoraX)| BORA Xpress specific integration guidelines]]
 +
| '''Thermal & Power Management
 +
|'''
 +
* [[Thermal_management_guidelines | Thermal management guidelines]]
 +
* [[Power_(BORAXpress)| SOM Power Block Diagram ]]
 +
|}
  
−
==== Design Overview ====
+
== Software Documentation ==
  
−
Please refer to [[Design Overview (BORAXpress)|this page]] for more details.
+
{| class="wikitable" | width="100%"
 +
| '''Bootloader'''
 +
|
 +
* [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components | U-boot releases]]
 +
* [[System_boot_and_recovery_via_microSD_card_(BELK) | BORA Xpress Booting options]]
 +
* [[Change_Linux_Command_Line_Parameter_from_U-boot | How to modify Linux parameters in U-Boot]]
 +
| '''Linux'''
 +
|
 +
* [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components | Linux releases]]
 +
* [[Booting_Linux_Kernel | How to boot Linux on DAVE Embedded Systems' SOMs]]
 +
* [[Bora_Embedded_Linux_Kit_(BELK) | DAVE Embedded Systems' Linux Kit]]
 +
* [[BELK/BXELK_Quick_Start_Guide | Embedded Linux Kit Quick Start Guide]]
 +
| '''Vivado'''
 +
|
 +
* [[Programmable_logic_(BORAXpress) | BORA SOM's programmable logic PL]]
 +
* [[Creating_and_building_example_Vivado_project_(BELK) | A project example in Vivado]]
 +
* [[BORAX-TR001-Vivado-serial-IO-analyzer-and-IBERT | Technical Report on Vivado serial IO]]
 +
|}
  
−
==== Mechanicals ====
+
= BORA Xpress Evaluation Kit =
  
−
Please refer to [[Mechanicals (BORAXpress)|this page]] for more details.
+
BoraX Embedded Linux Kit (BXELK for short) is a designed to start working with the BORA Xpress platform and experimenting with the implemented features.
  
−
==== Pinout ====
+
Please refer to [[BoraX_Embedded_Linux_Kit_(BXELK)|this page]] for more details.
  
−
Please refer to [[Pinout (BORAXpress)|this page]] for more details.
+
= Stay tuned with updates: BORA Xpress RSS Feed =
  
−
==== Power ====
+
Please subscribe to the <newsfeedlink feed="Bora Pages Updates" format="rss">Bora Pages Updates</newsfeedlink> RSS Feed using your favourite RSS reader to be notified on '''wiki pages updates related to BORA'''.
  
−
Please refer to [[Power (BORAXpress)|this page]] for more details.
+
Please refer to the [[Dave_Developer's_Wiki_Conventions#Keeping_updated_on_Dave_Developer.27s_wiki_pages.27_modifications | Keeping updated on '''DAVE Embedded Systems''' Developer's wiki pages modifications]] section for further information on how to subscribe to the RSS feed.
−
 
 
−
==== Reset scheme ====
 
−
 
 
−
BORA Xpress provides several different resets signals. Please refer to [[Reset scheme (BORAXpress)|Reset scheme]] for more details.
 
−
 
 
−
==== Processing system (PS) peripherals ====
 
−
 
 
−
Please refer to [[Processing system peripherals (BORAXpress)|this page]] for more details.
 
−
 
 
−
==== Programmable logic (PL) ====
 
−
 
 
−
Please refer to [[Programmable logic (BORAXpress)|this page]] for more details.
 
−
 
 
−
==== RTC ====
 
−
 
 
−
Please refer to [[RTC (BORAXpress)|this page]] for more details.
 
−
 
 
−
==== Thermal IC ====
 
−
 
 
−
Please refer to [[Thermal IC (BORAXpress)|this page]] for more details.
 
−
 
 
−
==== Watchdog ====
 
−
 
 
−
Please refer to [[Watchdog (BORAXpress)|this page]] for more details.
 
  
 +
= Index of topics about BORA Xpress SoM =
  
 
This category collects all the pages specific to BORA Xpress modules and related carrier boards.
 
This category collects all the pages specific to BORA Xpress modules and related carrier boards.

Revision as of 15:48, 4 December 2017


BORA Xpress XILINX Zynq CPU module[edit | edit source]

BORA Xpress.png

BORA Xpress is the top-class Dual Cortex-A9 + FPGA CPU module by DAVE Embedded Systems, based on the recent Xilinx "Zynq" XC7Z015 / XC7Z030 application processor. BORA Xpress offers great computational power, thanks to the rich set of peripherals, the Dual Cortex-A9 and the Artix-7 FPGA inside. BORA Xpress is designed in order to keep full compatibility with the ULTRA Line CPU modules, to guarantee the premium quality and technical value of those customers that require top performances.

The Hardware section provides detailed information about hardware interfaces and characteristics. This document will provide a functional overview of the module and will focus on system-related issues.

For detailed information about BORA Xpress, please refer to the BORA Xpress SOM article.


Main Features[edit | edit source]

  • Unmatched performance thanks to Dual ARM Cortex-A9 @ up to 1GHz
  • SERDES: Xpress lanes up to 6.25 Gbps
  • All memories you need: on-board NOR and NAND Flash
  • Enabling smarter system thanks to Artix-7 or Kintex-7 FPGA integrated on-chip
  • FPGA banks wide range PSU input from 1.2V to 3.3V
  • Highest security and reliability: internal voltage monitoring and power good enable
  • Reduced carrier complexity: dual CAN, USB, Ethernet GB and native 3.3 V I/O
  • Easy to fit thanks to its small form factor
  • Accurate timing application thanks to on-board 5ppm RTC
  • Pin2Pin Compatibility with BORA SOM based on Zynq XC7Z010/XC7Z020

BORA Xpress technical specification[edit | edit source]

CPU and Memories
CPU Xilinx Dual ARM Cortex-A9 ZYNQ XC7Z015/ZC7Z030 @ up to 1GHz
Cache 32 Kbyte instruction, 32 Kbyte data, 512 Kbyte L2 for each core
SDRAM up to 1GB DDR3 @ 533 MHz
NOR Bootable SPI NOR 8, 16 MB
NAND All sizes, on request
External local bus
Expansion bus
Peripherals
Feature Specifications Options
Coprocessors NEON™ & Single / Double Precision
Floating Point for each processor
USB Up to 2x 2.0 OTG ports
UARTs Up to 2x UART ports
GPIO Up to x lines, shared with other functions (interrupts available)
Networks Ethernet 10/100/1000 Mbps
CAN 2x full CAN 2.0B compliant interfaces
SD/MMC 2x SD/SDIO 2.0/MMC3.31 compliant controllers
Serial buses 2x full-duplex SPI ports with three peripheral chip selects
2x master and slave I²C interfaces
Timers 2x triple timers/counters (TTC)
RTC On board (DS3232), external battery powered
Debug JTAG IEEE 1149.1 Test Access Port
CoreSight™ and Program Trace Macrocell (PTM)
Specifications
Feature Specifications Options
FPGA model Artix™-7 (Z-7015) Kintex-7 (Z-7030)
Logic cells 74K 125K
LUTs 46K 78K
Flip flops 92K 157K
RAM 380KB 1060KB
DSP slices 160 400
Differential pairs Up to 4 PCI Express gen2
Electrical, mechanical and environmental specification
Feature Specifications Options
Supply Voltage 3.3V, on-board voltage regulation
Active power consumption Please refer to Power consumption section
Dimensions 85mm x 50mm
Weight
MTBF
Operating temperature 0..70 °C
-40..+85 °C
Connectors 3 x 140 pin 0.6mm pitch
BORA-Xpress-bd-1600.png

Hardware Documentation[edit | edit source]

Electrical Schematics Mechanical Documentation Carrier Board design Thermal & Power Management

Software Documentation[edit | edit source]

Bootloader Linux Vivado

BORA Xpress Evaluation Kit[edit | edit source]

BoraX Embedded Linux Kit (BXELK for short) is a designed to start working with the BORA Xpress platform and experimenting with the implemented features.

Please refer to this page for more details.

Stay tuned with updates: BORA Xpress RSS Feed[edit | edit source]

Please subscribe to the Bora Pages Updates RSS Feed using your favourite RSS reader to be notified on wiki pages updates related to BORA.

Please refer to the Keeping updated on DAVE Embedded Systems Developer's wiki pages modifications section for further information on how to subscribe to the RSS feed.

Index of topics about BORA Xpress SoM[edit | edit source]

This category collects all the pages specific to BORA Xpress modules and related carrier boards.

Pages in category "BoraX"

The following 60 pages are in this category, out of 60 total.

A

B

C

D

F

H

I

L

M

P

R

S

T

W

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