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= BORA Xpress XILINX Zynq CPU module =
[[File:BORA Xpress.png|200px|frameless|border|left]]
BORA Xpress is the top-class Dual Cortex-A9 + FPGA CPU module by DAVE Embedded Systems, based on the recent Xilinx "Zynq" XC7Z015 / XC7Z030 application processor.
BORA Xpress offers great computational power, thanks to the rich set of peripherals, the Dual Cortex-A9 and the Artix-7 FPGA inside.
BORA Xpress is designed in order to keep full compatibility with the ULTRA Line CPU modules, to guarantee the premium quality and technical value of those customers that require top performances.
 
The [[BORA_Xpress_SOM#Hardware | Hardware]] section provides detailed information about hardware interfaces and characteristics. This document will provide a functional overview of the module and will focus on system-related issues.
 
For detailed information about BORA Xpress, please refer to the [[BORA Xpress SOM]] article.
 
== Main Features ==
* Pin2Pin Compatibility with BORA SOM based on Zynq XC7Z010/XC7Z020
For detailed information about == BORA Xpresstechnical specification =={| class="wikitable outercollapse" | width="100%"|{| class="wikitable mw-collapsible mw-collapsed"! colspan="3" style="text-align:left" | CPU and Memories|-| CPU|| Xilinx Dual ARM Cortex-A9 ZYNQ XC7Z015/ZC7Z030 @ up to 1GHz |||-| Cache|| 32 Kbyte instruction, please refer 32 Kbyte data, 512 Kbyte L2 for each core |||-| SDRAM|| up to the [[BORA Xpress SOM]] article.1GB DDR3 @ 533 MHz |||-| NOR|| Bootable SPI NOR 8, 16 MB |||-| NAND|| All sizes, on request |||-| External local bus|| |||-| Expansion bus|| |||-|}
{| class="wikitable mw-collapsible mw-collapsed"! colspan= BORA RSS Feed "3" style="text-align:left" | Peripherals|-| align="center" style="background:#f0f0f0;"|'''Feature'''| align="center" style="background:#f0f0f0;"|'''Specifications'''| align="center" style="background:#f0f0f0;"|'''Options'''|-| Coprocessors|| NEON™ & Single / Double Precision<br>Floating Point for each processor|||-| USB||Up to 2x 2.0 OTG ports |||-| UARTs||Up to 2x UART ports |||-| GPIO||Up to x lines, shared with other functions (interrupts available) |||-| Networks||Ethernet 10/100/1000 Mbps |||-| CAN||2x full CAN 2.0B compliant interfaces |||-| SD/MMC||2x SD/SDIO 2.0/MMC3.31 compliant controllers |||-| Serial buses||2x full-duplex SPI ports with three peripheral chip selects<br>2x master and slave I²C interfaces |||-| Timers||2x triple timers/counters (TTC) |||-| RTC ||On board (DS3232), external battery powered |||-| Debug||JTAG IEEE 1149.1 Test Access Port<br>CoreSight™ and Program Trace Macrocell (PTM) |||-|}
Please subscribe to the <newsfeedlink feed{| class="wikitable mw-collapsible mw-collapsed"! colspan="3" style="text-align:left" | Specifications|-| align="center" style="background:#f0f0f0;"|'''Feature'''| align="center" style="background:#f0f0f0;"|'''Specifications'''| align="Bora Pages Updatescenter" formatstyle="rssbackground:#f0f0f0;">Bora Pages Updates</newsfeedlink> RSS Feed using your favourite RSS reader to be notified on |'''wiki pages updates related to BORAOptions'''.|-| FPGA model||Artix™-7 (Z-7015) || Kintex-7 (Z-7030)|||-| Logic cells||74K || 125K |||-| LUTs||46K || 78K |||-| Flip flops|| 92K || 157K |||-| RAM||380KB || 1060KB |||-| DSP slices|| 160 || 400 |||-| Differential pairs|| colspan="2" align="center" | Up to 4 PCI Express gen2 |||-|}
Please refer to the [[Dave_Developer{| class="wikitable mw-collapsible mw-collapsed"! colspan="3" style="text-align:left" | Electrical, mechanical and environmental specification|-| align="center" style="background:#f0f0f0;"|'''Feature'''s_Wiki_Conventions| align="center" style="background:#Keeping_updated_on_Dave_Developer.27s_wiki_pages.27_modifications f0f0f0;"| Keeping updated on '''DAVE Embedded SystemsSpecifications'''| align="center" style="background:#f0f0f0;"|'''Options'' Developer's wiki pages modifications|-| Supply Voltage|| 3.3V, on-board voltage regulation |||-| Active power consumption|| Please refer to [[Hardware_Manual_(BORAXpress)#Power_consumption | Power consumption]] section for further information on how to subscribe to the RSS feed|||-| Dimensions || 85mm x 50mm |||-| Weight|| |||-| MTBF|| |||-| Operating temperature||0..70 °C<br>-40..+85 °C |||-| Connectors||3 x 140 pin 0.6mm pitch |||-|}| [[File:BORA-Xpress-bd-1600.png|300px|center]]| * [http://www.dave.eu/products/som/xilinx/zynq-XC7Z015-XC7Z030_bora-xpress BORA Xpress Web Page]* [http://www.dave.eu/sites/default/files/files/boraxpress-leaflet.pdf BORA Xpress leaflet]* [http://www.dave.eu/sites/default/files/files/boraxpress-bd.pdf BORA Xpress Block Diagram]|}
== BORA Xpress Product Page Hardware Documentation ==Please visit [http://www.dave.eu/products/som/xilinx/zynq-XC7Z015-XC7Z030_bora-xpress BORA Xpress Web Page] for more product information.
{| class="wikitable" |width= "100%"| '''Electrical Schematics'''|* [[BORA_Xpress_SOM | Harware Manual]]* [[BORA_Xpress_SOM#Reset_scheme | Reset Block Diagram]]* [[RTC_(BORAXpress)|On board RTC specifications]]* [[Pinout_(BORAXpress)| BORA Xpress Leaflet ==Electrical pinout]]| '''Mechanical Documentation'''|Please download the latest leaflet of * [http://www.dave.eu/sites/default/files/files/BORA -Xpress from the following link:-dxf.zip BORA Xpress 2D Mechanical Drawing (DXF format)]* [http://www.dave.eu/sites/default/files/files/boraxpressBORA-Xpress-leafletstp.pdfzip BORA Xpress 3D Mechanical Drawing (STEP format)]|'''Carrier Board design'''| * [[Carrier_board_design_guidelines_(SOM)| General carrier board design guidelines]]* [[Integration_guide_(Bora/BoraX)| BORA Xpress specific integration guidelines]]| '''Thermal & Power Management|''' * [[Thermal_management_guidelines | Thermal management guidelines]]* [[Power_(BORAXpress)| SOM Power Block Diagram ]]|}
== Software Documentation ==
{| class="wikitable" | width="100%"| '''Bootloader'''|* [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components | U-boot releases]]* [[System_boot_and_recovery_via_microSD_card_(BELK) | BORA Xpress Evaluation Booting options]]* [[Change_Linux_Command_Line_Parameter_from_U-boot | How to modify Linux parameters in U-Boot]]| '''Linux'''|* [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components | Linux releases]]* [[Booting_Linux_Kernel | How to boot Linux on DAVE Embedded Systems' SOMs]]* [[Bora_Embedded_Linux_Kit_(BELK) | DAVE Embedded Systems' Linux Kit]]* [[BELK/BXELK_Quick_Start_Guide | Embedded Linux Kit=Quick Start Guide]]| '''Vivado'''| * [[Programmable_logic_(BORAXpress) | BORA SOM's programmable logic PL]]* [[Creating_and_building_example_Vivado_project_(BELK) | A project example in Vivado]]* [[BORAX-TR001-Vivado-serial-IO-analyzer-and-IBERT | Technical Report on Vivado serial IO]]|}
= BORA Xpress Evaluation Kit BELK is a development/test board designed to start working with the BORA Xpress platform and experimenting with the implemented features. The carrier board hosts an BORA Xpress CPU module and offers the following features:=
* 10/100/1000 Ethernet #0 BoraX Embedded Linux Kit (PS)* 10/100/1000 Ethernet #1 (Routed through EMIO)* 1x USB 2.0 OTG (MicroAB connector)* 1x Serial port (RS232 DB9)* 1x MicroSD* External DDR3 SDRAM bank** This memory bank is connected to bank 35 - powered @ 1.5V - that is optimized at PCB level to interface such devices.** This bank is expressly available BXELK for peripherals and/or IPs implemented in FPGA fabric. This solution '''permits these blocks to work without impacting on Bora's DDR3 memory bandwidth'''. To access this bank, MIG (Memory Interface Generator) controller has to be implemented on PL.*** MIG controller requires an external 200 MHz clock source.* State-of-the-art programmable MEMS clock generator (Silicon Labs Si504short): this is an alternative clock source a designed to allow start working with the user to easily experiment his/her own peripherals BORA Xpress platform and IPs on FPGA* XADC** Some signals of Bank 35 can be configured as XADC signalsexperimenting with the implemented features. For this reason they can be routed alternatively to 2.54mm-pitch connectors, instead of DDR3 memory.* JTAG port* Trace port* Socket for [[Wireless_Module_(DWM) | DWM Wireless Module]]* Digilent Pmod™ Compatible expansion connectors* Headers for external for NAND flash and SPI NOR flash* 2.54mm-pitch pin-strip connectors for Bora PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, ..)* Jumpers for voltage selection of the PL banks* +12V power connector
== Linux Evaluation Kit ==Please refer to [[BELKBoraX_Embedded_Linux_Kit_(BXELK)|this page]] for more details.
=Stay tuned with updates: BORA Xpress technical detailsRSS Feed =
Please subscribe to the <newsfeedlink feed="Bora Pages Updates" format="rss">Bora Pages Updates</newsfeedlink> RSS Feed using your favourite RSS reader to be notified on '''wiki pages updates related to BORA'''.
Please refer to the [[Dave_Developer's_Wiki_Conventions#Keeping_updated_on_Dave_Developer.27s_wiki_pages.27_modifications | Keeping updated on '''DAVE Embedded Systems''' Developer's wiki pages modifications]] section for further information on how to subscribe to the RSS feed.
==Block diagram== The following picture shows a simplified block diagram Index of topics about BORA Xpress module.SoM =
[[File:This category collects all the pages specific to BORA-Xpress-bd-1600modules and related carrier boards.png|600px|center]]
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