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= BORA Lite Xilinx ZYNQ XCZ007S/12SXC7Z007S/14S / or XC7Z010 / XC7Z020 020 SOM module =
[[File:BORALite-TOP.png|200px|frameless|border|left]]
[https://www.dave.eu/products/som/xilinx/zynq-XC7Z010-XC7Z020_bora BORA Lite] is the updated version of BORA SOM in a more compact and convenient form factor SODIMM DDR3 204pins.
This new top-class Single/Dual Cortex-A9 + FPGA CPU module by DAVE Embedded Systems is based on the recent Xilinx Zynq XC7Z007S/012S/014S or XC7Z010/XC7Z020 020 application processor.
Thanks to BORA Lite, customers are going to save time and resources by using a compact solution that includes both a CPU and an FPGA, avoiding complexities on the carrier PCB. Additionally, thanks to SODIMM form factor this solution represent the cheapest way to integrate a Zynq SOC in an embedded design.
| align="center" style="background:#f0f0f0;"|'''Options'''
|-
| CPU||Xilinx Single/Dual ARM Cortex-A9<br>ZYNQ XC7Z007S/012S014S 014S or XC7Z010/ZC7Z020 @ 800MHz ||
|-
| Cache||L1: 32Kbyte instruction, 32Kbyte data<br>L2: 512Kbyte for each core ||
| '''Electrical Schematics'''
|
* [[Hardware Manual Design_Overview_(BoraLite) | Design Overview]]* [[Processing_system_peripherals_(BoraLite) | Processing System (PS) pheripherals]]* [[Programmable_logic_(BoraLite) | Programmable Logic (PL)]]
* [[Reset_scheme_(Bora/BoraLite)| Reset Block Diagram]]
* [[RTC (Bora)|On board RTC specifications]]
| '''Mechanical Documentation'''
|
* [https://wwwmirror.dave.eu/sitesbora/defaulthw/filesBoraXEVB/files/boraLiteboraxevb-2D-CS143714.dxf.zip BORA 2D Mechanical Drawing (DXF format)]* [https://wwwmirror.dave.eu/systembora/fileshw/area-riservataBoraXEVB/boraLite_stpboraxevb_3D_step_cs143714.zip BORA 3D Mechanical Drawing (STEP format)]
|'''Carrier Board design'''
|
* [https://mirror.dave.eu/bora/hw/BoraXEVB/S-EVBBX0000C0R-1.6.1_color.pdf Carrier board electrical schematics]
* [[Carrier_board_design_guidelines_(SOM) | General carrier board design guidelines]]
* [[Integration_guide_(Bora/BoraX/BoraLite)|BORA Lite specific integration guidelines]]
* [[Physical_devices_mapping_(BELK/BXELK) | Device mapping (Evaluation Kit BELK/BXELK)]]
| '''Thermal & Power Management
|'''
