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Carrier board design guidelines (SOM)

61 bytes added, 09:52, 23 October 2012
Case #2: PHY is not integrated on SOM and a RGMII PHY is used
* If less than minimum gap is used, use a GND trace for improve trace separation
==== Case #2: PHY is not integrated on SOM and a RGMII PHY is used ====
This section refers to the case of :* PHY not integrated on SOM * Gigabit PHY populated on carrier board and interfaced connected to SOM through RGMII (this interface.Tthis solution is implemented on [[NaonEVB-Mid]] for example).
===== Schematics =====
* Add series resistors (RPACK resistors recommended) to RGMII lines

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